M34F04-WMN6TP

M34F04 4-Kbit serial I2C bus EEPROM with write control of the top half of memory Datasheet − production data Features • Two-wire I2C serial interface supports • 400 kHz protocol • Single supply voltage – 2.5 to 5.5 V • Write control of the top half of memory (addresses 100h to 1FFh) • Byte and Page Write (up to 16 Bytes) SO8 (MN) 150 mil width • Random and Sequential Read modes • Self-timed programming cycle • Automatic address incrementing • Enhanced ESD/latch-up behavior • More than 1 million erase/write cycles • More than 40 year data retention • Package – SO8 ECOPACK®2 May 2015 This is information on a product in full production. DocID11090 Rev 4 1/26 www.st.com Contents M34F04 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Chip enable (E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Write control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5.1 3 2.5.2 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5.3 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.8 Page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.9 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 14 3.10 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.11 Random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.12 Current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.13 Sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.14 Acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/26 DocID11090 Rev 4 M34F04 7 Contents Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DocID11090 Rev 4 3/26 3 List of tables M34F04 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. 4/26 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DocID11090 Rev 4 M34F04 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write mode sequences, to addresses in the top half, with WC=1 (data write inhibited) . . . 12 Write mode sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Maximum RL value versus bus capacitance (CBUS) for an I2C bus . . . . . . . . . . . . . . . . . 21 SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 22 SO8N – 8-lead plastic small outline, 150 mils body width, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DocID11090 Rev 4 5/26 5 Description 1 M34F04 Description The M34F04 is an electrically erasable programmable memory (EEPROM), organized as 512 x 8. The upper half (1FFh to 100h) of the memory array can be protected from inadvertent write operations by driving High the WC pin. Figure 1. Logic diagram 6##  % % 3#, 3$! -& 7# 633 !) These devices are compatible with the I2C memory protocol. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The devices carry a built-in 4bit Device Type Identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and RW bit (as described in Table 2), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. Table 1. Signal names Name 6/26 Definition E1, E2 Chip Enable SDA Serial Data SCL Serial Clock WC Write Control VCC Supply Voltage VSS Ground DocID11090 Rev 4 M34F04 Description Figure 2. SO connections -& .# % % 633         6## 7# 3#, 3$! !) NC = Not Connected See Section 7: Package mechanical data for package dimensions, and how to identify pin-1. DocID11090 Rev 4 7/26 25 Signal description M34F04 2 Signal description 2.1 Serial clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to VCC. (Figure 10 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 Serial data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 10 indicates how the value of the pull-up resistor can be calculated). 2.3 Chip enable (E1, E2) These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2) of the 7-bit Device Select Code. These inputs must be tied to VCC or VSS, to establish the Device Select Code. 2.4 Write control (WC) This input signal is useful for protecting half of the memory from inadvertent write operations. Write operations are disabled to the upper half (1FFh to 100h) of the memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and Write operations are allowed. When attempting to write in the upper half of the memory, while Write Control (WC) is being driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged. 8/26 DocID11090 Rev 4 M34F04 Signal description 2.5 Supply voltage (VCC) 2.5.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage must be applied: this voltage must be a DC voltage within the specified [VCC(min), VCC(max)] range as defined in Table 5. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). 2.5.2 Internal device reset In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise of VCC), the device will not respond to any instruction until VCC has reached the Power On Reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Section 6: DC and AC parameters). When VCC has passed the POR threshold voltage, the device is reset and in the Standby Power mode. 2.5.3 Power-down At power-down (where VCC decreases continuously), as soon as VCC drops from the normal operating voltage to below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it. Figure 3. I2C bus protocol 3#, 3$! 3$! )NPUT 34!24 #ONDITION 3#,  3$! -3"  3$! #HANGE 34/0 #ONDITION     !#+ 34!24 #ONDITION 3#,  3$! -3"      !#+ 34/0 #ONDITION !)" DocID11090 Rev 4 9/26 25 Device operation 3 M34F04 Device operation The device supports the I2C protocol. This is summarized in Figure 3. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24Cxx device is always a slave in all communication. 3.1 Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. 3.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle. 3.3 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. 3.4 Data input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low. 10/26 DocID11090 Rev 4 M34F04 3.5 Device operation Memory addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The Device Select Code consists of a 4-bit Device Type Identifier, and a 2-bit Chip Enable “Address” (E2, E1). To address the memory array, the 4-bit Device Type Identifier is 1010b. Table 2. Device select code Device Type Identifier(1) Chip Enable(2)(3) RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 E2 E1 A8 RW Device Select Code 1. The most significant bit, b7, is sent first. 2. E1 and E2 are compared against the respective external pins on the memory device. 3. A8 represents most significant bits of the address. When the Device Select Code is received on Serial Data (SDA), the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Stand-by mode. Using the E1 and E2 inputs pins, up to four M34F04 devices can be connected to one I2C bus. Table 3. Operating modes Mode Current Address Read RW bit WC (1) Bytes 1 X 0 X 1 X Sequential Read 1 X ≥1 Byte Write (upper addresses) 0 VIL or Z 1 START, Device Select, RW = 0 Byte Write (lower addresses) 0 X 1 START, Device Select, RW = 0 Page Write (upper addresses) 0 VIL or Z ≤16 START, Device Select, RW = 0 Page Write (lower addresses) 0 X ≤16 START, Device Select, RW = 0 Random Address Read 1 Initial Sequence 1 START, Device Select, RW = 1 START, Device Select, RW = 0, Address reSTART, Device Select, RW = 1 Similar to Current or Random Address Read 1. Z = unconnected and floating X = VIH or VIL or unconnected and floating. DocID11090 Rev 4 11/26 25 Device operation M34F04 Figure 4. Write mode sequences, to addresses in the top half, with WC=1 (data write inhibited) 7# !#+ "94%!$$2 ./!#+ $!4!). 34/0 $%63%, 34!24 "YTE7RITE !#+ 27 7# !#+ $%63%, 34!24 0AGE7RITE !#+ "94%!$$2 ./!#+ $!4!). ./!#+ $!4!). $!4!). 27 7#CONTgD ./!#+ $!4!).. 34/0 0AGE7RITE CONTgD ./!#+ !)# 3.6 Write operations Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 5, and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and the device does not respond to any requests. 3.7 Byte write After the Device Select code and the address byte, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High (during the period from the Start condition until the end of the address byte), the device replies to the data byte with NoAck, as shown in Figure 4, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 5. 12/26 DocID11090 Rev 4 M34F04 Page write The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If the addressed location is Write-protected, by Write Control (WC) being driven High (during the period from the Start condition until the end of the address byte), the device replies to the data bytes with NoAck, as shown in Figure 4, and the locations are not modified. After each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. Figure 5. Write mode sequences with WC=0 (data write enabled) 7# !#+ !#+ "94%!$$2 !#+ $!4!). 34/0 $%63%, 34!24 "94%72)4% 27 7# !#+ 0!'%72)4% $%63%, 34!24 !#+ "94%!$$2 !#+ $!4!). !#+ $!4!). $!4!). 27 7#CONTgD !#+ 0!'%72)4% CONTgD !#+ $!4!).. 34/0 3.8 Device operation !)" DocID11090 Rev 4 13/26 25 Device operation M34F04 Figure 6. Write cycle polling flowchart using ACK 72)4%#YCLE IN0ROGRESS 34!24#ONDITION $%6)#%3%,%#4 WITH27 ./ !#+ 2ETURNED &IRSTBYTEOFINSTRUCTION WITH27ALREADY DECODEDBYTHEDEVICE 9%3 ./ .EXT /PERATIONIS !DDRESSINGTHE -EMORY 9%3 3END!DDRESS AND2ECEIVE!#+ 2E34!24 ./ 34/0 34!24 #ONDITION 9%3 $!4!FORTHE 72)4%/PERATION $%6)#%3%,%#4 WITH27 #ONTINUETHE 72)4%/PERATION #ONTINUETHE 2ANDOM2%!$/PERATION !)# 3.9 Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 9, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 6, is: 14/26 • Initial condition: a Write cycle is in progress. • Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). • Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). DocID11090 Rev 4 M34F04 Device operation Figure 7. Read mode sequences !#+ $!4!/54 34/0 34!24 $%63%, ./!#+ 27 !#+ 34!24 $%63%, !#+ "94%!$$2 27 !#+ 34!24 $%63%, $!4!/54 27 !#+ !#+ $!4!/54 ./!#+ $!4!/54. 27 !#+ 34!24 $%63%, !#+ "94%!$$2 27 !#+ !#+ $%63%, 34!24 3%15%.4)!, 2!.$/2%!$ $%63%, ./!#+ 34/0 3%15%.4)!, #522%.4 2%!$ !#+ 34!24 2!.$/!$$2%33 2%!$ 34/0 #522%.4 !$$2%33 2%!$ !#+ $!4!/54 27 ./!#+ 34/0 $!4!/54. !) Note: The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 3rd bytes) must be identical. 3.10 Read operations Read operations are performed independently of the state of the Write Control (WC) signal. 3.11 Random address read A dummy Write is performed to load the address into the address counter (as shown in Figure 7) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. DocID11090 Rev 4 15/26 25 Device operation 3.12 M34F04 Current address read The device has an internal address counter which is incremented each time a byte is read. For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the RW bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 7, without acknowledging the byte. 3.13 Sequential read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 7. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h. 3.14 Acknowledge in read mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Stand-by mode. 16/26 DocID11090 Rev 4 M34F04 4 Initial delivery state Initial delivery state The device is delivered with all bits in the memory array set to 1 (each Byte contains FFh). DocID11090 Rev 4 17/26 25 Maximum ratings 5 M34F04 Maximum ratings Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Table 4. Absolute maximum ratings Symbol TA TSTG TLEAD Parameter Min. Max. Unit Ambient Operating Temperature –40 125 °C Storage Temperature –65 150 °C Load temperature during soldering see note(1) °C VIO Input or Output range –0.50 6.5 V VCC Supply Voltage –0.50 6.5 V VESD Electrostatic Discharge Voltage (Human Body model)(2) –3000 3000(3) V 1. Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS directive 2011/65/EU of July 2011). 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω) 3. 4000 V for products identified with process letter S or G 18/26 DocID11090 Rev 4 M34F04 6 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 5. Operating conditions Symbol VCC TA Parameter Min. Max. Unit Supply Voltage 2.5 5.5 V Ambient Operating Temperature –40 85 °C Max. Unit Table 6. AC measurement conditions Symbol CL Parameter Min. Load Capacitance 100 Input Rise and Fall Times pF 50 ns Input Levels 0.2VCC to 0.8VCC V Input and Output Timing Reference Levels 0.3VCC to 0.7VCC V Figure 8. AC measurement I/O waveform )NPUT,EVELS )NPUTAND/UTPUT 4IMING2EFERENCE,EVELS 6## 6## 6## 6## !)" Table 7. Input parameters Symbol Parameter(1)(2) Test condition Min. Max. Unit CIN Input Capacitance (SDA) 8 pF CIN Input Capacitance (other pins) 6 pF 70 kΩ ZWCL WC Input Impedance VIN < 0.3VCC 5 ZWCH WC Input Impedance VIN > 0.7VCCs 500 Pulse width ignored (Input Filter on SCL and SDA) Single glitch tNS kΩ 100 ns 1. TA = 25 °C, f = 400 kHz 2. Sampled only, not 100% tested. DocID11090 Rev 4 19/26 25 DC and AC parameters M34F04 Table 8. DC characteristics Symbol Test condition (in addition to those in Table 5) Parameter ILI Input Leakage Current (SCL, SDA) ILO Output Leakage Current ICC Supply Current ICC1 Stand-by Supply Current VIL Input Low Voltage (E2, E1, SCL, SDA) VIH Input High Voltage (E2, E1, SCL, SDA, WC) VOL Output Low Voltage Min. Max. Unit VIN = VSS or VCC ±2 µA VOUT = VSS or VCC, SDA in Hi-Z ±2 µA VCC =2.5V, fc=400kHz (rise/fall time < 30ns) 1 mA VIN = VSS or VCC, VCC = 2.5 V 2(1) µA –0.3 0.3VCC V 0.7VCC VCC+1 V 0.4 V IOL = 2.1 mA, VCC = 2.5 V 1. 0.5 µA for products identified with process letters S or G Table 9. AC characteristics Test conditions specified in Table 5 and Table 6 Symbol Alt. fC fSCL Clock Frequency tCHCL tHIGH Clock Pulse Width High 600 ns tCLCH tLOW Clock Pulse Width Low 1300 ns tDL1DL2 (1) tF Parameter Max. Unit 400 kHz SDA Fall Time 20 100 ns 0 ns 100 ns tDXCX tSU:DAT Data In Set Up Time tCLDX tHD:DAT Data In Hold Time tCLQX tDH Data Out Hold Time tCLQV(2) tAA Clock Low to Next Data Valid (Access Time) (3) Min. 300 900 ns ns tSU:STA Start Condition Set Up Time 600 ns tDLCL tHD:STA Start Condition Hold Time 600 ns tCHDH tSU:STO Stop Condition Set Up Time 600 ns tDHDL tBUF Time between Stop Condition and Next Start Condition 1300 ns tW tWR Write Time tCHDX 5 ms 1. Sampled only, not 100% tested. 2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 3. For a reSTART condition, or following a Write cycle. 20/26 DocID11090 Rev 4 M34F04 DC and AC parameters Figure 9. AC waveforms T#(#, T#,#( 3#, T$,#, 3$!)N T#($8 T#,$8 34!24 #ONDITION 3$! )NPUT 3$! T$8#8 #HANGE T#($( T$($, 34!24 34/0 #ONDITION #ONDITION 3#, 3$!)N T#($( T#($8 T7 34/0 #ONDITION 7RITE#YCLE 34!24 #ONDITION 3#, T#,16 3$!/UT T#,18 $ATA6ALID !)# Figure 10. Maximum RL value versus bus capacitance (CBUS) for an I2C bus 6## -AXIMUM20VALUEK½   2,  2, 3$! -!34%2  FCK(Z  FCK(Z #"53 3#, #"53     #"53P& !) DocID11090 Rev 4 21/26 25 Package mechanical data 7 M34F04 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 SO8N package information Figure 11. SO8N – 8-lead plastic small outline, 150 mils body width, package outline K[Û $ $ F FFF E H PP *$8*(3/$1( ' N  ( (  $ / / 62$B9 1. Drawing is not to scale. Table 10. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data inches(1) millimeters Symbol 22/26 Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.170 - 0.230 0.0067 - 0.0091 D 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 DocID11090 Rev 4 M34F04 Package mechanical data Table 10. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. Figure 12. SO8N – 8-lead plastic small outline, 150 mils body width, package recommended footprint   [  2B621B)3B9 1. Dimensions are expressed in millimeters. DocID11090 Rev 4 23/26 25 Part numbering 8 M34F04 Part numbering Table 11. Ordering information scheme Example: M34 F04 Device type M34 = I2C serial access EEPROM (ASSP) Device function 04 = 4 Kbit (512 x 8) Operating voltage W = VCC = 2.5 to 5.5V (400 kHz) Package MN = SO8 (150 mil width) Temperature range 6 = –40 to 85 °C Option T = Tape & reel packing Plating technology blank = Standard SnPb plating P or G = ECOPACK® (RoHs compliant) 24/26 DocID11090 Rev 4 – W MN 6 T P M34F04 9 Revision history Revision history Table 12. Document revision history Date 23-Jan-2004 24-Jan-2006 14-Feb-2013 14-May-2015 Version 1.0 Description Document written 2 Document status promoted from Preliminary data to full Datasheet. SO8 package specifications updated (see Table 10. and Figure 12.). SO8 package is compliant with ST ECOPACK® specifications. “Power On Reset” paragraph removed from below SUMMARY DESCRIPTION. Supply voltage (VCC) paragraph added to SIGNAL DESCRIPTION section. Table 4: Absolute maximum ratings updated. 3 Document reformatted. Updated the title and features list on cover page. Added the sentence “The upper half... WC pin” in Section 1: Description. Moved Table 2: Device select code to Section 3.5: Memory addressing. Updated the VESD minimum/maximum values and added a note in Table 4: Absolute maximum ratings. Updated the ICC1 maximum value and added a note in Table 8: DC characteristics. Updated the tCLQX and tCLQV minimum values in Table 9: AC characteristics. Moved Figure 10: Maximum RL value versus bus capacitance (CBUS) for an I2C bus to Section 6: DC and AC parameters. Updated Figure 11: SO8N – 8-lead plastic small outline, 150 mils body width, package outline and Table 10: SO8N – 8-lead plastic small outline, 150 mils body width, package data. Moved ECOPACK mention to Section 8. Removed notes below Table 11: Ordering information scheme. 4 Updated: – Features; – Disclaimer: Removed military warning; – Section 7: Package mechanical data; – Figure 11: SO8N – 8-lead plastic small outline, 150 mils body width, package outline; – Table 10: SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data Added: – TLEAD inside Table 4: Absolute maximum ratings; – Table 12: SO8N – 8-lead plastic small outline, 150 mils body width, package recommended footprint. DocID11090 Rev 4 25/26 25 M34F04 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 26/26 DocID11090 Rev 4