M36DR432A100ZA6C

M36DR432A M36DR432B 32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory and 4 Mbit (256K x16) SRAM, Multiple Memory Product FEATURES SUMMARY s SUPPLY VOLTAGE – VDDF = VDDS =1.65V to 2.2V s s s Figure 1. Packages – VPPF = 12V for Fast Program (optional) ACCESS TIME: 100,120ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code, M36DR432A: 00A0h – Bottom Device Code, M36DR432B: 00A1h FBGA FLASH MEMORY s 32 Mbit (2Mb x16) BOOT BLOCK – Parameter Blocks (Top or Bottom Location) s Stacked LFBGA66 (ZA) 8 x 8 ball array PROGRAMMING TIME – 10µs typical – Double Word Programming Option s ASYNCRONOUS PAGE MODE READ – Page width: 4 Word – Page Mode Access Time: 35ns s DUAL BANK OPERATION – Read within one Bank while Program or Erase within the other – No Delay between Read and Write Operations s BLOCK PROTECTION ON ALL BLOCKS – WPF for Block Locking COMMON FLASH INTERFACE – 64 bit Security Code s s s s SRAM 4 Mbit (256K x 16 bit) LOW VDDS DATA RETENTION: 1V POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS November 2001 1/46 M36DR432A, M36DR432B DESCRIPTION The M36DR432 is a multichip memory device containing a 32 Mbit boot block Flash memory and a 4 Mbit of SRAM. The device is offered in a Stacked LFBGA66 (0.8 mm pitch) package. The two components are distinguished by use with three chip enable inputs: EF for the Flash memory and, E1S and E2S for the SRAM. The two components are also separately power supplied and grounded. Figure 2. Logic Diagram VSSF Table 1. Signal Names A0-A17 A18-A20 DQ0-DQ15 VDDF VPPF Address Inputs Address Inputs for Flash Chip only Data Input/Output Flash Power Supply Flash Optional Supply Voltage for Fast Program & Erase Flash Ground SRAM Power Supply SRAM Ground Not Connected Internally VDDF VPPF VDDS 21 A0-A20 EF GF WF RPF WPF E1S E2S GS WS UBS LBS M36DR432A M36DR432B 16 DQ0-DQ15 VDDS VSSS NC Flash control functions EF GF WF RPF WPF Chip Enable input Output Enable input Write Enable input Reset input Write Protect input SRAM control functions E1S, E2S GS WS UBS Chip Enable input Output Enable input Write Enable input Upper Byte Enable input Lower Byte Enable input VSSF VSSS AI90203 LBS 2/46 M36DR432A, M36DR432B Figure 3. LFBGA Connections (Top view through package) #1 #2 1 2 3 4 5 6 7 8 #3 #4 A NC NC A20 A11 A15 A14 A13 A12 VSSF NC NC NC B A16 A8 A10 A9 DQ15 WS DQ14 DQ7 C WF NC DQ13 DQ6 DQ4 DQ5 D VSSS RPF DQ12 E2S VDDS VDDF E WPF VPPF A19 DQ11 DQ10 DQ2 DQ3 F LBS UBS GS DQ9 DQ8 DQ0 DQ1 G A18 A17 A7 A6 A3 A2 A1 E1S H NC NC NC A5 A4 A0 EF VSSF GF NC NC NC AI90204 3/46 M36DR432A, M36DR432B Table 2. Absolute Maximum Ratings (1) Symbol TA TBIAS TSTG VIO (2) VDDF VDDS VPPF Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Flash Chip Supply Voltage SRAM Chip Supply Voltage Program Voltage (3) Value –40 to 85 –40 to 125 –55 to 150 –0.2 to VDD(4) + 0.3 –0.5 to 2.7 –0.2 to 2.6 –0.5 to 13.0 Unit °C °C °C V V V V Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum voltage may undershoot to –2V during transition and for less than 20ns. 3. Depends on range. 4. VDD = VDDS = VDDF. Figure 4. Functional Block Diagram VDDF VPPF EF GF WF RPF WPF A18-A20 A0-A17 Flash Memory 32 Mbit (x16) VDDS VSSF DQ0-DQ15 E1S E2S GS WS UBS LBS SRAM 4 Mbit (x16) VSSS AI90205 4/46 M36DR432A, M36DR432B SIGNAL DESCRIPTIONS See Figure 2 and Table 1. Address Inputs (A0-A17). Addresses A0 to A17 are common inputs for the Flash chip and the SRAM chip. The address inputs for the Flash memory are latched during a write operation on the falling edge of the Flash Chip Enable (EF) or Write Enable (WF), while address inputs for the SRAM array are latched during a write operation on the falling edge of the SRAM Chip Enable lines (E1S or E2S) or Write Enable (WS). Address Inputs (A18-A20). Address A18 to A20 are address inputs for the Flash chip. They are latched during a write operation on the falling edge of Flash Chip Enable (EF) or Write Enable (WF). Data Input/Outputs (DQ0-DQ15). The input is data to be programmed in the Flash or SRAM memory array or a command to be written to the C.I. of the Flash chip. Both are latched on the rising edge of Flash Chip Enable (EF) or Write Enable (WF) and, SRAM Chip Enable lines (E1S or E2S) or Write Enable (WS). The output is data from the Flash memory or SRAM array, the Electronic Signature Manufacturer or Device codes or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Flash Chip Enable (EF) and Output Enable (GF) or SRAM Chip Enable lines (E1S or E2S) and Output Enable (GS) are active. The output is high impedance when the both the Flash chip and the SRAM chip are deselected or the outputs are disabled and when Reset (RPF) is at a VIL. Flash Chip Enable (EF). The Chip Enable input for Flash activates the memory control logic, input buffers, decoders and sense amplifiers. EF at VIH deselects the memory and reduces the power consumption to the standby level and output do Hi-Z. EF can also be used to control writing to the command register and to the Flash memory array, while WF remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. Flash Write Enable (WF). The Write Enable input controls writing to the Command Register of the Flash chip and Address/Data latches. Data are latched on the rising edge of WF. Flash Output Enable (GF). The Output Enable gates the outputs through the data buffers during a read operation of the Flash chip. When GF and WF are High the outputs are High impedance. Flash Reset/Power Down Input (RPF). The RPF input provides hardware reset of the memory (without affecting the Configuration Register status), and/or Power Down functions, depending on the Configuration Register status. Reset/Power Down of the memory is achieved by pulling RPF to VIL for at least tPLPH. When the reset pulse is giv- en, if the memory is in Read, Erase Suspend Read or Standby, it will output new valid data in tPHQ7V1 after the rising edge of RPF. If the memory is in Erase or Program modes, the operation will be aborted and the reset recovery will take a maximum of tPLQ7V. The memory will recover from Power Down (when enabled) in tPHQ7V2 after the rising edge of RPF. See Tables 1, 26 and Figure 11. Flash Write Protect (WPF). Write Protect is an input to protect or unprotect the two lockable parameter blocks of the Flash memory. When WPF is at VIL, the lockable blocks are protected. Program or erase operations are not achievable. When WPF is at VIH, the lockable blocks are unprotected and they can be programmed or erased (refer to Table 17). SRAM Chip Enable (E1S, E2S). The Chip Enable inputs for SRAM activate the memory control logic, input buffers and decoders. E1S at VIH or E2S at VIL deselects the memory and reduces the power consumption to the standby level. E1S and E2S can also be used to control writing to the SRAM memory array, while WS remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. SRAM Write Enable (WS). The Write Enable input controls writing to the SRAM memory array. WS is active low. SRAM Output Enable (GS). The Output Enable gates the outputs through the data buffers during a read operation of the SRAM chip. GS is active low. the SRAM Upper Byte Enable (UBS). Enable upper bytes for SRAM (DQ8-DQ15). UBS is active low. SRAM Lower Byte Enable (LBS). Enable the lower bytes for SRAM (DQ0-DQ7). LBS is active low. VDDF Supply Voltage (1.65V to 2.2V). Flash memory power supply for all operations (Read, Program and Erase). VPPF Programming Voltage (11.4V to 12.6V). Used to provide high voltage for fast factory programming. High voltage on VPPF pin is required to use the Double Word Program instruction. It is also possible to perform word program or erase instructions with VPPF pin grounded. VDDS Supply Voltage (1.65V to 2.2V). SRAM power supply for all operations (Read, Program). VSSF and VSSS Ground. VSSF and VSSS are the reference for all voltage measurements respectively in the Flash and SRAM chips. 5/46 M36DR432A, M36DR432B Table 3. Main Operation Modes Operation Mode Read Write Block Locking Standby Reset Output Disable Read Write EF VIL VIL VIL VIH X VIL GF VIL VIH X X X VIH WF VIH VIL X X X VIH RPF VIH VIH VIH VIH VIL VIH WPF X VIH VIL X X X VPPF Don't care VCCF or VPPFH Don't care Don't care Don't care Don't care VIL VIL VIH Any Flash mode is allowable X X VIH Data Retention Any Flash mode is allowable X X Output Disable Any Flash mode is allowable VIL E1S E2S GS WS UBS, LBS (1) DQ15-DQ0 Data Output Data Input X Hi-Z Hi-Z Hi-Z Data out Word Read Data in Word Write Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z SRAM must be disabled SRAM must be disabled SRAM must be disabled Any SRAM mode is allowable Any SRAM mode is allowable Any SRAM mode is allowable VIH VIH X VIL X X VIL X VIH VIL VIH X X X X X X VIH VIH VIL X X X X X X VIH VIL VIL X X VIH X X VIH X Flash Memory Flash must be disabled Flash must be disabled Note: X = VIL or VIH, VPPFH = 12V ± 5%. 1. If UBS and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately. 6/46 SRAM Standby/ Power Down M36DR432A, M36DR432B FLASH MEMORY COMPONENT Organization The Flash Chip is organized as 2Mb x16 bits. A0A20 are the address lines, DQ0-DQ15 are the Data Input/Output. Memory control is provided by Chip Enable EF, Output Enable GF and Write Enable WF inputs. Reset RPF is used to reset all the memory circuitry and to set the chip in power down mode if this function is enabled by a proper setting of the Configuration Register. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, DQ6 and DQ2 provide Toggle signals and DQ5 provides error bit to indicate the state of the P/E.C operations. Memory Blocks The device features asymmetrically blocked architecture. The Flash Chip has an array of 71 blocks and is divided into two banks A and B, providing Dual Bank operations. While programming or erasing in Bank A, read operations are possible into Bank B or vice versa. The memory also features an erase suspend allowing to read or program in another block within the same bank. Once suspended the erase can be resumed. The Bank Size and Sectorization are summarized in Table 4. Parameter Blocks are located at the top of the memory address space for the Top version, and at the bottom for the Bottom version. The memory maps are shown in Tables 5, 6, 7 and 8. The Program and Erase operations are managed automatically by the P/E.C. Block protection against Program or Erase provides additional data security. All blocks are protected at Power Up. Instructions are provided to protect or unprotect any block in the application. A second register locks the protection status while WPF is low (see Block Locking description). The Reset command does not affect the configuration of unprotected blocks and the Configuration Register status. Device Operations The following operations can be performed using the appropriate bus cycles: Read Array (Random, and Page Modes), Write command, Output Disable, Standby, Reset/Power Down and Block Locking. See Table 9. Read. Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register, the CFI, the Block Protection Status or the Configuration Register status. Read operation of the memory array is performed in asynchronous page mode, that provides fast access time. Data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by A0-A1 address inputs. Read operations of the Electronic Signature, the Status Register, the CFI, the Block Protection Status, the Configuration Register status and the Security Code are performed as single asynchronous read cycles (Random Read). Both Chip Enable EF and Output Enable GF must be at VIL in order to read the output of the memory. Write. Write operations are used to give Instruction Commands to the memory or to latch Input Data to be programmed. A write operation is initiated when Chip Enable EF and Write Enable WF are at VIL with Output Enable GF at VIH. Addresses are latched on the falling edge of WF or EF whichever occurs last. Commands and Input Data are latched on the rising edge of WF or EF whichever occurs first. Noise pulses of less than 5ns typical on EF, WF and GF signals do not start a write cycle. Dual Bank Operations. The Dual Bank allows to read data from one bank of memory while a program or erase operation is in progress in the other bank of the memory. Read and Write cycles can be initiated for simultaneous operations in different banks without any delay. Status Register during Program or Erase must be monitored using an address within the bank being modified. Output Disable. The data outputs are high impedance when the Output Enable GF is at VIH with Write Enable WF at VIH. Standby. The memory is in standby when Chip Enable EF is at VIH and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable GF or Write Enable WF inputs. Automatic Standby. When in Read mode, after 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus. Power Down. The memory is in Power Down when the Configuration Register is set for Power Down and RPF is at VIL. The power consumption is reduced to the Power Down level, and Outputs are in high impedance, independent of the Chip Enable EF, Output Enable GF or Write Enable WF inputs. Block Locking. Any combination of blocks can be temporarily protected against Program or Erase by setting the lock register and pulling WPF to VIL (see Block Lock instruction). 7/46 M36DR432A, M36DR432B Table 4. Bank Size and Sectorization Bank Size Bank A Bank B 4 Mbit 28 Mbit Parameter Blocks 8 blocks of 4 KWord Main Blocks 7 blocks of 32 KWord 56 blocks of 32 KWord Table 5. Bank A, Top Boot Block Addresses M36DR432A # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Size (KWord) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 Address Range 1FF000h-1FFFFFh 1FE000h-1FEFFFh 1FD000h-1FDFFFh 1FC000h-1FCFFFh 1FB000h-1FBFFFh 1FA000h-1FAFFFh 1F9000h-1F9FFFh 1F8000h-1F8FFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 000000h-007FFFh Table 6. Bank B, Top Boot Block Addresses M36DR432A # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 8/46 M36DR432A, M36DR432B Table 7. Bank B, Bottom Boot Block Addresses M36DR432B # 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh # 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh Table 8. Bank A, Bottom Boot Block Addresses M36DR432B Size (KWord) 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Address Range 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 007000h-007FFFh 006000h-006FFFh 005000h-005FFFh 004000h-004FFFh 003000h-003FFFh 002000h-002FFFh 001000h-001FFFh 000000h-000FFFh 9/46 M36DR432A, M36DR432B Table 9. User Bus Operations (1) Operation Write Output Disable Standby Reset / Power Down Block Locking Note: 1. X = Don't care. EF VIL VIL VIH X VIL GF VIH VIH X X X WF VIL VIH X X X RPF VIH VIH VIH VIL VIH WPF VIH VIH VIH VIH VIL DQ0-DQ15 Data Input Hi-Z Hi-Z Hi-Z X Table 10. Read Electronic Signature (AS and Read CFI instructions) Code Manufacturer Code M36DR432A Device Code M36DR432B VIL VIL VIH VIH VIL 0 Don't Care A1h 00h Device EF VIL VIL GF VIL VIL WF VIH VIH A0 VIL VIH A1 VIL VIL A2-A7 0 0 Other DQ0-DQ7 DQ8-DQ15 Addresses Don't Care Don't Care 20h A0h 00h 00h Table 11. Read Block Protection (AS and Read CFI instructions) Block Status Protected Block Unprotected Block Locked Block EF VIL VIL VIL GF VIL VIL VIL WF VIH VIH VIH A0 VIL VIL VIL A1 VIH VIH VIH A2-A7 0 0 0 Other Addresses Don't Care Don't Care Don't Care A12-A20 Block Address Block Address Block Address DQ0 1 0 X DQ1 0 0 1 DQ2-DQ15 0000h 0000h 0000h Table 12. Read Configuration Register (AS and Read CFI instructions) RPF Function Reset Reset/Power Down EF VIL VIL GF VIL VIL WF VIH VIH A0 VIH VIH A1 VIH VIH A2-A7 0 0 Other Addresses Don't Care Don't Care DQ10 0 1 DQ0-DQ9 DQ11-DQ15 Don't Care Don't Care 10/46 M36DR432A, M36DR432B INSTRUCTIONS AND COMMANDS Seventeen instructions are defined (see Table 15), and the internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Data Polling, Toggle, Error bits can be read at any time, during programming or erase, to monitor the progress of the operation. Instructions, made up of one or more commands written in cycles, can be given to the Program/ Erase Controller through a Command Interface (C.I.). The C.I. latches commands written to the memory. Commands are made of address and data sequences. Two Coded Cycles unlock the Command Interface. They are followed by an input command or a confirmation command. The Coded Sequence consists of writing the data AAh at the address 555h during the first cycle and the data 55h at the address 2AAh during the second cycle. Instructions are composed of up to six cycles. The first two cycles input a Coded Sequence to the Command Interface which is common to all instructions (see Table 15). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature, Block Protection, Configuration Register Status or CFI Query for Read operations. In order to give additional data protection, the instructions for Block Erase and Bank Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For a Double Word Programming instruction, the fourth and fifth command cycles input the address and data to be programmed. For a Block Erase and Bank Erase instructions, the fourth and fifth cycles input a further Coded Sequence before the Erase confirm command on the sixth cycle. Any combination of blocks of the same memory bank can be erased. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. When power is first applied the command interface is reset to Read Array. Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosen to ensure maximum data security. Table 13. Commands Hex Code 00h 10h 20h 30h 40h Bypass Reset Bank Erase Confirm Unlock Bypass Block Erase Resume/Confirm Double Word Program Block Protect, or Block Unprotect, or Block Lock, or Write Configuration Register Set-up Erase Read Electronic Signature, or Block Protection Status, or Configuration Register Status CFI Query Program Erase Suspend Read Array/Reset Command 60h 80h 90h 98h A0h B0h F0h Read/Reset (RD) Instruction. The Read/Reset instruction consists of one write cycle giving the command F0h. It can be optionally preceded by the two Coded Cycles. Subsequent read operations will read the memory array addressed and output the data read. CFI Query (RCFI) Instruction. Common Flash Interface Query mode is entered writing 98h at address 55h. The CFI data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. Table 18, 19, 20 and 21 show the addresses used to retrieve each data. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 80h. This area can be accessed only in read mode by the final user and there are no ways of changing the code after it has been written by ST. Write a read instruction (RD) to return to Read mode. Auto Select (AS) Instruction. This instruction uses two Coded Cycles followed by one write cycle giving the command 90h to address 555h for command set-up. A subsequent read will output the Manufacturer or the Device Code (Electronic Signature), the Block Protection status or the Configuration Register status depending on the levels of A0 and A1 (see Table 10, 11 and 12). A7-A2 must be at VIL, while other address input are ignored. 11/46 M36DR432A, M36DR432B The bank address is don’t care for this instruction. The Electronic Signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of Flash Chip. The Manufacturer Code is output when the address lines A0 and A1 are at VIL, the Device Code is output when A0 is at VIH with A1 at VIL. The codes are output on DQ0-DQ7 with DQ8DQ15 at 00h. The AS instruction also allows the access to the Block Protection Status. After giving the AS instruction, A0 is set to VIL with A1 at VIH, while A12-A20 define the address of the block to be verified. A read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. The AS Instruction finally allows the access to the Configuration Register status if both A0 and A1 are set to VIH. If DQ10 is '0' only the Reset function is active as RPF is set to VIL (default at power-up). If DQ10 is '1' both the Reset and the Power Down functions will be achieved by pulling RPF to VIL. The other bits of the Configuration Register are reserved and must be ignored. A reset command puts the device in read array mode. Write Configuration Register (CR) Instruction. This instruction uses two Coded Cycles followed by one write cycle giving the command 60h to address 555h. A further write cycle giving the command 03h writes the contents of address bits A0-A15 to the 16 bits configuration register. Bits written by inputs A0-A9 and A11-A15 are reserved for future use. Address input A10 defines the status of the Reset/Power Down functions. It must be set to VIL to enable only the Reset function and to VIH to enable also the Power Down function. At Power Up all the Configuration Register bits are reset to '0'. Enter Bypass Mode (EBY) Instruction. This instruction uses the two Coded cycles followed by one write cycle giving the command 20h to address 555h for mode set-up. Once in Bypass mode, the device will accept the Exit Bypass (XBY) and Program or Double Word Program in Bypass mode (PGBY, DPGBY) commands. The Bypass mode allows to reduce the overall programming time when large memory arrays need to be programmed. Exit Bypass Mode (XBY) Instruction. This instruction uses two write cycles. The first inputs to the memory the command 90h and the second inputs the Exit Bypass mode confirm (00h). After the XBY instruction, the device resets to Read Memory Array mode. Program in Bypass Mode (PGBY) Instruction. This instruction uses two write cycles. The Program command A0h is written to any Address on the first cycle and the second write cycle latch12/46 es the Address on the falling edge of WF or EF and the Data to be written on the rising edge and starts the P/E.C. Read operations within the same bank output the Status Register bits after the programming has started. Memory programming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Program (PG) Instruction. This instruction uses four write cycles. The Program command A0h is written to address 555h on the third cycle after two Coded Cycles. A fourth write operation latches the Address and the Data to be written and starts the P/E.C. Read operations within the same bank output the Status Register bits after the programming has started. Memory programming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Programming at an address not in blocks being erased is also possible during erase suspend. Double Word Program (DPG) Instruction. This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. High voltage (11.4V to 12.6V) on VPP pin is required. This instruction uses five write cycles. The double word program command 40h is written to address 555h on the third cycle after two Coded Cycles. A fourth write cycle latches the address and data to be written to the first location. A fifth write cycle latches the new data to be written to the second location and starts the P/E.C.. Note that the two locations must have the same address except for the address bit A0. The Double Word Program can be executed in Bypass mode (DPGBY) to skip the two coded cycles at the beginning of each command. Block Protect (BP), Block Unprotect (BU), Block Lock (BL) Instructions. All blocks are protected at power-up. Each block of the array has two levels of protection against program or erase operation. The first level is set by the Block Protect instruction; a protected block cannot be programmed or erased until a Block Unprotect instruction is given for that block. A second level of protection is set by the Block Lock instruction, and requires the use of the WPF pin, according to the following scheme: – when WPF is at VIH, the Lock status is overridden and all blocks can be protected or unprotected; – when WPF is at VIL, Lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. Blocks that are not locked can still change their protection status, and program or erase accordingly; M36DR432A, M36DR432B – the lock status is cleared for all blocks at power up; once a block has been locked state can be cleared only with a reset command. The protection and lock status can be monitored for each block using the Autoselect (AS) instruction. Protected blocks will output a ‘1’ on DQ0 and locked blocks will output a ‘1’ on DQ1. Refer to Table 14 for a list of the protection states. Block Erase (BE) Instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 555h on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded cycles and an address within the block to be erased is given and latched into the memory. Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Coded cycles. All blocks must belong to the same bank of memory; if a new block belonging to the other bank is given, the operation is aborted. The erase will start after an erase timeout period of 100µs. Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is '0' the Block Erase Command has been given and the timeout is running, if DQ3 is '1', the timeout has expired and the P/E.C. is erasing the Block(s). If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before erasing to FFh. Read operations within the same bank, after the sixth rising edge of WF or EF, output the status register bits. During the execution of the erase by the P/E.C., the memory accepts only the Erase Suspend ES instruction; the Read/Reset RD instruction is accepted during the 100µs time-out period. Data Polling bit DQ7 returns '0' while the erasure is in progress and '1' when it has completed. The Toggle bit DQ6 toggles during the erase operation, and stops when erase is completed. After completion the Status Register bit DQ5 returns '1' if there has been an erase failure. In such a situation, the Toggle bit DQ2 can be used to determine which block is not correctly erased. In the case of erase failure, a Read/Reset RD instruction is necessary in order to reset the P/E.C. Bank Erase (BKE) Instruction. This instruction uses six write cycles and is used to erase all the blocks belonging to the selected bank. The Erase Set-up command 80h is written to address 555h on the third cycle after the two Coded cycles. The Bank Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles at an address within the selected bank. If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations within the same bank after the sixth rising edge of WF or EF output the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit DQ7 returns '0', then '1' on completion. The Toggle bit DQ6 toggles during erase operation and stops when erase is completed. After completion the Status Register bit DQ5 returns '1' if there has been an Erase Failure. Erase Suspend (ES) Instruction. In a dual bank memory the Erase Suspend instruction is used to read data within the bank where erase is in progress. It is also possible to program data in blocks not being erased. The Erase Suspend instruction consists of writing the command B0h without any specific address. No Coded Cycles are required. Erase suspend is accepted only during the Block Erase instruction execution. The Toggle bit DQ6 stops toggling when the P/E.C. is suspended within 15µs after the Erase Suspend (ES) command has been written. The device will then automatically be set to Read Memory Array mode. When erase is suspended, a Read from blocks being erased will output DQ2 toggling and DQ6 at '1'. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume ER and the Program PG instructions. A Program operation can be initiated during erase suspend in one of the blocks not being erased. It will result in DQ6 toggling when the data is being programmed. Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at an address within the bank being erased and without any Coded Cycle. 13/46 M36DR432A, M36DR432B Table 14. Protection States (1) Current State (2) (WP, DQ1, DQ0) 100 101 110 111 000 001 011 Program/Erase Allowed yes no yes no yes no no Next State After Event (3) Protect 101 101 111 111 001 001 011 Unprotect 100 100 110 110 000 000 011 Lock 111 111 111 111 011 011 011 WP transition 000 001 011 011 100 101 111 or 110 (4) Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WPF status. 2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Autoselect instruction with A1 = VIH and A0 = VIL. 3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WPF has changed its logic value. 4. A WPF transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110. Table 15. Instructions (1,2) Mne. Instr. Cyc. 1+ RD (4) Read/Reset Memory Array 3+ Data Addr. RCFI CFI Query 1+ Data Addr. AS (4) Auto Select 3+ Data Addr. 4 Data Addr. PG Program 4 Data Addr. DPG Double Word Program 5 Data Enter Bypass Mode Addr. 3 Data AAh 55h 20h AAh 555h 55h 2AAh 40h 555h Program Data 1 Program Data 2 AAh 555h 55h 2AAh A0h 555h AAh 555h 55h 2AAh 60h 555h AAh 555h 55h 2AAh 90h 555h 98h 555h 2AAh 555h Read electronic Signature or Block Protection or Configuration Register Status until a new cycle is initiated. Configuration Data 03h Program Address Read Data Polling or Toggle Bit until Program Program completes. Data Program Program Address 1 Address 2 Note 6, 7 AAh 55h Read CFI data until a new write cycle is initiated. 55h F0h Addr. (3) Data Addr. 1st Cyc. X Read Memory Array until a new write cycle is initiated. F0h 555h 2AAh 555h Read Memory Array until a new write cycle is initiated. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. CR Configuration Register Write EBY 14/46 M36DR432A, M36DR432B Mne. XBY Instr. Exit Bypass Mode Cyc. Addr. 2 Data Addr. PGBY Program in Bypass Mode 2 Data Addr. 3 Data Addr. BP Block Protect 4 Data Addr. BU Block Unprotect 1 Data Addr. BL Block Lock 4 Data Addr. BE Block Erase 6+ Data Addr. BKE Bank Erase 6 Data ES Erase Suspend 1 Addr. (3) Data Addr. ER Note: 1. 2. 3. 4. 1st Cyc. X 90h X A0h X 40h 555h AAh 555h AAh 555h AAh 555h AAh 555h AAh X B0h Bank Address 30h 2nd Cyc. X 00h 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. Program Address Read Data Polling or Toggle Bit until Program Program completes. Data Program Program Address 1 Address 2 Note 6, 7 Program Data 1 2AAh 55h 2AAh 55h 2AAh 55h 2AAh 55h 2AAh 55h Program Data 2 555h 60h 555h 60h 555h 60h 555h 80h 555h 80h Block Address 01h Block Address D0h Block Address 2Fh 555h AAh 555h AAh 2AAh 55h 2AAh 55h Block Address 30h Bank Address 10h Double Word DPGBY Program in Bypass Mode Read until Toggle stops, then read all the data needed from any Blocks not being erased then Resume Erase. Erase Resume 1 Data Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time Commands not interpreted in this table will default to read array mode. For Coded cycles address inputs A11-A20 are don't care. X = Don't Care. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles. 5. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. 6. Program Address 1 and Program Address 2 must be consecutive addresses differing only for address bit A0. 7. High voltage on VPPF (11.4V to 12.6V) is required for the proper execution of the Double Word Program instruction. 15/46 M36DR432A, M36DR432B STATUS REGISTER BITS P/E.C. status is indicated during execution by Data Polling on DQ7, detection of Toggle on DQ6 and DQ2, or Error on DQ5 bits. Any read attempt within the Bank being modified and during Program or Erase command execution will automatically output these five Status Register bits. The P/E.C. automatically sets bits DQ2, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1 and DQ4) are reserved for future use and should be masked (see Tables 17 and 16). Read attempts within the bank not being modified will output array data. Data Polling Bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7. In case of a double word program operation, the complement is done on DQ7 of the last word written to the command interface, i.e. the data written in the fifth cycle. During Erase operation, it outputs a '0'. After completion of the operation, DQ7 will output the bit last programmed or a '1' after erasing. Data Polling is valid and only effective during P/E.C. operation, that is after the fourth WF pulse for programming or after the sixth WF pulse for erase. It must be performed at the address being programmed or at an address within the block being erased. See Figure 25 for the Data Polling flowchart and Figure 12 for the Data Polling waveforms. DQ7 will also flag the Erase Suspend mode by switching from '0' to '1' at the start of the Erase Suspend. In order to monitor DQ7 in the Erase Suspend mode an address within a block being erased must be provided. For a Read Operation in Suspend mode, DQ7 will output '1' if the read is attempted on a block being erased and the data value on other blocks. During Program operation in Erase Suspend Mode, DQ7 will have the same behavior as in the normal program execution outside of the suspend mode. Toggle Bit (DQ6). When Programming or Erasing operations are in progress, successive attempts to read DQ6 will output complementary data. DQ6 will toggle following toggling of either GF, or EF when GF is at VIL. The operation is completed when two successive reads yield the same output data. The next read will output the bit last programmed or a '1' after erasing. The toggle bit DQ6 is valid only during P/E.C. operations, that is after the fourth WF pulse for programming or after the sixth WF pulse for Erase. DQ6 will be set to '1' if a Read operation is attempted on an Erase Sus- pend block. When erase is suspended DQ6 will toggle during programming operations in a block different from the block in Erase Suspend. Either EF or GF toggling will cause DQ6 to toggle. See Figure 25 for Toggle Bit flowchart and Figure 13 for Toggle Bit waveforms. Toggle Bit (DQ2). This toggle bit, together with DQ6, can be used to determine the device status during the Erase operations. During Erase Suspend a read from a block being erased will cause DQ2 to toggle. A read from a block not being erased will output data. DQ2 will be set to '1' during program operation and to ‘0’ in Erase operation. After erase completion and if the error bit DQ5 is set to '1', DQ2 will toggle if the faulty block is addressed. Error Bit (DQ5). This bit is set to '1' by the P/E.C. when there is a failure of programming or block erase, that results in invalid data in the memory block. In case of an error in block erase or program, the block in which the error occurred or to which the programmed data belongs, must be discarded. Other Blocks may still be used. The error bit resets after a Read/Reset (RD) instruction. In case of success of Program or Erase, the error bit will be set to '0'. Erase Timer Bit (DQ3). This bit is set to ‘0’ by the P/E.C. when the last block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the erase timeout period is finished, DQ3 returns to ‘1’, in the range of 80µs to 120µs. Table 16. Polling and Toggle Bits Mode Program Erase Erase Suspend Read (in Erase Suspend block) Erase Suspend Read (outside Erase Suspend block) Erase Suspend Program DQ7 DQ7 0 DQ6 Toggle Toggle DQ2 1 N/A 1 1 Toggle DQ7 DQ6 DQ2 DQ7 Toggle 1 16/46 M36DR432A, M36DR432B Table 17. Status Register Bits (1) DQ Name Logic Level '1' '0' 7 Data Polling DQ DQ '-1-0-1-0-1-0-1-' DQ 6 Toggle Bit '-1-1-1-1-1-1-1-' Definition Erase Complete or erase block in Erase Suspend. Erase On-going Program Complete or data of non erase block during Erase Suspend. Program On-going (2) Erase or Program On-going Program Complete Erase Complete or Erase Suspend on currently addressed block Program or Erase Error Program or Erase On-going Successive reads output complementary data on DQ6 while Programming or Erase operations are on-going. DQ6 remains at constant level when P/E.C. operations are completed or Erase Suspend is acknowledged. This bit is set to '1' in the case of Programming or Erase failure. Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. Note '1' 5 4 Error Bit '0' Reserved '1' 3 Erase Time Bit '0' Erase Timeout Period Expired P/E.C. Erase operation has started. Only possible command entry is Erase Suspend (ES) An additional block to be erased in parallel can be entered to the P/E.C: Erase Timeout Period On-going Erase Suspend read in the Erase Suspended Block. Erase Error due to the currently addressed block (when DQ5 = '1'). Program on-going or Erase Complete. Erase Suspend read on non Erase Suspend block. '-1-0-1-0-1-0-1-' 2 Toggle Bit 1 DQ 1 0 Reserved Reserved Indicates the erase status and allows to identify the erased block. Note: 1. Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. 2. In case of double word program DQ7 refers to the last word input. 17/46 M36DR432A, M36DR432B POWER CONSUMPTION Power Down The memory provides Reset/Power Down control input RPF. The Power Down function can be activated only if the relevant Configuration Register bit is set to '1'. In this case, when the RPF signal is pulled at VSS the supply current drops to typically ICC2 (see Table 24), the memory is deselected and the outputs are in high impedance.If RPF is pulled to VSS during a Program or Erase operation, this operation is aborted in tPLQ7V and the memory content is no longer valid (see Reset/Power Down input description). Power Up The memory Command Interface is reset on Power Up to Read Array. Either EF or WF must be tied to VIH during Power Up to allow maximum security and the possibility to write a command on the first rising edge of WF. Supply Rails Normal precautions must be taken for supply voltage decoupling; each device in a system should have the VCCF rails decoupled with a 0.1µF capacitor close to the VCCF and VSS pins. The PCB trace widths should be sufficient to carry the required VCCF program and erase currents. 18/46 M36DR432A, M36DR432B COMMON FLASH INTERFACE (CFI) The Common Flash Interface (CFI) specification is a JEDEC approved, standardised data structure that can be read from the Flash memory device. CFI allows a system software to query the flash device to determine various electrical and timing parameters, density information and functions supported by the device. CFI allows the system to easily interface to the Flash memory, to learn about its features and parameters, enabling the software to configure itself when necessary. Tables 18, 19, 20, and 21 show the address used to retrieve each data. Table 18. Query Structure Overview Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) The CFI data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. Tables 18, 19, 20, and 21 show the addresses used to retrieve each data. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 81h. This area can be accessed only in read mode and there are no ways of changing the code after it has been written by ST. Write a read instruction to return to Read mode. Refer to the CFI Query instruction to understand how the M36DR432 enters the CFI Query mode. Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 19, 20 and 21. Query data are always presented on the lowest order data outputs. Table 19. CFI Query Identification String Offset 00h 01h 02h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0020h 00A0h - top 00A1h - bottom reserved 0051h 0052h 0059h 0002h 0000h offset = P = 0040h Address for Primary Algorithm extended Query table 0000h 0000h 0000h value = A = 0000h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (note: 0000h means none exists) Address for Alternate Algorithm extended Query table note: 0000h means none exists Manufacturer Code Device Code Reserved Query Unique ASCII String "QRY" Query Unique ASCII String "QRY" Query Unique ASCII String "QRY" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Description Note: 1. Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. 19/46 M36DR432A, M36DR432B Table 20. CFI Query System Interface Information Offset 1Bh Data 0017h Description VCCF Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VCCF Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPPF [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Note: This value must be 0000h if no VPP pin is present VPPF [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Note: This value must be 0000h if no VPP pin is present Typical timeout per single byte/word program (multi-byte program count = 1), 2n µs (if supported; 0000h = not supported) Typical timeout for maximum-size multi-byte program or page write, 2n µs (if supported; 0000h = not supported) Typical timeout per individual block erase, 2n ms (if supported; 0000h = not supported) Typical timeout for full chip erase, 2n ms (if supported; 0000h = not supported) Maximum timeout for byte/word program, 2n times typical (offset 1Fh) (0000h = not supported) Maximum timeout for multi-byte program or page write, 2n times typical (offset 20h) (0000h = not supported) Maximum timeout per individual block erase, 2n times typical (offset 21h) (0000h = not supported) Maximum timeout for chip erase, 2n times typical (offset 22h) (0000h = not supported) 1Ch 0022h 1Dh 0000h 1Eh 00C0h 1Fh 20h 21h 22h 23h 24h 25h 26h 0004h 0000h 000Ah 0000h 0004h 0000h 0004h 0000h 20/46 M36DR432A, M36DR432B Table 21. Device Geometry Definition Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch Data 0016h 0001h Flash Device Interface Code description: Asynchronous x16 0000h 0000h 0000h 0002h Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions within device bit 7 to 0 = x = number of Erase Block Regions Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk." 2. x specifies the number of regions within the device containing one or more contiguous Erase Blocks of the same size. For example, a 128KB device (1Mb) having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is considered to have 5 Erase Block Regions. Even though two regions both contain 16KB blocks, the fact that they are not contiguous means they are separate Erase Block Regions. 3. By definition, symmetrically block devices have only one blocking region. M36DR432A 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h M36DR432B 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h M36DR432A Erase Block Region Information 003Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h M36DR432B 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase Block Region: e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = "1 block") Note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0 bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in size. The value z = 0 is used for 128 byte block size. e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K Device Size = 2n in number of bytes Description 21/46 M36DR432A, M36DR432B SRAM COMPONENT Device Operations The following operations can be performed using the appropriate bus cycles: Read Array, Write Array, Output Disable, Power Down (see Table 3). Read. Read operations are used to output the contents of the SRAM Array. The SRAM is in Read mode whenever Write Enable (WS) is at VIH with Output Enable (GS) at VIL, and both Chip Enables (E1S and E2S) and UBS, LBS combinations are asserted. Valid data will be available at the output pins within tAVQV after the last stable address, providing GS is Low, E1S is Low and E2S is High. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tE1LQV, tE2HQV, or tGLQV) rather than the address. Data out may be indeterminate at tE1LQX, tE2HQX and tGLQX, but data lines will always be valid at tAVQV (see Table 31, Figures 16 and 17). Write. Write operations are used to write data in the SRAM. The SRAM is in Write mode whenever the WS and E1S pins are at VIL, with E2S at VIH. Either the Chip Enable inputs (E1S and E2S) or the Write Enable input (WS) must be de-asserted during address transitions for subsequent write cycles. Write begins with the concurrence of both Chip Enables being active with WS at VIL. A Write begins at the latest transition among E1S going to VIL, E2S going to VIH and WS going to VIL. Therefore, address setup time is referenced to Write Enable and both Chip Enables as tAVWL, tAVE1L and tAVE2H respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the rising edge of E1S, the rising edge of WS or the falling edge of E2S, whichever occurs first. If the Output is enabled (E1S=VIL, E2S=VIH and GS=VIL), then WS will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVE1H before the rising edge of E1S or for tDVE2L before the falling edge of E2S, whichever occurs first, and remain valid for tWHDX, tE1HAX or tE2LAX (see Table 32, Figure 19, 21, 23). Standby/Power-Down. The SRAM chip has a Chip Enable power-down feature which invokes an automatic standby mode (see Table 31, Figure 18) whenever either Chip Enable is de-asserted (E1S=VIH or E2S=VIL). Data Retention The SRAM data retention performances as VCCS go down to VDR are described in Table 33 and Figure 23, 24. In E1S controlled data retention mode, minimum standby current mode is entered when E1S ≥ VCCS – 0.2V and E2S ≤ 0.2V or E2S ≥ VCCS – 0.2V. In E2S controlled data retention mode, minimum standby current mode is entered when E2S ≤ 0.2V. Output Disable. The data outputs are high impedance when the Output Enable (GS) is at VIH with Write Enable (WS) at VIH. 22/46 M36DR432A, M36DR432B Table 22. AC Measurement Conditions Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages ≤ 4ns VDD Figure 6. AC Measurement Load Circuit VDD 0 to VDD VDD/2 25kΩ Figure 5. AC Measurement Waveform DEVICE UNDER TEST 25kΩ VDD VDD/2 0V AI90206 0.1µF CL = 50pF CL includes JIG capacitance Note: VDD means VDDF = VDDS AI90207 Table 23. Device Capacitance (1) (TA = 25 °C, f = 1 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 10 12 Unit pF pF Note: 1. Sampled only, not 100% tested. 23/46 M36DR432A, M36DR432B Table 24. DC Characteristics (TA = –40 to 85°C; VDDF = VDDS = 1.65V to 2.2V) Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Device Flash & SRAM Flash & SRAM Flash IDDS VDD Standby Current Test Condition 0V ≤ VIN ≤ VDD 0V ≤ VOUT ≤ VDD EF = VDDF ± 0.2V VDDF = VDD max E1S ≥ VDDS – 0.2V, E2S ≤ VDDS – 0.2V, VIN ≥ VDDS – 0.2V or VIN ≤ VDDS – 0.2V, f=0 RPF = VSSF ± 0.2V IIO = 0 mA, E1S = VIL, E2S = WS = VIH, VIN = VIL or VIH, VDDS = VDD max, cycle time = 1µs IIO = 0 mA, E1S = VIL, E2S = WS = VIH, VIN = VIL or VIH, VDDS = VDD max, min cycle time EF = VIL, GF = VIH, f = 5 MHz Program in progress Program/Erase in progress in one bank Read in the other bank Erase in progress Erase Suspend in progress Program Suspend in progress VPPF ≤ VDDS VPPF = 12V ± 0.6V VPPF ≤ VDDS VPPF = 12V ± 0.6V VPPF = 12V ± 0.6V Program in progress VPPF = 12V ± 0.6V Program in progress –0.5 1.4 VDDF = VDDS = VDD min IOL = 100µA VDDF = VDDS = VDD min IOH = –100µA VDD –0.1 0.2 100 0.2 100 5 5 10 10 20 10 15 Min Typ Max ±2 ±10 50 Unit µA µA µA SRAM 20 50 µA IDDD Supply Current (Reset) Flash 2 10 µA 10 mA IDD Supply Current SRAM 25 mA IDDR IDDW IDDWD IDDE Supply Current (Read) Supply Current (Program) Supply Current (Dual Bank) Supply Current (Erase) Flash Flash Flash Flash Flash 20 20 40 20 50 mA mA mA mA µA Supply Current IDDES(1) (Erase Suspend) Supply Current IDDWS(1) (Program Suspend) IPPS IPPR IPPW IPPE VIL VIH VOL VOH Program Current (Standby) Program Current (Read) Program Current (Program) Program Current (Erase) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Flash 50 5 400 5 400 10 10 0.4 VDD +0.3 0.2 µA µA µA µA µA mA mA V V V V Flash Flash Flash Flash Flash & SRAM Flash & SRAM Flash & SRAM Flash & SRAM 24/46 M36DR432A, M36DR432B Symbol VPPL Parameter Program Voltage (Program or Erase operations) Program Voltage (Program or Erase operations) Program Voltage (Program and Erase lock-out) VDDF Supply Voltage (Program and Erase lockout) Device Flash Test Condition Min 1.65 Typ Max 3.6 Unit V VPPH Flash 11.4 12.6 V VPPLK Flash 1 V VLKO Flash 2 V Note: 1. IDDES and IDDWS are specified with device deselected. If device is read while in erase suspend, current draw is sum of IDDES and I DDR. If the device is read while in program suspend, current draw is the sum of IDDWS and IDDR. Table 25. Flash Read AC Characteristics (TA = –40 to 85°C; VDDF = 1.65V to 2.2V) Flash Symbol Alt Parameter Test Condition Min tAVAV tAVQV tAVQV1 tAXQX tEHQX tEHQZ (1) tELQV (2) tELQX (1) tGHQX tGHQZ (1) tGLQV (2) tGLQX (1) tRC tACC tPAGE tOH tOH tHZ tCE tLZ tOH tDF tOE tOLZ Address Valid to Next Address Valid Address Valid to Output Valid (Random) Address Valid to Output Valid (Page) Address Transition to Output Transition Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition EF = VIL, GF = VIL EF = VIL, GF = VIL EF = VIL, GF = VIL EF = VIL, GF = VIL GF = VIL GF = VIL GF = VIL GF = VIL EF = VIL EF = VIL EF = VIL EF = VIL 0 0 0 25 25 0 0 0 25 100 0 0 35 35 100 100 35 0 0 35 120 100 Max Min 120 120 45 120 Max ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. Sampled only, not 100% tested. 2. GF may be delayed by up to tELQV - tGLQV after the falling edge of EF without increasing tELQV 25/46 26/46 tAVAV VALID tAVQV tELQV tAXQX tEHQZ tELQX tEHQX tGLQV tGLQX VALID tGHQX tGHQZ AI90208 M36DR432A, M36DR432B Figure 7. Flash Read AC Waveforms A0-A20 EF GF DQ0-DQ15 Note: Write Enable (WF) = High. A2-A20 VALID A0-A1 tELQV Figure 8. Flash Page Read AC Waveforms VALID VALID VALID VALID EF tGLQV GF tAVQV tGHQX tEHQZ tAVQV1 VALID VALID VALID tEHQX VALID tGHQZ DQ0-DQ15 M36DR432A, M36DR432B AI90209 27/46 M36DR432A, M36DR432B Table 26. Flash Write AC Characteristics, Write Enable Controlled (TA = –40 to 85 °C; VDDF = 1.65V to 2.2V Flash Symbol Alt Parameter Min tAVAV tAVWL tDVWH tELWL tGHWL tPLQ7V tVDHEL tWHDX tWHEH tWHGL tWHWL tWLAX tWLWH tVCS tDH tCH tOEH tWPH tAH tWP tWC tAS tDS tCS Address Valid to Next Address Valid Address Valid to Write Enable Low Input Valid to Write Enable High Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low RPF Low to Reset Complete During Program/Erase VCCF High to Chip Enable Low Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Output Enable Low Write Enable High to Write Enable Low Write Enable Low to Address Transition Write Enable Low to Write Enable High 50 0 0 30 30 50 50 100 0 50 0 0 15 50 0 0 30 30 50 50 100 Max Min 120 0 50 0 0 15 120 Max ns ns ns ns ns µs µs ns ns ns ns ns ns Unit Figure 9. Flash Write AC Waveforms, WF Controlled tAVAV A0-A20 VALID tWLAX tAVWL EF tELWL GF tGHWL WF tWHWL tDVWH DQ0-DQ15 VALID tWHDX tWLWH tWHGL tWHEH VDDF tVDHEL AI90210 Note: 1. Address are latched on the falling edge of WF, Data is latched on the rising edge of WF . 28/46 M36DR432A, M36DR432B Table 27. Flash Write AC Characteristics, Chip Enable Controlled (TA = –40 to 85 °C; VDDF = 1.65V to 2.2V) Flash Symbol Alt Parameter Min tAVAV tAVEL tDVEH tEHDX tEHEL tEHGL tEHWH tELAX tELEH tGHEL tPLQ7V tVDHWL tWLEL tVCS tWS tWC tAS tDS tDH tCPH tOEH tWH tAH tCP Address Valid to Next Address Valid Address Valid to Chip Enable Low Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Chip Enable Low to Address Transition Chip Enable Low to Chip Enable High Output Enable High Chip Enable Low RPF Low to Reset Complete During Program/Erase VCCF High to Write Enable Low Write Enable Low to Chip Enable Low 50 0 100 0 50 0 30 30 0 50 50 0 15 50 0 100 Max Min 120 0 50 0 30 30 0 50 50 0 15 120 Max ns ns ns ns ns ns ns ns ns ns µs µs ns Unit Figure 10. Flash Write AC Waveforms, EF Controlled tAVAV A0-A20 VALID tELAX tAVEL WF tWLEL GF tGHEL EF tEHEL tDVEH DQ0-DQ15 VALID tEHDX tELEH tEHGL tEHWH VDDF tVDHWL AI90211 Note: Address are latched on the falling edge of EF, Data is latched on the rising edge of EF . 29/46 M36DR432A, M36DR432B Table 28. Flash Read and Write AC Characteristics, RPF Related (TA = –40 to 85°C; VDDF = 1.65V to 2.2V) Flash Symbol Alt Parameter Test Condition Min tPHQ7V1 tPHQ7V2 tPLPH tPLQ7V tRP RPF High to Data Valid (Read Mode) RPF High to Data Valid (Power Down enabled) RPF Pulse Width RPF Low to Reset Complete During Program/Erase 100 15 100 Max 150 50 100 15 Min 120 Max 150 50 ns µs ns µs Unit Figure 11. Flash Read and Write AC Waveforms, RPF Related READ PROGRAM / ERASE WF DQ7 VALID DQ7 VALID RPF tPLPH tPHQ7V1,2 tPLQ7V AI90212 30/46 M36DR432A, M36DR432B Table 29. Flash Program, Erase Times and Program, Erase Endurance Cycles (TA = –40 to 85°C; VDDF = 1.65V to 2.2V, VPPF = VDDF unless otherwise specified) Parameter Parameter Block (4 KWord) Erase (Preprogrammed) Main Block (32 KWord) Erase (Preprogrammed) Bank Erase (Preprogrammed, Bank A) Bank Erase (Preprogrammed, Bank B) Chip Program (2) Chip Program (DPG, VPP = 12V) (2) Word Program Program/Erase Cycles (per Block) 100,000 200 Min Max (1) 2.5 10 Typ 0.15 1 2 10 20 10 10 10 Typical after 100k W/E Cycles 0.4 3 6 30 25 Unit s s s s s s µs cycles Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or erase should perform significantly better. 2. Excludes the time needed to execute the sequence for program instruction. Table 30. Flash Data Polling and Toggle Bits AC Characteristics (1) (TA = –40 to 85 °C; VDDF = 1.65V to 2.2V) Flash Symbol Parameter Min tEHQ7V Chip Enable High to DQ7 Valid (Program, EF Controlled) Chip Enable High to DQ7 Valid (Block Erase, EF Controlled) Chip Enable High to Output Valid (Program) tEHQV Chip Enable High to Output Valid (Block Erase) tQ7VQV Q7 Valid to Output Valid (Data Polling) Write Enable High to DQ7 Valid (Program, WF Controlled) tWHQ7V Write Enable High to DQ7 Valid (Block Erase, WF Controlled) Write Enable High to Output Valid (Program) Write Enable High to Output Valid (Block Erase) 10 1 10 1 1 10 0 200 10 200 10 s ns µs s µs s 10 1 10 Max 200 10 200 µs s µs Unit tWHQV Note: 1. All other timings are defined in Read AC Characteristics table. 31/46 32/46 ADDRESS (WITHIN BLOCKS) tAVQV tELQV tEHQ7V tGLQV tWHQ7V DQ7 VALID IGNORE tQ7VQV VALID DATA POLLING READ CYCLES DATA POLLING (LAST) CYCLE MEMORY ARRAY READ CYCLE AI90213 M36DR432A, M36DR432B A0-A20 EF GF Figure 12. Flash Data Polling DQ7 AC Waveforms WF DQ7 DQ0-DQ6/ DQ8-DQ15 LAST WRITE CYCLE OF PROGRAM OR ERASE INSTRUCTION A0-A20 VALID tEHQV tAVQV EF tELQV GF tGLQV WF tWHQV STOP TOGGLE VALID Figure 13. Flash Data Toggle DQ6, DQ2 AC Waveforms DQ6,DQ2 DQ0-DQ1,DQ3-DQ5, DQ7-DQ15 IGNORE VALID LAST WRITE CYCLE OF PROGRAM OF ERASE INSTRUCTION DATA TOGGLE READ CYCLE DATA TOGGLE READ CYCLE MEMORY ARRAY READ CYCLE AI90214 M36DR432A, M36DR432B Note: All other timings are as a normal Read cycle. 33/46 M36DR432A, M36DR432B Figure 14. Flash Data Polling Flowchart Figure 15. Flash Data Toggle Flowchart START START READ DQ5 & DQ7 at VALID ADDRESS READ DQ5 & DQ6 DQ7 = DATA NO NO YES DQ6 = TOGGLES YES NO NO DQ5 =1 YES READ DQ7 DQ5 =1 YES READ DQ6 DQ7 = DATA NO FAIL YES DQ6 = TOGGLES YES PASS FAIL NO PASS AI90215 AI90216 34/46 M36DR432A, M36DR432B Table 31. SRAM Read AC Characteristics (TA = –40 to 85°C; VDDS = 1.65V to 2.2V) SRAM Symbol tAVAV tAVQV tAXQX tBHQZ tBLQV tBLQX tE1HQZ tE1LQV tE1LQX tE2HQV tE2HQX tE2LQZ tGHQZ tGLQV tGLQX tPD (1) tPU (1) Alt tRC tAA tOH tBHZ tBA tBLZ tHZ1 tCO1 tLZ1 tCO2 tLZ2 tHZ2 tOHZ tOE tOLZ Read Cycle Time Address Valid to Output Valid Address Transition to Output Transition UBS, LBS Disable to Hi-Z Output UBS, LBS Access Time UBS, LBS Enable to Low-Z Output Chip Enable 1 High to Output Hi-Z Chip Enable 1 Low to Output Valid Chip Enable 1 Low to Output Transition Chip Enable 2 High to Output Valid Chip Enable 2 High to Output Transition Chip Enable 2 Low to Output Hi-Z Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable 1 High or Chip Enable 2 Low to Power Down Chip Enable 1 Low or Chip Enable 2 High to Power Up 0 5 100 10 0 0 25 30 35 10 100 5 0 30 100 15 25 100 Parameter Min 100 100 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. Sampled only. Not 100% tested. Figure 16. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = VIL tAVAV A0-A17 tAVQV tAXQX VALID DQ0-DQ15 DATA VALID DATA VALID AI90217 Note: E1S = Low, E2S = High, GS = Low, WS = High. 35/46 M36DR432A, M36DR432B Figure 17. SRAM Read AC Waveforms, E1S, E2S or GS Controlled tAVAV A0-A17 tAVQV tE1LQV E1S tE1LQX tE2HQV E2S tE2HQX tBLQV UBS, LBS tBLQX tGLQV GS tGLQX DQ0-DQ15 DATA VALID AI90218 VALID tAXQX tE1HQZ tE2LQZ tBHQZ tGHQZ Note: Write Enable (WS) = High. Figure 18. SRAM Standby AC Waveforms E1S E2S IDD tPU 50% tPD AI90219 36/46 M36DR432A, M36DR432B Table 32. SRAM Write AC Characteristics (TA = –40 to 85°C; VDDS = 1.65V to 2.2V) SRAM Symbol tAVAV tAVE1L tAVE2H tAVWH tAVWL tBLWH tDVE1H tDVE2L tDVWH tE1HAX tE1LWH, tE2HWH tE2LAX tGHQZ tWHAX tWHDX tWHQX tWLQZ tWLWH Note: 1. 2. 3. 4. Alt tWC tAS (1) tAS (1) tAW tAS (1) tBW tDW tDW tDW tWR (2) tCW (3) tWR (2) tGHZ tWR (2) tDH tOW tWHZ tWP (4) Write Cycle Time Parameter Min 100 0 0 80 0 80 40 40 40 0 80 0 25 0 0 5 35 70 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Address Valid to Chip Enable 1 Low Address Valid to Chip Enable 2 High Address Valid to Write Enable High Address Valid to Write Enable Low UBS, LBS Valid to End of Write Input Valid to Chip Enable 1 High Input Valid to Chip Enable 2 Low Input Valid to Write Enable High Chip Enable 1 High to Address Transition Chip Select to End of Write Chip Enable 2 Low to Address Transition Output Enable Higt to Output Hi-Z Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to Output Hi-Z Write Enable Pulse Width tAS is measured from the address valid to the beginning of write. tWR is measured from the end or write to the address change. tWR applied in case a write ends as E1S or WS going high. tCW is measured from E1S going low end of write. A Write occurs during the overlap (tWP) of low E1S and low WS. A write begins when E1S goes low and WS goes low with asserting UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the earliest transition when E1S goes high and WS goes high. The tWP is measured from the beginning of write to the end of write. 37/46 M36DR432A, M36DR432B Figure 19. SRAM Write AC Waveforms, WS Controlled with GS Low tAVAV A0-A17 VALID tAVWH tAVE1L E1S tAVE2H E2S tE2HWH tBLWH UBS, LBS tAVWL WS tWLQZ tDVWH DQ0-DQ15 INPUT VALID AI90220 tE1LWH tWHAX tWLWH tWHQX tWHDX Note: Output Enable (GS) = Low. Figure 20. SRAM Write AC Waveforms, WS Controlled with GS High tAVAV A0-A17 VALID tAVWH tAVE1L E1S tAVE2H E2S tE2HWH tBLWH UBS, LBS tAVWL WS tWLWH tE1LWH tWHAX GS tWHQX tGHQZ DQ0-DQ15 tDVWH INPUT VALID AI90221 tWHDX 38/46 M36DR432A, M36DR432B Figure 21. SRAM Write Cycle Waveform, UBS and LBS Controlled tAVAV A0-A17 VALID tE1LWH E1S tAVWH E2S tE2HWH tAVWL UBS, LBS tWLWH WS tDVWH DQ0-DQ15 DATA VALID tWHDX tBLWH tE1HAX AI90222 Figure 22. SRAM Write AC Waveforms, E1S Controlled tAVAV A0-A17 tAVE1L E1S VALID tE1LWH tE1HAX E2S tBLWH UBS, LBS tAVWL WS tDVE1H DQ0-DQ15 INPUT VALID tWHDX AI90223 Note: Output Enable (GS) = High. 39/46 M36DR432A, M36DR432B Table 33. SRAM Low VCCS Data Retention Characteristics (1, 2) (TA = –40 to 85°C; VDDS = 1.65V to 2.2V) Symbol IDDDR VDR tCDR tR Parameter Supply Current (Data Retention) Supply Voltage (Data Retention) Chip Disable to Power Down Operation Recovery Time Test Condition VDDS = 1.2V, E1S ≥ VDDS – 0.2V, E2S ≥ VDDS – 0.2V or E2S ≤ 0.2V, f = 0 E1S ≥ VDDS – 0.2V, E2S ≤ 0.2V, f = 0 E1S ≥ VCCS – 0.2V, E2S ≤ 0.2V, f = 0 1 0 tRC Min Max 10 2.2 Unit µA V ns ns Note: 1. All other Inputs VIH ≤ VDD– 0.2V or VIL ≤ 0.2V. 2. Sampled only. Not 100% tested. Figure 23. SRAM Low VDDS Data Retention AC Waveforms, E1S Controlled tCDR VDDS 1.65 V 1.2 V VDR DATA RETENTION MODE tR E1S ≥ VDDS – 0.2V E1S V SSS AI90224 Figure 24. SRAM Low VDDS Data Retention AC Waveforms, E2S Controlled DATA RETENTION MODE VDDS 1.65 V E2S tCDR VDR 0.4 V VSSS AI90225 tR E2S ≤ 0.2V 40/46 M36DR432A, M36DR432B Table 34. Ordering Information Scheme Example: Device Type M36 = MMP (Flash + SRAM) Architecture D = Dual Bank, Page Mode Operating Voltage R = VDDF = VDDS =1.65V to 2.2V SRAM Chip Size & Organization 4 = 4 Mbit (256K x 16 bit) Device Function 32A = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Top Boot 32B = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Bottom Boot Speed 100 = 100ns 120 = 120ns Package ZA = LFBGA66: 0.8mm pitch Temperature Range 6 = –40 to 85°C Option T = Tape & Reel packing C = Cypress’s SRAM M36DR432A 100 ZA 6 T Devices are shipped from the factory with the memory content bits erased to ’1’. Table 35. Daisy Chain Ordering Scheme Example: Device Type M36DR432 Daisy Chain -ZA = LFBGA66: 0.8mm pitch Option T = Tape & Reel Packing M36DR432 -ZA T For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 41/46 M36DR432A, M36DR432B Table 36. Revision History Date 24-May-2001 19-Nov-2001 Version -01 -02 First Issue LFBGA66 mechanical data updated (Table 37) Revision Details 42/46 M36DR432A, M36DR432B Table 37. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Package Mechanical Data Symbol A A1 A2 b D D1 D2 ddd E E1 e FD FE SD SE 8.000 5.600 0.800 1.600 1.200 0.400 0.400 – – – – – – – 0.400 12.000 5.600 8.800 0.350 – – – 0.250 1.100 0.450 – – – 0.100 – – – – – – – 0.3150 0.2205 0.0315 0.0630 0.0472 0.0157 0.0157 – – – – – – – 0.0157 0.4724 0.2205 0.3465 0.0138 – – – millimeters Typ Min Max 1.400 0.0098 0.0433 0.0177 – – – 0.0039 – – – – – – – Typ inches Min Max 0.0551 Figure 25. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Bottom View Package Outline D D2 D1 SE E E1 BALL "A1" b e FE A FD SD e A2 A1 ddd BGA-Z12 Note: Drawing is not to scale. 43/46 M36DR432A, M36DR432B Figure 26. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) #1 #2 1 2 3 4 5 6 7 8 #3 #4 A B C D E F G H AI90251 44/46 M36DR432A, M36DR432B Figure 27. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package) START POINT END POINT #1 #2 1 2 3 4 5 6 7 8 #3 #4 A B C D E F G H AI90252 45/46 M36DR432A, M36DR432B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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