M36L0T7050T0ZAQE

M36L0T7050T0 M36L0T7050B0 128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 32Mbit (2M x16) PSRAM, Multi-Chip Package FEATURES SUMMARY MULTI-CHIP PACKAGE – 1 die of 128Mbit (8Mx16, Multiple Bank, Multi-level, Burst) Flash Memory – 1 die of 32Mbit (2Mx16) Pseudo SRAM ■ SUPPLY VOLTAGE – VDDF = 1.7 to 2V – VDDP = VDDQ = 2.7 to 3.3V – VPP = 9V for fast program (12V tolerant) ■ ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code (Top Flash Configuration) M36L0T7050T0: 88C4h – Device Code (Bottom Flash Configuration) M36L0T7050B0: 88C5h ■ PACKAGE – Compliant with Lead-Free Soldering Processes – Lead-Free Versions FLASH MEMORY ■ SYNCHRONOUS / ASYNCHRONOUS READ – Synchronous Burst Read mode: 50MHz – Asynchronous Page Read mode – Random Access: 90ns ■ SYNCHRONOUS BURST READ SUSPEND ■ PROGRAMMING TIME – 10µs typical Word program time using Write to Buffer and Program ■ MEMORY ORGANIZATION – Multiple Bank Memory Array: 8 Mbit Banks – Parameter Blocks (Top or Bottom location) ■ DUAL OPERATIONS – program/erase in one Bank while read in others – No delay between read and write operations ■ SECURITY – 64 bit unique device number – 2112 bit user programmable OTP Cells ■ Figure 1. Package FBGA TFBGA88 (ZAQ) 8 x 10mm BLOCK LOCKING – All blocks locked at power-up – Any combination of blocks can be locked with zero latency – WP for Block Lock-Down – Absolute Write Protection with VPP = VSS ■ COMMON FLASH INTERFACE (CFI) ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK PSRAM ■ ACCESS TIME: 70ns ■ LOW STANDBY CURRENT: 100µA ■ DEEP POWER-DOWN CURRENT: 10µA ■ BYTE CONTROL: UBP/LBP ■ PROGRAMMABLE PARTIAL ARRAY ■ 8 WORD PAGE ACCESS CAPABILITY: 18ns ■ POWER-DOWN MODES – Deep Power-Down ■ – 4 Mbit Partial Array Refresh – 8 Mbit Partial Array Refresh – 16 Mbit Partial Array Refresh December 2004 1/18 M36L0T7050T0, M36L0T7050B0 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Chip Enable (EF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Latch Enable (LF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Clock (KF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Wait (WAITF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable (E1P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable (E2P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output Enable (GP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write Enable (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Upper Byte Enable (UBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Lower Byte Enable (LBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDP Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3. Power-Down Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/18 M36L0T7050T0, M36L0T7050B0 Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5. Figure 5. Figure 6. Table 6. Table 7. Table 8. Table 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline15 Table 10. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data. . . . . 15 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3/18 M36L0T7050T0, M36L0T7050B0 SUMMARY DESCRIPTION The M36L0T7050T0 and M36L0T7050B0 combine two memory devices in a Multi-Chip Package: a 128-Mbit, Multiple Bank Flash memory, the M30L0T7000T0 or M30L0T7000B0, and a 32-Mbit PseudoSRAM, the M69AW048B. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8x10mm, 8x10 ball array, 0.8mm pitch) package. In addition to the standard version, the packages are also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes. The memory is supplied with all the bits erased (set to ‘1’). Figure 2. Logic Diagram VDDQ VDDF 23 A0-A22 DQ0-DQ15 EF GF WF RPF WPF LF KF E1P GP WP E2P UBP LBP M36L0T7050T0 M36L0T7050B0 WAITF RPF WPF KF WAITF Reset Input Write Protect Input Burst Clock Wait Data in Burst Mode Table 1. Signal Names A0-A22 (1) DQ0-DQ15 VDDF VDDQ VPPF VSS VDDP NC DU Address Inputs Common Data Input/Output Power Supply for Flash Memory Flash Memory Power Supply for I/O Buffers Flash Optional Supply Voltage for Fast Program and Erase Ground PSRAM Power Supply Not Connected Internally Do Not Use as Internally Connected Flash Memory Signals LF Latch Enable Input Chip Enable Input Output Enable Input Write Enable Input VPPF VDDP 16 EF GF WF PSRAM Signals E1P GP WP E2P UBP LBP Chip Enable Input Output Enable Input Write Enable Input Power-down Input Upper Byte Enable Input Lower Byte Enable Input Note: 1. A22-A21 are not connected to the PSRAM component. VSS AI08734 4/18 M36L0T7050T0, M36L0T7050B0 Figure 3. TFBGA Connections (Top view through package) 1 2 3 4 5 6 7 8 A DU DU DU DU B A4 A18 A19 VSS VDDF NC A21 A11 C A5 LBP NC VSS NC KF A22 A12 D A3 A17 NC VPPF WP EP A9 A13 E A2 A7 NC WPF LF A20 A10 A15 F A1 A6 UBP RPF WF A8 A14 A16 G A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAITF NC H GP DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 NC J NC GF DQ9 DQ11 DQ4 DQ6 DQ15 VDDQ K EF DU DU NC VDDP NC VDDQ E2P L VSS VSS VDDQ VDDF VSS VSS VSS VSS M DU DU DU DU AI08735 5/18 M36L0T7050T0, M36L0T7050B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A22). Addresses A0-A20 are common inputs for the Flash Memory and the PSRAM components. The other lines (A21-A22) are inputs for the Flash Memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Flash memory Program/Erase Controller or they select the cells to access in the PSRAM. The Flash memory component is accessed through the Chip Enable signal (EF) and through the Write Enable (WF) signal, while the PSRAM is accessed through two Chip Enable signals (E1P and E2P) and the Write Enable signal (WP). Data Input/Output (DQ0-DQ15). In the Flash memory the Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Write Bus operation. In the PSRAM the Upper Byte Data Inputs/Outputs, DQ8-DQ15, carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UBP) is driven Low. The Lower Byte Data Inputs/Outputs, DQ0-DQ7, carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LBP) is driven Low. Flash Chip Enable (EF). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. Flash Output Enable (GF). The Output Enable input controls data output during Flash memory Bus Read operations. Flash Write Enable (WF). The Write Enable controls the Bus Write operation of the Flash memories’ Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M30L0T7000T0 datasheet). Flash Reset (RPF). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 7., Flash DC Characteristics - Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 8., Flash Memory DC Characteristics - Voltages). Flash Latch Enable (LF). Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is Low, VIL, and it is inhibited when Latch Enable is High, VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Flash Clock (KF). The Clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during Asynchronous Read and in write operations. Flash Wait (WAITF). WAIT is a Flash output signal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable is at VIH or Flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable. Chip Enable (E1P). When asserted (Low), the Chip Enable, E1P, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. Chip Enable (E2P). The Chip Enable, E2P, puts the device in Power-down mode (Deep PowerDown, PAR and Standby) when it is driven Low. One of these, Deep Power-Down mode, is the lowest power mode. Output Enable (GP). The Output Enable, GP, provides a high speed tri-state control, allowing 6/18 M36L0T7050T0, M36L0T7050B0 fast read/write cycles to be achieved with the common I/O data bus. Write Enable (WP). The Write Enable, WP, controls the Bus Write operation of the memory. Upper Byte Enable (UBP). The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. Lower Byte Enable (LBP). The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. VDDF Supply Voltage. VDDF provides the power supply to the internal cores of the Flash memory component. It is the main power supply for all Flash operations (Read, Program and Erase). VDDP Supply Voltage. The VDDP Supply Voltage supplies the power for all operations (Read, Write, etc.) and for driving the refresh logic, even when the device is not being accessed. VDDQ Supply Voltage. VDDQ provides the power supply for the Flash Memory I/O pins. This allows all Outputs to be powered independently of the Flash Memory core power supply, VDDF. VPPF Program Supply Voltage. VPPF is both a Flash control input and a Flash power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQ) VPPF is seen as a control input. In this case a voltage lower than VPPLKF gives an absolute protection against Program or Erase, while VPPF > VPP1F enables these functions (see Tables 7 and 8, DC Characteristics for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPHF it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS is the common ground reference for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips. Note: Each Flash memory device in a system should have their supply voltage (VDDF1 and VDDF2) and the program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 6., AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents. 7/18 M36L0T7050T0, M36L0T7050B0 FUNCTIONAL DESCRIPTION The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by three Chip Enable inputs: EF for the Flash memory and E1P and E2P for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The Figure 4. Functional Block Diagram most common example is simultaneous read operations in the Flash memory and the PSRAM which would result in a data bus contention. Therefore it is recommended to put the other device in the high impedance state when reading the selected device. VDDF VPPF VDDQ EF A21-A22 A0-A20 GF WF RPF WPF LF KF VDDP 128 Mbit Flash Memory DQ0-DQ15 WAITF E1P GP WP E2P UBP LBP 32 Mbit PSRAM VSS AI08736 8/18 M36L0T7050T0, M36L0T7050B0 Table 2. Main Operating Modes Operation Flash Read Flash Write Flash Address Latch Flash Output Disable Flash Standby Flash Reset PSRAM Read Flash Memory must be disabled PSRAM Write Output Disable PSRAM Standby PSRAM Deep Power-Down Note: 1. 2. 3. 4. EF VIL VIL VIL VIL VIH X GF VIL VIH X VIH X X WF VIH VIL VIH VIH X X LF VIL(2) VIL(2) VIL X X X RPF VIH VIH VIH VIH VIH VIL WAITF(4) E1P E2P GP WP LBP,UBP DQ15-DQ0 Flash Data Out PSRAM must be disabled Flash Data In Flash Data Out or Hi-Z (3) Hi-Z Hi-Z Hi-Z Any PSRAM mode is allowed Hi-Z Hi-Z VIL VIL VIL Any Flash mode is allowed VIH X VIH VIH VIH VIH VIL VIL VIH VIH X X VIH VIL VIH X X VIL VIL X X X PSRAM data out PSRAM data in Hi-Z Hi-Z Hi-Z X = Don't care. LF can be tied to VIH if the valid address has been previously latched. Depends on GF. WAIT signal polarity is configured using the Set Configuration Register command. See the M30L0T7000T0 datasheet for details. 9/18 M36L0T7050T0, M36L0T7050B0 FLASH MEMORY DEVICE The M36L0T7050T0 and M36L0T7050B0 contain a 128 Mbit Flash memory. For detailed information on how to use the devices, see the M30L0T7000(T/B)0 datasheet which is available from your local STMicroelectronics distributor. PSRAM DEVICE The M36L0T7050T0 and M36L0T7050B0 contain a 32 Mbit PSRAM. This device can be placed in a number of sleep and partial sleep modes (see Table 3.). For detailed information on how to use the Table 3. Power-Down Configuration Data Power-Down Configuration Data Power-Down Modes DQ15–DQ9 Deep Power-Down (default) 4Mb PAR 8Mb PAR 16Mb PAR 0 0 0 0 DQ8-DQ2 0 0 0 0 DQ1 1 1 0 0 DQ0 1 0 1 0 device, see the M69AW048B datasheet which is available from the internet site http://www.st.com or from your local STMicroelectronics distributor. 10/18 M36L0T7050T0, M36L0T7050B0 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 4. Absolute Maximum Ratings Value Symbol TA TBIAS TSTG TLEAD VIO VDDF VDDQ, VDDP VPPF IO tVPPFH Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Lead Temperature during Soldering Input or Output Voltage Flash Memory Core Supply Voltage PSRAM and Input/Output Supply Voltages Flash Program Voltage Output Short Circuit Current Time for VPPF at VPPFH –0.5 –0.2 –0.2 –0.2 –25 –25 –55 Max 85 85 125 (1) plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Unit °C °C °C °C V V V V mA hours 7191395 specification, 3.6 2.5 3.6 14 100 100 ECOPACK® Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 11/18 M36L0T7050T0, M36L0T7050B0 DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 5., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and AC Measurement Conditions Flash Memory Parameter Min VDDF Supply Voltage VDDP Supply Voltage VDDQF Supply Voltage 1.7 – 2.7 8.5 –0.4 –25 30 22 5 0 to VDDQ VDDQ/2 5 0 to VDDQ VDDQ/2 Max 2.0 – 3.3 12.6 VDDQ +0.4 85 Min – 2.7 – – – –30 50 22 Max – 3.3 – – – 85 V V V V V °C pF kΩ ns V V PSRAM Unit VPPF Supply Voltage (Factory environment) VPPF Supply Voltage (Application environment) Ambient Operating Temperature Load Capacitance (CL) Output Circuit Resistors (R1, R2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit VDDQ VDDQ VDDQ/2 0V VDDF VDDQ R1 DEVICE UNDER TEST AI06161 0.1µF 0.1µF CL R2 CL includes JIG capacitance AI08364B Table 6. Device Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 12 15 Unit pF pF Note: Sampled only, not 100% tested. 12/18 M36L0T7050T0, M36L0T7050B0 Table 7. Flash DC Characteristics - Currents Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=6MHz) Test Condition 0V ≤ VIN ≤ VDDQ 0V ≤ VOUT ≤ VDDQ EF = VIL, GF = VIH 4 Word Supply Current Synchronous Read (f=40MHz) IDD1 8 Word 16Word Continuous 4 Word Supply Current Synchronous Read (f=50MHz) 8 Word 16 Word Continuous IDD2 IDD3 IDD4 Supply Current (Reset) Supply Current (Standby) Supply Current (Automatic Standby) Supply Current (Program) IDD5 (1) Supply Current (Erase) VPPF = VDDF Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read in another Bank E = VDD ± 0.2V VPPF = VPPH VPPF = VDDF VPPF = VPPH VPPF = VDDF VPPF ≤ VDDF VPPF ≤ VDDF 10 24 20 36 mA mA VPPF = VDDF VPPF = VPPH 10 8 20 15 mA mA RPF = VSS ± 0.2V EF = VDDF ± 0.2V EF = VIL, GF = VIH VPPF = VPPH 14 13 15 17 21 16 19 22 23 25 25 25 8 Min Typ Max ±2 ±10 16 17 19 21 26 19 23 26 28 75 75 75 15 Unit µA µA mA mA mA mA mA mA mA mA mA µA µA µA mA Supply Current IDD6 (1,2) (Dual Operations) 40 55 mA IDD7(1) Supply Current Program/ Erase Suspended (Standby) VPPF Supply Current (Program) 25 2 0.2 2 0.2 0.2 0.2 75 5 5 5 5 5 5 µA mA µA mA µA µA µA IPP1(1) VPPF Supply Current (Erase) IPP2 IPP3(1) VPPF Supply Current (Read) VPPF Supply Current (Standby) Note: 1. Sampled only, not 100% tested. 2. VDD Dual Operation current is the sum of read and program or erase currents. 13/18 M36L0T7050T0, M36L0T7050B0 Table 8. Flash Memory DC Characteristics - Voltages Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPPF Program Voltage-Logic VPPF Program Voltage Factory Program or Erase Lockout VDDF Lock Voltage RPF pin Extended High Voltage 1 3.3 IOL = 100µA IOH = –100µA Program, Erase Program, Erase VDDQ –0.1 1.1 8.5 1.8 9.0 3.3 12.6 0.4 Test Condition Min –0.5 VDDQ –0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V V Table 9. PSRAM DC Characteristics Symbol ICC1 VDDP Active Current ICC2 Parameter Test Condition tRC / tWC = VDDP = 3.3V, minimum VIN = VIH or VIL, E1P = VIL and E2P = VIH, tRC / tWC = IOUT = 0mA 1 µs VDDP = 3.3V, VIN = VIH or VIL, E1P = VIL and E2P = VIH, IOUT = 0mA, tPRC = min. Deep PowerDown 4 Mb PAR 8 Mb PAR 16 Mb PAR Input Leakage Current Output Leakage Current Standby Supply Current CMOS Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage VDDP = 2.7V, IOH = –0.5mA IOL = 1mA 0V ≤ VIN ≤ VDDP 0V ≤ VOUT ≤ VDDP VDDP = 3.3V, VIN ≤ 0.2V or VIN ≥ VDDP –0.2V, E1P = E2P ≥ VDDP –0.2V 0.8VDDP –0.3 2.4 0.4 –1 –1 Min Max 30 3 Unit mA mA ICC3 VDDP Page Read Current 10 mA ICCPD ICCP4 ICCP8 ICCP16 ILI ILO ISB VIH (1) VIL (2) VOH VOL VDDP Power Down Current VDDP = 3.3V, VIN = VIH or VIL, E2P ≤ 0.2V 10 40 50 65 1 1 100 VDDP + 0.2 0.2VDDP µA µA µA µA µA µA µA V V V V Note: 1. Maximum DC voltage on input and I/O pins is VDDP + 0.2V. During voltage transitions, input may positive overshoot to VDDP + 1.0V for a period of up to 5ns. 2. Minimum DC voltage on input or I/O pins is –0.3V. During voltage transitions, input may positive overshoot to VSS + 1.0V for a period of up to 5ns. 14/18 M36L0T7050T0, M36L0T7050B0 PACKAGE MECHANICAL Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline D D1 e SE E E2 E1 b BALL "A1" ddd FE FE1 A A1 FD SD A2 BGA-Z42 Note: Drawing is not to scale. Table 10. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 E2 e FD FE FE1 SD SE 10.000 7.200 8.800 0.800 1.200 1.400 0.600 0.400 0.400 – – 9.900 0.850 0.350 8.000 5.600 0.100 10.100 0.3937 0.2835 0.3465 0.0315 0.0472 0.0551 0.0236 0.0157 0.0157 – – 0.3898 0.300 7.900 0.400 8.100 0.200 0.0335 0.0138 0.3150 0.2205 0.0039 0.3976 0.0118 0.3110 0.0157 0.3189 Min Max 1.200 0.0079 Typ Min Max 0.0472 inches 15/18 M36L0T7050T0, M36L0T7050B0 PART NUMBERING Table 11. Ordering Information Scheme Example: Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture 0 = No Die Operating Voltage T = VDDF = 1.7 to 2V; VDDQ = VDDP = 2.7 to 3.3V Flash 1 Density 7 = 128 Mbit Flash 2 Density 0 = No Die RAM 1 Density 5 = 32 Mbit RAM 0 Density 0 = No Die Parameter Blocks Location T = Top Boot Block Flash B = Bottom Boot Block Flash Product Version 0 = 0.13µm Flash technology, 90ns speeds; 0.18µm RAM, 70ns speed Package ZAQ = Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch Option Blank = Standard Packing T = Tape & Reel Packing E= lead-free and RoHS package, standard packing F= lead-free and RoHS package, tape and reel packing M36 L 0 T 7 0 5 0 T 0 ZAQ T Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 16/18 M36L0T7050T0, M36L0T7050B0 REVISION HISTORY Table 12. Document Revision History Date 29-Jul-2003 Version 0.1 First Issue Document status promoted from Target Specification to full Datasheet. TFBGA88 package specifications updated, package fully compliant with the ST ECOPACK specification. Flash memory and PSRAM data updated to the version 0.2 of the M30L0T7000x0 datasheet and to the version 5.0 of the M69AW048B datasheet. Revision Details 10-Dec-2004 1.0 17/18 M36L0T7050T0, M36L0T7050B0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 18/18