M40SZ100WMQ6F

M40SZ100W 3 V NVRAM supervisor for LPSRAM Datasheet - production data Description The M40SZ100W NVRAM controller is a selfcontained device which converts a standard lowpower SRAM into a non-volatile memory. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. 16 1 SO16 Features  Convert low power SRAMs into NVRAMs  3 V operating voltage  Precision power monitoring and power switching circuitry When an invalid VCC condition occurs, the conditioned chip enable output (ECON) is forced inactive to write protect the stored data in the SRAM. During a power failure, the SRAM is switched from the VCC pin to the external battery to provide the energy required for data retention. On a subsequent power-up, the SRAM remains write-protected until a valid power condition returns.  Automatic write-protection when VCC is out-oftolerance  Choice of supply voltage and power-fail deselect voltage: – VCC = 2.7 to 3.6 V; 2.55 V  VPFD  2.70 V  Reset output (RST) for power on reset  1.25 V reference (for PFI/PFO)  Less than 15 ns chip enable access propagation delay  Battery low pin (BL)  RoHS compliant – Lead-free second level interconnect December 2013 This is information on a product in full production. DocID007528 Rev 4 1/20 www.st.com Contents M40SZ100W Contents 1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Data retention lifetime calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Power-on reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Reset input (RSTIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 Battery low pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 DocID007528 Rev 4 M40SZ100W List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Power-down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reset AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SO16 – 16-lead plastic small outline package mechanical data. . . . . . . . . . . . . . . . . . . . . 17 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DocID007528 Rev 4 3/20 20 List of figures M40SZ100W List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. 4/20 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 RSTIN timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SO16 – 16-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DocID007528 Rev 4 M40SZ100W 1 Device overview Device overview Figure 1. Logic diagram VCC VBAT VOUT E BL M40SZ100W PFI ECON PFO RSTIN RST VSS AI03933 Table 1. Signal names E Chip enable input ECON Conditioned chip enable output RST Reset output (open drain) RSTIN BL Reset input Battery low output (open drain) VOUT Supply voltage output VCC Supply voltage VBAT Backup supply voltage PFI Power fail input PFO Power fail output VSS Ground NC Not connected internally DocID007528 Rev 4 5/20 20 Device overview M40SZ100W Figure 2. Pin connections NC NC RST NC RSTIN PFO VBAT VSS VCC NC VOUT NC PFI BL E ECON 1 16 2 15 14 3 4 M40SZ100W 13 12 5 6 11 7 10 8 9 AI03935 Figure 3. Block diagram VOUT VCC VBAT VBL= 2.5V COMPARE VSO = 2.5V COMPARE VPFD= 2.65V COMPARE BL (1) POR RSTIN RST(1) E ECON PFI 1.25V COMPARE PFO AI04766 1. Open drain output 6/20 DocID007528 Rev 4 M40SZ100W Device overview Figure 4. Hardware hookup 3.0V, 3.3V Regulator Unregulated Voltage VIN VCC VCC 0.1μF VOUT VCC M40SZ100W 0.1μF E From Microprocessor RSTIN R1 1Mb or 4Mb LPSRAM E ECON PFI PFO To Microprocessor NMI VSS RST To Microprocessor Reset BL To Battery Monitor Circuit R2 VBAT AI04767 DocID007528 Rev 4 7/20 20 Operation 2 M40SZ100W Operation The M40SZ100W, as shown in Figure 4 on page 7, can control one (two, if placed in parallel) standard low-power SRAM. This SRAM must be configured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not. During normal operating conditions, the conditioned chip enable (ECON) output pin follows the chip enable (E) input pin with timing shown in Table 2 on page 10. An internal switch connects VCC to VOUT. This switch has a voltage drop of less than 0.3 V (IOUT1). When VCC degrades during a power failure, ECON is forced inactive independent of E. In this situation, the SRAM is unconditionally write protected as VCC falls below an out-oftolerance threshold (VPFD). For the M40SZ100W the power fail detection value associated with VPFD is shown in Table 7 on page 16. If chip enable access is in progress during a power fail detection, that memory cycle continues to completion before the memory is write protected. If the memory cycle is not terminated within time tWPT, ECON is unconditionally driven high, write protecting the SRAM. A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the SRAM's contents. At voltages below VPFD (min), the user can be assured the memory will be write protected within the Write Protect Time (tWPT) provided the VCC fall time does not exceed tF (see Table 2 on page 10). As VCC continues to degrade, the internal switch disconnects VCC and connects the internal battery to VOUT. This occurs at the switchover voltage (VSO). Below the VSO, the battery provides a voltage VOHB to the SRAM and can supply current IOUT2 (see Table 7 on page 16). When VCC rises above VSO, VOUT is switched back to the supply voltage. Output ECON is held inactive for tCER (120 ms maximum) after the power supply has reached VPFD, independent of the E input, to allow for processor stabilization (see Figure 6 on page 10). 2.1 Data retention lifetime calculation Most low power SRAMs on the market today can be used with the M40SZ100W NVRAM controller. There are, however some criteria which should be used in making the final choice of which SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M40SZ100W and SRAMs to be “Don't care” once VCC falls below VPFD(min) (see Figure 5 on page 9). The SRAM should also guarantee data retention down to VCC = 2.0 V. The chip enable access time must be sufficient to meet the system needs with the chip enable propagation delays included. If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0 V. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the ICCDR value of the M40SZ100W to determine the total current requirements for data retention. Caution: 8/20 Take care to avoid inadvertent discharge through VOUT and ECON after battery has been attached. DocID007528 Rev 4 M40SZ100W Operation For a further more detailed review of lifetime calculations, please see application note AN1012. Figure 5. Power-down timing VCC VPFD (max) VPFD VPFD (min) VSO tF tFB E tWPT VOHB ECON RST PFO VALID AI03936 DocID007528 Rev 4 9/20 20 Operation M40SZ100W Figure 6. Power-up timing VCC VPFD (max) VPFD VPFD (min) VSO tR tRB tCER E tEPD ECON tEPD VOHB tREC RST PFO VALID AI03937 Table 2. Power-down/up AC characteristics Parameter(1) Symbol tF (2) VPFD (max) to VPFD (min) VCC fall time Min 300 tFB(3) VPFD (min) to VSS VCC fall time 10 tPFD PFI to PFO propagation delay 15 VPFD(min) to VPFD (max) VCC rise time 10 tR Max tEPD Chip enable propagation delay (low or high) tRB VSS to VPFD (min) VCC rise time 1 Unit μs μs 25 μs μs 15 ns μs tCER Chip enable recovery 40 120 ms tREC VPFD (max) to RST high 40 200 ms tWPT Write protect time 40 200 μs 1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.7 to 3.6 V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 μs after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. 10/20 DocID007528 Rev 4 M40SZ100W 2.2 Operation Power-on reset output All microprocessors have a reset input which forces them to a known state when starting. The M40SZ100W has a reset output (RST) pin which is guaranteed to be low by VPFD (see Table 7 on page 16). This signal is an open drain configuration. An appropriate pull-up resistor to VCC should be chosen to control the rise time. This signal will be valid for all voltage conditions, even when VCC equals VSS (with valid battery voltage). Once VCC exceeds the power failure detect voltage VPFD, an internal timer keeps RST low for tREC to allow the power supply to stabilize. 2.3 Reset input (RSTIN) The M40SZ100W provides one independent input which can generate an output reset. The duration and function of this reset is identical to a reset generated by a power cycle. Table 3 and Figure 7 illustrate the AC reset characteristics of this function. Pulses shorter than tRLRH will not generate a reset condition. RSTIN is internally pulled up to VCC through a 100 k resistor. Figure 7. RSTIN timing waveform RSTIN tRLRH RST (1) tR1HRH AI04768 1. With pull-up resistor Table 3. Reset AC characteristics Parameter(1) Symbol tRLRH (2) tR1HRH(3) Min RSTIN low to RSTIN high 200 RSTIN high to RST high 40 Max Unit 200 ms ns 1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.7 to 3.6 V (except where noted). 2. Pulse width less than 50 ns will result in no RESET (for noise immunity). 3. CL = 50 pF (see Figure 9 on page 15). 2.4 Battery low pin The M40SZ100W automatically performs battery voltage monitoring upon power-up, and at factory-programmed time intervals of at least 24 hours. The Battery Low (BL) pin will be asserted if the battery voltage is found to be less than approximately 2.5 V. The BL pin will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. DocID007528 Rev 4 11/20 20 Operation M40SZ100W If a battery low is generated during a power-up sequence, this indicates that the battery is below 2.5 V and may not be able to maintain data integrity in the SRAM. Data should be considered suspect, and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. The M40SZ100W only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery backup mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. The BL pin is an open drain output and an appropriate pull-up resistor to VCC should be chosen to control the rise time. 2.5 Power-fail input/output The power-fail input (PFI) is compared to an internal reference voltage (independent from the VPFD comparator). If PFI is less than the power-fail threshold (VPFI), the power-fail output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure 4 on page 7) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the M40SZ100W or the microprocessor drops below the minimum operating voltage. During battery backup, the power-fail comparator turns off and PFO goes (or remains) low. This occurs after VCC drops below VPFD(min). When power returns, PFO is forced high, irrespective of VPFI for the write protect time (tREC), which is the time from VPFD (max) until the inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. 2.6 VCC noise and negative going transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 μF (as shown in Figure 8 on page 13) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. 12/20 DocID007528 Rev 4 M40SZ100W Operation Figure 8. Supply voltage protection VCC VCC 0.1µF DEVICE VSS AI00622 DocID007528 Rev 4 13/20 20 Maximum ratings 3 M40SZ100W Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Absolute maximum ratings Symbol TSTG TSLD (1) Parameter Storage temperature (VCC off) Lead solder temperature for 10 seconds Value Unit –55 to 125 °C 260 °C –0.3 to VCC +0.3 V Supply voltage –0.3 to 4.6 V IO Output current 20 mA PD Power dissipation 1 W VIO Input or output voltages VCC 1. For SO package, Lead-free (Pb-free) lead finish: reflow at peak temperature of 260 °C (the time above 255 °C must not exceed 30 seconds). Caution: 14/20 Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode. DocID007528 Rev 4 M40SZ100W 4 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in Table 5: DC and AC measurement conditions. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 5. DC and AC measurement conditions Parameter Value VCC supply voltage 2.7 to 3.6 V Ambient operating temperature –40 to 85 °C Load capacitance (CL) 50 pF Input rise and fall times  5 ns Input pulse voltages 0.2 to 0.8VCC Input and output timing ref. voltages 0.3 to 0.7VCC Figure 9. AC testing load circuit 333 DEVICE UNDER TEST CL = 50pF 1.73V CL includes JIG capacitance AI02393 Figure 10. AC testing input/output waveforms 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI02568 Table 6. Capacitance Parameter(1)(2) Symbol CIN COUT (3) Min Max Unit Input capacitance - 7 pF Output capacitance - 10 pF 1. Sampled only, not 100% tested. 2. At 25 °C, f = 1 MHz. 3. Outputs deselected. DocID007528 Rev 4 15/20 20 DC and AC parameters M40SZ100W Table 7. DC characteristics Sym ICC ICCDR ILI(3) ILO(4) Test condition(1) Parameter Supply current Min Typ Outputs open (2) Data retention mode current 50 0 V  VIN  VCC Input leakage current Input leakage current (PFI) –25 2 Max Unit 0.5 mA 200 nA ±1 μA 25 nA Output leakage current 0 V  VOUT  VCC ±1 μA VOUT current (active) VOUT > VCC – 0.3 100 mA IOUT2 VOUT current (battery backup) VOUT > VBAT – 0.3 100 μA VBAT Battery voltage 3.5(6) V IOUT1(5) 2.5 3.0 VIH Input high voltage 0.7VCC VCC + 0.3 V VIL Input low voltage –0.3 0.3VCC V voltage(6) VOH Output high VOHB VOH battery backup(7) IOH = –1.0 mA 2.4 IOUT2 = –1.0 μA 2.5 V 2.9 3.5 V Output low voltage IOL = 3.0 mA 0.4 V VOL Output low voltage (open drain)(8) IOL = 10 mA 0.4 V VPFD Power-fail deselect voltage VPFI VSO PFI input threshold VCC = 3 V PFI hysteresis PFI rising Battery backup switchover voltage 2.55 2.60 2.70 V 1.225 1.250 1.275 V 20 70 mV 2.5 1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.7 to 3.6 V (except where noted). 2. Measured with VOUT and ECON open. 3. RSTIN internally pulled-up to VCC through 100 k resistor. 4. Outputs deselected. 5. External SRAM must match SUPERVISOR chip VCC specification. 6. For PFO pin (CMOS). 7. Chip enable output (ECON) can only sustain CMOS leakage currents in the battery backup mode. Higher leakage currents will reduce battery life. 8. For RST & BL pins (open drain). 16/20 DocID007528 Rev 4 V M40SZ100W 5 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 11. SO16 – 16-lead plastic small package outline A2 A C B CP e D N E H 1 A1 α L SO-b Note: Drawing is not to scale. Table 8. SO16 – 16-lead plastic small outline package mechanical data Symbol mm Typ. inches Min. Max. 0.10 0.25 A Typ. Min. Max. 0.004 0.010 1.75 A1 A2 0.069 1.60 0.063 B 0.35 0.46 0.014 0.018 C 0.19 0.25 0.007 0.010 D 9.80 10.00 0.386 0.394 E 3.80 4.00 0.150 0.158 – – – – H 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 a 0° 8° 0° 8° N 16 e CP 1.27 0.050 16 0.10 DocID007528 Rev 4 0.004 17/20 20 Part numbering 6 M40SZ100W Part numbering Table 9. Ordering information scheme Example: M40SZ 100W MQ 6 F Device type M40SZ Supply voltage and write protect voltage 100W = VCC = 2.7 to 3.6 V; VPFD = 2.6 to 2.7 V Package MQ = SO16 Temperature range 6 = –40 to 85 °C Shipping method F = Lead-free ECOPACK® package, tape & reel For a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the ST sales office nearest to you. 18/20 DocID007528 Rev 4 M40SZ100W 7 Revision history Revision history Table 10. Document revision history Date Revision Dec-2001 1.0 Changes First issue 13-May-2002 1.1 Modify reflow time and temperature footnote (Table 4) 01-Aug-2002 1.2 Add marketing status (cover page; Table 9) 15-Sep-2003 1.3 Remove reference to M68xxx (obsolete) part (Figure 4); update disclaimer 20-Nov-2007 2 Reformatted document; added lead-free second level interconnect information to cover page and Section 5: Package mechanical data; updated Table 4 and 9. 25-Oct-2010 3 Updated cover page, Section 3, Table 9, ECOPACK® text in Section 5; reformatted document; minor textual changes. 16-Dec-2013 4 Removed SNAPHAT and SOH28 package option as well as 5 V part (M40SZ100Y) from datasheet Removed shipping option in tubes from Table 9 DocID007528 Rev 4 19/20 20 M40SZ100W Please Read Carefully: Information in this document is provided solely in connection with ST products. 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