M40Z111
M40Z111W
5V or 3V NVRAM supervisor for up to two LPSRAMs
Features
■
Convert low power SRAMs into NVRAMs
■
Precision power monitoring and power
switching circuitry
■
Automatic write-protection when VCC is out-oftolerance
■
Choice of supply voltages and
power-fail deselect voltages:
– M40Z111: VCC = 4.5 to 5.5V
THS = VSS; 4.5 ≤ VPFD ≤ 4.75V
THS = VOUT; 4.2 ≤ VPFD ≤ 4.5V
– M40Z111W: VCC = 3.0 to 3.6V
THS = VSS; 2.8 ≤ VPFD ≤ 3.0V
VCC = 2.7 to 3.3V
THS = VOUT; 2.5 ≤ VPFD ≤ 2.7V
■
Less than 15ns chip enable access
propagation delay (for 5.0v device)
■
Packaging includes a 28-lead SOIC and
SNAPHAT® top (to be ordered separately)
■
SOIC package provides direct connection for a
SNAPHAT top which contains the battery
■
RoHS compliant
– Lead-free second level interconnect
November 2007
SNAPHAT (SH)
battery
28
1
SOH28 (MH)
Rev 4
1/21
www.st.com
1
Contents
M40Z111, M40Z111W
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Data retention lifetime calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
M40Z111, M40Z111W
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech. data . . . . . . . . . . 16
4-pin SNAPHAT housing for 48mAh battery, package mechanical data . . . . . . . . . . . . . . 17
4-pin SNAPHAT housing for 120mAh battery, package mechanical data . . . . . . . . . . . . . 18
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3/21
List of figures
M40Z111, M40Z111W
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
4/21
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SOIC28 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline . . . . 15
4-pin SNAPHAT housing for 48mAh battery, package outline . . . . . . . . . . . . . . . . . . . . . . 17
4-pin SNAPHAT housing for 120mAh battery, package outline . . . . . . . . . . . . . . . . . . . . . 18
M40Z111, M40Z111W
1
Description
Description
The M40Z111/W NVRAM supervisor is a self-contained device which converts a standard
low-power SRAM into a non-volatile memory.
A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance
condition.
When an invalid VCC condition occurs, the conditioned chip enable (ECON) output is forced
inactive to write-protect the stored data in the SRAM.
During a power failure, the SRAM is switched from the VCC pin to the lithium cell within the
SNAPHAT® to provide the energy required for data retention. On a subsequent power-up,
the SRAM remains write protected until a valid power condition returns.
The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT housing containing the battery. The unique design
allows the SNAPHAT battery package to be mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the
high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to
prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape
& Reel form. For the 28-lead SOIC, the battery package (e.g., SNAPHAT) part number is
“M4Z28-BR00SH1” or “M4Z32-BR00SH1” (See Table 11 on page 19).
Figure 1.
Logic diagram
VCC
THS
VOUT
M40Z111
M40Z111W
E
ECON
VSS
AI02238B
5/21
Description
M40Z111, M40Z111W
Table 1.
Signal names
THS
E
Threshold select input
Chip enable input
ECON
Conditioned chip enable output
VOUT
Supply voltage output
VCC
Supply voltage
VSS
Ground
NC
Not connected internally
Figure 2.
SOIC28 connections
VOUT
NC
NC
NC
NC
VCC
NC
VCC
NC
NC
NC
NC
THS
VSS
28
1
2
27
3
26
4
25
5
24
6
23
7 M40Z111 22
8 M40Z111W 21
9
20
10
19
11
18
12
17
13
16
14
15
AI02239B
6/21
VCC
E
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
ECON
NC
M40Z111, M40Z111W
Figure 3.
Description
Hardware hookup
3.0, 3.3, or 5V
VCC
VOUT
VCC
E2
1N5817 or
MBR5120T3
0.1μF
M40Z111/W
E
Thereshold
CMOS
SRAM
0.1μF
ECON
E
x8 or x16
THS
VSS
AI02394
7/21
Operation
2
M40Z111, M40Z111W
Operation
The M40Z111/W, as shown in Figure 3 on page 7, can control up to two standard low-power
SRAMs. These SRAMs must be configured to have the chip enable input disable all other
input signals. Most slow, low-power SRAMs are configured like this, however many fast
SRAMs are not. During normal operating conditions, the conditioned chip enable (ECON)
output pin follows the chip enable (E) input pin with timing shown in Table 2 on page 10. An
internal switch connects VCC to VOUT. This switch has a voltage drop of less than 0.3V
(IOUT1).
When VCC degrades during a power failure, ECON is forced inactive independent of E. In this
situation, the SRAM is unconditionally write protected as VCC falls below an out-of-tolerance
threshold (VPFD). The power fail detection value associated with VPFD is selected by the
THS pin and is shown in Table 6 on page 14.
Note:
Note: The THS pin must be connected to either VSS or VOUT.
If chip enable access is in progress during a power fail detection, that memory cycle
continues to completion before the memory is write protected. If the memory cycle is not
terminated within time tWP, ECON is unconditionally driven high, write protecting the SRAM.
A power failure during a write cycle may corrupt data at the currently addressed location, but
does not jeopardize the rest of the SRAM's contents. At voltages below VPFD (min), the user
can be assured the memory will be write protected provided the VCC fall time exceeds tF.
As VCC continues to degrade, the internal switch disconnects VCC and connects the internal
battery to VOUT. This occurs at the switchover voltage (VSO). Below the VSO, the battery
provides a voltage VOHB to the SRAM and can supply current IOUT2 (see Table 6 on
page 14). When VCC rises above VSO, VOUT is switched back to the supply voltage. Output
ECON is held inactive for tER (200ms maximum) after the power supply has reached VPFD,
independent of the E input, to allow for processor stabilization (see Figure 5 on page 9).
2.1
Data retention lifetime calculation
Most low power SRAMs on the market today can be used with the M40Z111/W NVRAM
SUPERVISOR. There are, however some criteria which should be used in making the final
choice of which SRAM to use. The SRAM must be designed in a way where the chip enable
input disables all other inputs to the SRAM. This allows inputs to the M40Z111/W and
SRAMs to be “Don't Care” once VCC falls below VPFD (min). The SRAM should also
guarantee data retention down to VCC = 2.0V. The chip enable access time must be
sufficient to meet the system needs with the chip enable propagation delays included. If the
SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT. If data
retention lifetime is a critical parameter for the system, it is important to review the data
retention current specifications for the particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0V.
Manufacturers generally specify a typical condition for room temperature along with a worst
case condition (generally at elevated temperatures). The system level requirements will
determine the choice of which value to use. The data retention current value of the SRAMs
can then be added to the ICCDR value of the M40Z111/W to determine the total current
requirements for data retention.
8/21
M40Z111, M40Z111W
Operation
The available battery capacity for the SNAPHAT® of your choice can then be divided by this
current to determine the amount of data retention available (see Table 11 on page 19). For
more information on Battery Storage Life refer to the Application Note AN1012.
Figure 4.
Power down timing
VCC
VPFD (max)
VPFD
VPFD (min)
VSO
tF
tFB
E
tWPT
VOHB
ECON
AI02396
Figure 5.
Power up timing
VCC
VPFD (max)
VPFD
VPFD (min)
VSO
tR
tRB
tER
E
tEDH
ECON
tEDL
VOHB
AI02397
9/21
Operation
M40Z111, M40Z111W
Table 2.
Power down/up AC characteristics
Parameter(1)
Symbol
Min
Max
Unit
tF(2)
VPFD (max) to VPFD (min) VCC fall time
300
µs
tFB(3)
VPFD (min) to VSS VCC fall time
10
µs
tR
VPFD (min) to VPFD (max) VCC rise time
10
µs
tRB
VSS to VPFD (min) VCC rise time
1
µs
tEDL
Chip enable propagation delay
tEDH
Chip enable propagation delay
tER(4)
Chip enable recovery
tWPT
Write protect time
M40Z111
15
ns
M40Z111W
20
ns
M40Z111
10
ns
M40Z111W
20
ns
40
200
ms
M40Z111
40
150
µs
M40Z111W
40
250
µs
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where
noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring
until 200 µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
4. tER (min) = 20ms for industrial temperature range - grade 6 device.
2.2
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in
Figure 6) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS).
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
10/21
M40Z111, M40Z111W
Figure 6.
Operation
Supply voltage protection
VCC
VCC
0.1μF
DEVICE
VSS
AI00622
11/21
Maximum rating
3
M40Z111, M40Z111W
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 3.
Absolute maximum ratings
Symbol
TA
TSTG
TSLD(1)
VIO
VCC
Parameter
Value
Unit
Grade 6
–40 to 85
°C
SNAPHAT®
–40 to 85
°C
SOIC
–55 to 125
°C
260
°C
–0.3 to VCC +0.3
V
M40Z111
–0.3 to 7.0
V
M40Z111W
–0.3 to 4.6
V
Ambient operating temperature
Storage temperature (VCC off)
Lead solder temperature for 10 seconds
Input or output voltages
Supply voltage
IO
Output current
20
mA
PD
Power dissipation
1
W
1. For SO package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260°C (total thermal budget
not to exceed 245°C for greater than 30 seconds).
Caution:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up
mode.
Caution:
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
12/21
M40Z111, M40Z111W
4
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in Table 4:
DC and AC measurement conditions. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 4.
DC and AC measurement conditions
Parameter
M40Z111
M40Z111W
VCC supply voltage
4.5 to 5.5V
2.7 to 3.6V
Ambient operating temperature
–40 to 85°C
–40 to 85°C
Load capacitance (CL)
100pF
50pF
Input rise and fall times
≤ 5ns
≤ 5ns
0 to 3V
0 to 3V
1.5V
1.5V
Input pulse voltages
Input and output timing ref. voltages
Note:
Note that Output Hi-Z is defined as the point where data is no longer driven.
Figure 7.
AC testing load circuit
645Ω
DEVICE
UNDER
TEST
(1)
CL = 100pF
or 5pF
CL includes JIG capacitance
1.75V
AI02326
1. 50pF for M40Z111W.
Table 5.
Capacitance
Parameter(1)(2)
Symbol
CIN
COUT
(3)
Min
Max
Unit
Input capacitance
8
pF
Output capacitance
10
pF
1. Effective capacitance measured with power supply at 5V (M40Z111) or 3.3V (M40Z111W); sampled only,
not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected
13/21
DC and AC parameters
Table 6.
Sym
M40Z111, M40Z111W
DC characteristics
Parameter
M40Z111
Test condition(1)
Unit
Min
ICC
Supply current
Outputs open
Typ
Max
3
6
Data retention mode
ICCDR
current
ILI
Input leakage current
M40Z111W
Min
Typ
Max
2
4
mA
150
150
nA
0V ≤ VIN ≤ VCC
±1
±1
µA
0V ≤ VOUT ≤ VCC
±1
±1
µA
VOUT > VCC –0.3
160
100
mA
VOUT > VCC –0.2
100
65
mA
ILO(2)
Output leakage current
IOUT1
VOUT current (active)
IOUT2
VOUT current (battery
back-up)
VBAT
Battery voltage
2.0
VIH
Input high voltage
VIL
Input low voltage
VOH
Output high voltage
IOH = –2.0mA
2.4
VOHB
VOH battery back-up
IOUT2 = –1.0µA
2.0
VOUT > VBAT –0.3
100
3.0
100
3.5
2.0
2.2
VCC + 0.3
–0.3
0.8
3.5
V
2.0
VCC +
0.3
V
–0.3
0.8
V
2.4
2.9
2.0
Output low voltage
THS
Threshold select voltage
VSS
VOUT
VSS
Power-fail deselect
voltage (THS = VSS)
4.50 4.60
4.75
2.80
Power-fail deselect
voltage (THS = VOUT)
4.20 4.35
4.50
2.50
VSO
Battery back-up
switchover voltage
IOL = 4.0mA
3.6
VOL
VPFD
3.0
µA
V
2.9
3.6
V
0.4
V
VOUT
V
2.90
3.00
V
2.60
2.70
V
0.4
3.0
VPFD –
100mV
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. Outputs deselected.
14/21
V
M40Z111, M40Z111W
5
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 8.
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT,
package outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note:
Drawing is not to scale.
15/21
Package mechanical data
Table 7.
M40Z111, M40Z111W
SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech. data
mm
inches
Symbol
Typ
Min
A
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
a
0°
8°
0°
8°
N
28
e
CP
16/21
Max
1.27
0.050
28
0.10
0.004
M40Z111, M40Z111W
Figure 9.
Package mechanical data
4-pin SNAPHAT housing for 48mAh battery, package outline
A1
A2
A3
A
eA
B
L
eB
D
E
SHZP-A
Note:
Drawing is not to scale.
Table 8.
4-pin SNAPHAT housing for 48mAh battery, package mechanical data
mm
inches
Symbol
Typ
Min
A
Max
Typ
Min
9.78
Max
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
17/21
Package mechanical data
M40Z111, M40Z111W
Figure 10. 4-pin SNAPHAT housing for 120mAh battery, package outline
A1
A2
A3
A
eA
B
L
eB
D
E
SHZP-A
Note:
Drawing is not to scale.
Table 9.
4-pin SNAPHAT housing for 120mAh battery, package mechanical data
mm
inches
Symbol
Typ
Min
A
Typ
Min
10.54
Max
0.415
A1
8.00
8.51
0.315
0.335
A2
7.24
8.00
0.285
0.315
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
0.710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
A3
18/21
Max
0.38
0.015
M40Z111, M40Z111W
6
Part numbering
Part numbering
Table 10.
Ordering information scheme
Example:
M40Z
111W
MH
6
E
Device type
M40Z
Supply voltage and write protect voltage
111 = VCC = 4.5 to 5.5V; VPFD = 4.3 to 4.5V
THS = VSS = 4.5 ≤ VPFD ≤ 4.75V
THS = VOUT = 4.2 ≤ VPFD ≤ 4.5V
111W = VCC = 2.7 to 3.6V; VPFD = 2.6 to 2.7V
THS = VSS = 2.8 ≤ VPFD ≤ 3.0V
VCC = 2.7 to 3.3V
THS = VOUT = 2.5 ≤ VPFD ≤ 2.7V
Package
MH(1) = SOH28
Temperature range
6 = –40 to 85°C
Shipping method for SOIC
E = Lead-free ECOPACK® package, tubes
F = Lead-free ECOPACK® package, tape & reel
1. The SOIC package (SOH28) requires the battery package (SNAPHAT®) which is ordered separately under
the part number “M4ZXX-BR00SHX” in plastic tubes or “M4ZXX-BR00SHXTR” in tape & reel form.
Caution:
Do not place the SNAPHAT battery package “M4ZXX-BR00SH” in conductive foam as this
will drain the lithium button-cell battery.
For a list of available options (e.g., speed, package) or for further information on any aspect
of this device, please contact the ST sales office nearest to you.
Table 11.
Battery table
Part number
Description
Package
M4Z28-BR00SH1 SNAPHAT housing for 48mAh battery
SH
M4Z32-BR00SH1 SNAPHAT housing for 120mAh battery
SH
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Revision history
7
M40Z111, M40Z111W
Revision history
Table 12.
20/21
Document revision history
Date
Revision
Changes
Sep-2000
1
First Draft Issue
14-Sep-2001
2
Reformatted, TOC added, changed DC Characteristics (Table 6);
changed battery, ind. temperature information (Table 3, 2, 10, 11,
Figure 9, 10); Corrected SOIC label (Figure 2); added E2 to Hookup
(Figure 3)
13-May-2002
3
Modify reflow time and temperature footnote (Table 3)
12-Nov-2007
4
Reformatted document; added lead-free second level interconnect
information to cover page and Section 5: Package mechanical data;
updated Figure 5, Table 3, 10, 11.
M40Z111, M40Z111W
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