M41T01M6F

M41T01 Low-power serial real-time clock (RTC) with built-in battery switchover circuit Datasheet - production data Description The M41T01 is a low-power serial real-time clock (RTC). The built-in 32.768 kHz oscillator circuit works with an external crystal and does not need any load capacitors. 8 1 SO8 Features  2.0 to 5.5 V clock operating voltage  Counters for seconds, minutes, hours, day, date, month, years, and century  Software clock calibration  Automatic switchover and deselect circuitry  Ultra-low battery supply current of 800 nA  Low operating current of 300 μA  Battery and capacitor backup  Battery backup not recommended for 3.0 V applications (capacitor backup only) The M41T01 clock has a built-in power sense circuit which detects power failures and automatically switches to the battery supply during power failures. Eight bytes of the RAM are used for the clock/calendar function and are configured in binary-coded decimal (BCD) format. Addresses and data are transferred serially via a two-line bidirectional bus. The built-in address register is incremented automatically after each WRITE or READ data byte. The energy needed to sustain the RAM and clock operations can be supplied from a small lithium coin cell. Typical data retention time is in excess of 5 years with a 50 mA/h 3 V lithium cell. The M41T01 is supplied in an 8-lead plastic small outline package.  Operating temperature of –40 to 85 °C  Automatic leap year compensation October 2013 This is information on a product in full production. DocID025389 Rev 2 1/24 www.st.com Contents M41T01 Contents 1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 DocID025389 Rev 2 M41T01 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO8 – 8-lead plastic small outline package mechanical data. . . . . . . . . . . . . . . . . . . . . . . 21 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DocID025389 Rev 2 3/24 24 List of figures M41T01 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. 4/24 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Alternate READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AC testing input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO8 – 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DocID025389 Rev 2 M41T01 1 Device overview Device overview Figure 1. Logic diagram VCC VBAT OSCO OSCI M41T01 SCL SDA FT/OUT VSS AI07068b Table 1. Signal names OSCI Oscillator input OCSO Oscillator output FT/OUT Frequency test / output driver (open drain) SDA Serial data address input / output SCL Serial clock VBAT Battery supply voltage VCC Supply voltage VSS Ground Figure 2. SOIC connections M41T01 OSCI OSCO VBAT VSS 1 2 3 4 8 7 6 5 VCC FT/OUT SCL SDA AI07069b DocID025389 Rev 2 5/24 24 Device overview M41T01 Figure 3. Block diagram 1 Hz OSCI OSCILLATOR 32.768 kHz SECONDS DIVIDER OSCO MINUTES FT/OUT VCC VSS VBAT CENTURY/HOURS VOLTAGE SENSE and SWITCH CIRCUITRY CONTROL LOGIC DAY DATE MONTH SCL SDA SERIAL BUS INTERFACE YEAR ADDRESS REGISTER CONTROL AI07070b 6/24 DocID025389 Rev 2 M41T01 2 Operation Operation The M41T01 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order: 1. Seconds register 2. Minutes register 3. Century/hours register 4. Day register 5. Date register 6. Month register 7. Years register 8. Control register The M41T01 clock continually monitors VCC for an out of tolerance condition. Should VCC fall below VSO, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. Upon power-up, the device switches from battery to VCC at VSO and recognizes inputs. 2.1 2-wire bus characteristics This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:  Data transfer may be initiated only when the bus is not busy.  During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined:  Bus not busy Both data and clock lines remain high.  Start data transfer A change in the state of the data line, from high to low, while the clock is high, defines the START condition.  Stop data transfer A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition. DocID025389 Rev 2 7/24 24 Operation M41T01  Data valid The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal (see Figure 4). The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition, a device that gives out a message is called “transmitter”, the receiving device that gets the message is called “receiver”. The device that controls the message is called “master”. The devices that are controlled by the master are called “slaves”. Figure 4. Serial bus data transfer sequence DATA LINE STABLE DATA VALID CLOCK DATA START CONDITION CHANGE OF DATA ALLOWED STOP CONDITION AI00587 8/24 DocID025389 Rev 2 M41T01 Operation  Acknowledge Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse (see Figure 5). A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line high to enable the master to generate the STOP condition. Figure 5. Acknowledgement sequence CLOCK PULSE FOR ACKNOWLEDGEMENT START SCLK FROM MASTER DATA OUTPUT BY TRANSMITTER 1 2 MSB 8 9 LSB DATA OUTPUT BY RECEIVER AI00601 DocID025389 Rev 2 9/24 24 Operation 2.2 M41T01 READ mode In this mode, the master reads the M41T01 slave after setting the slave address (see Figure 6). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the word address An is written to the on-chip address pointer. Next the START condition and slave address are repeated, followed by the READ mode control bit (R/W = 1). At this point, the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. The address pointer is only incremented on reception of an acknowledge bit. The M41T01 slave transmitter will now place the data byte at address An+1 on the bus. The master receiver reads and acknowledges the new byte and the address pointer is incremented to An+2. This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. An alternate READ mode may also be implemented, whereby the master reads the M41T01 slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 7 on page 11). Figure 6. Slave address location R/W SLAVE ADDRESS 1 A LSB MSB START 1 0 1 0 0 0 AI00602 10/24 DocID025389 Rev 2 M41T01 Operation SLAVE ADDRESS DATA n+1 ACK DATA n ACK S ACK BUS ACTIVITY: R/W START WORD ADDRESS (An) ACK S R/W SDA LINE ACK BUS ACTIVITY: MASTER START Figure 7. READ mode sequence STOP SLAVE ADDRESS P AI00899 NO ACK DATA n+X STOP R/W SLAVE ADDRESS DATA n+X P NO ACK BUS ACTIVITY: DATA n+1 ACK DATA n ACK S ACK SDA LINE ACK BUS ACTIVITY: MASTER START Figure 8. Alternate READ mode sequence AI00895 DocID025389 Rev 2 11/24 24 Operation 2.3 M41T01 WRITE mode In this mode the master transmitter transmits to the M41T01 slave receiver. Bus protocol is shown in Figure 9. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address An will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the RAM on the reception of an acknowledge clock. The M41T01 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again after it has received the word address and each data byte (see Figure 6 on page 10). 2.4 Data retention mode With valid VCC applied, the M41T01 can be accessed as described above with READ or WRITE Cycles. Should the supply voltage decay, the M41T01 will automatically deselect, write protecting itself when VCC falls (see Figure 13 on page 20). STOP SLAVE ADDRESS 12/24 DATA n+X AI00591 DocID025389 Rev 2 P ACK DATA n+1 ACK BUS ACTIVITY: DATA n ACK WORD ADDRESS (An) ACK S R/W SDA LINE ACK BUS ACTIVITY: MASTER START Figure 9. WRITE mode sequence M41T01 3 Clock operation Clock operation The eight byte clock register (see Table 2 on page 14) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are contained within the first three registers. Bits D6 and D7 of clock register 2 (hours register) contain the century enable bit (CEB) and the century bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2 of register 3 contain the Day (day of week). Registers 4, 5 and 6 contain the Date (day of month), Month and Years. The final register is the Control register (this is described in Section 3.1: Clock calibration). Bit D7 of register 0 contains the stop bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second. Note: In order to guarantee oscillator startup after the initial power-up, set the ST bit to a '1,' then reset this bit to a '0.' This sequence enables a “kick start” circuit which aids the oscillator start-up during worst case conditions of voltage and temperature. The seven clock registers may be read one byte at a time, or in a sequential block. The control register (address location 7) may be accessed independently. A provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. If a clock address is being read, an update of the clock registers will be delayed by 250 ms to allow the READ to be completed before the update occurs. This will prevent a transition of data during the READ. Note: This 250 ms delay affects only the clock register update and does not alter the actual clock time. DocID025389 Rev 2 13/24 24 Clock operation M41T01 Table 2. Register map Data Function/range Addr D7 D5 D4 D3 D2 D1 D0 BCD format 0 ST 10 Seconds Seconds Seconds 00-59 1 X 10 Minutes Minutes Minutes 00-59 2 CEB(1) CB 3 X X 4 X X 5 X X 6 7 Note: D6 10 Hours X X Hours X Day 10 Date X 10 M. 10 Years OUT FT S Century/Hours 0-1/00-23 Day 01-07 Date Date 01-31 Month Month 01-12 Years Year 00-99 Calibration Control S = Sign bit FT = Frequency test bit ST = Stop bit OUT = Output level X = Don’t care CEB = Century enable bit CB = Century bit Note: 1 When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set). When CEB is set to '0', CB will not toggle. 14/24 DocID025389 Rev 2 M41T01 3.1 Clock operation Clock calibration The M41T01 is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25 °C, which equates to about ±1.53 minutes per month. With the calibration bits properly set, the accuracy of each M41T01 improves to better than ±2 ppm at 25°C. The oscillation rate of any crystal changes with temperature (see Figure 10 on page 16). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. The M41T01 design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 16. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration byte occupies the five lower order bits (D4-D0) in the control register (Addr 7). This byte can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or – 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41T01 may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accessed the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the frequency test (FT) bit, the seventh-most significant bit in the Control Register, is set to a '1', and the oscillator is running at 32,768 Hz, the FT/OUT pin of the device will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10(XX001010) to be loaded into the calibration byte for correction. Note that setting or changing the calibration byte does not affect the frequency test output frequency. DocID025389 Rev 2 15/24 24 Clock operation M41T01 Figure 10. Crystal accuracy across temperature Frequency (ppm) 20 0 –20 –40 –60 –80 ΔF = K x (T –T)2 O F –100 K = –0.036 ppm/ °C2 ± 0.006 ppm/°C2 –120 TO = 25°C ± 5°C –140 –160 –40 –30 –20 –10 0 10 20 30 40 50 60 Temperature°C 70 80 AI00999b Figure 11. Clock calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION 3.2 AI00594B Output driver pin When the FT bit is set, the FT/OUT pin provides a nominal 512 Hz frequency output used for calibration purposes (see Section 3.1). When the FT bit is set to zero, the FT/OUT pin becomes an output driver that reflects the contents of the OUT bit (D7 bit of register 7, see Table 2). If the OUT bit is zero, then the FT/OUT pin will be driven low, if the OUT bit is one, then the FT/OUT pin will be driven high. The OUT bit can be written through the 2-wire bus port. Note: The FT/OUT pin is open drain which requires an external pull-up resistor. 3.3 Initial power-on defaults Upon initial application of power to the device, the FT bit will be set to a '0' and the OUT bit will be set to a '1'. All other register bits will initially power on in a random state. 16/24 DocID025389 Rev 2 M41T01 4 Maximum rating Maximum rating Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. . Table 3. Absolute maximum ratings Symbol TA TSTG(1)(2) Parameter Value Units Ambient operating temperature –40 to 85 °C Storage temperature (VCC off, oscillator off) –55 to 125 °C VIO Input or output voltages –0.3 to 7 V VCC Supply voltage –0.3 to 7 V IO Output current 20 mA PD Power dissipation 0.25 W 1. For SO package, standard (SnPb) lead finish: reflow at peak temperature of 225°C (the time above 220 °C must not exceed 20 seconds) 2. For SO package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260°C (the time above 255 °C must not exceed 30 seconds) Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode. DocID025389 Rev 2 17/24 24 DC and AC parameters 5 M41T01 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 4. Operating and AC measurement conditions Parameter Note: M41T01 Unit Supply voltage (VCC) 2.0 to 5.5 V Ambient operating temperature (TA) –40 to 85 °C Load capacitance (CL) 100 pF Input rise and fall times 5 ns Input pulse voltages 0.2VCC to 0.8VCC V Input and output timing ref. voltages 0.3VCC to 0.7VCC V Output Hi-Z is defined as the point where data is no longer driven. Figure 12. AC testing input/output waveform 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI02568 Table 5. Capacitance Parameter(1,2) Symbol CIN COUT(3) tLP Max Unit Input capacitance (SCL) 7 pF Output capacitance (SDA, FT/OUT) 10 pF 1000 ns Low-pass filter input time constant (SDA and SCL) Min 250 1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested. 2. At 25 °C, f = 1 MHz. 3. Outputs deselected. 18/24 DocID025389 Rev 2 M41T01 DC and AC parameters Table 6. DC characteristics Symbol Test condition(1) Parameter Min Typ Max Unit 0 V  VIN  VCC ±1 μA 0 V  VOUT  VCC ±1 μA Switch frequency = 100 kHz 300 μA SCL, SDA = VCC – 0.3 V 70 μA ILI Input leakage current ILO Output leakage current ICC1 Supply current ICC2 Supply current (standby) VIL Input low voltage –0.3 0.3 VCC V VIH Input high voltage 0.7 VCC VCC + 0.5 V VOL Output low voltage IOL = 3 mA 0.4 V FT/OUT 5.5 V 3 3.5(4) V 0.8 1 μA Pull-up supply voltage (open drain) VBAT(2) Battery supply voltage IBAT Battery supply current 2.5(3) TA = 25 °C, VCC = 0 V, Oscillator ON, VBAT = 3 V 1. Valid for Ambient Operating Temperature: TA = –40 to 85 °C; VCC = 2.0 to 5.5 V (except where noted). 2. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply. 3. After switchover (VSO), VBAT(min) can be 2.0 V for crystal with RS = 40 k. 4. For rechargeable back-up, VBAT(max) may be considered VCC. Table 7. Crystal electrical characteristics Symbol Parameter (1)(2) fO Resonant frequency RS Series resistance CL Load capacitance Min Typ Max 32.768 Unit kHz 60 12.5 k pF 1. These values are externally supplied. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. 2. Load capacitors are integrated within the M41T01. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. DocID025389 Rev 2 19/24 24 DC and AC parameters M41T01 Figure 13. Power down/up mode AC waveforms VCC VSO tPD trec SDA SCL DON'T CARE AI00596 Table 8. Power down/up AC characteristics Parameter(1) Symbol tPD trec (2) Min Max Unit SCL and SDA at VIH before power-down 0 ns SCL and SDA at VIH after power-up 10 μs 1. Valid for Ambient Operating Temperature: TA = –40 to 85 °C; VCC = 2.0 to 5.5 V (except where noted). 2. VCC fall time should not exceed 5 mV/μs. Table 9. Power down/up trip points DC characteristics Symbol Parameter(1,2) Symbol Parameter(1,2) VSO(4) Battery backup switchover voltage Min Typ Max(3) Unit Min Typ Max(3) Unit VBAT – 0.80 VBAT – 0.50 VBAT – 0.30 V 1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.0 to 5.5 V (except where noted). 2. All voltages referenced to VSS. 3. In 3.3 V application, if initial battery voltage is  3.4 V, it may be necessary to reduce battery voltage (i.e., through wave soldering the battery) in order to avoid inadvertent switchover/deselection for VCC – 10% operation. 4. Switchover and deselect point. 20/24 DocID025389 Rev 2 M41T01 6 Package mechanical information Package mechanical information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 14. SO8 – 8-lead plastic small package outline h x 45˚ A C B CP e D N E H 1 A1 α L SO-a Note: Drawing is not to scale. Table 10. SO8 – 8-lead plastic small outline package mechanical data mm inches Sym typ min max typ min max A – 1.35 1.75 – 0.053 0.069 A1 – 0.10 0.25 – 0.004 0.010 B – 0.33 0.51 – 0.013 0.020 C – 0.19 0.25 – 0.007 0.010 D – 4.80 5.00 – 0.189 0.197 E – 3.80 4.00 – 0.150 0.157 e 1.27 – – 0.050 – – H – 5.80 6.20 – 0.228 0.244 h – 0.25 0.50 – 0.010 0.020 L – 0.40 0.90 – 0.016 0.035  – 0° 8° – 0° 8° N CP 8 – – 8 0.10 DocID025389 Rev 2 – – 0.004 21/24 24 Part numbering 7 M41T01 Part numbering Table 11. Ordering information scheme Example: M41T 01 M 6 F Device type M41T Supply voltage and write protect voltage 01 = VCC = 2.0 to 5.5 V Package M = SO8 (150 mils width) Temperature range 6 = –40 to 85°C Shipping method F = ECOPACK® package, tape & reel For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. 22/24 DocID025389 Rev 2 M41T01 8 Revision history Revision history Table 12. Document revision history Date Revision 01-May-2006 1 Initial release 2 Updated title, Features, Description Updated footnotes 1 and 2 of Table 3: Absolute maximum ratings Updated Section 3.2: Output driver pin Updated footnote 1 of Table 7: Crystal electrical characteristics Added ECOPACK® paragraph to Section 6: Package mechanical information Updated Table 11: Ordering information scheme 21-Oct-2013 Changes DocID025389 Rev 2 23/24 24 M41T01 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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