M41T60
Low-power serial real-time clock (RTC)
Datasheet - production data
Features
• Counters for seconds, minutes, hours, day,
date, month, years, and century
• 32 KHz crystal oscillator integrating load
capacitance and high crystal series resistance
operation
QFN16
3 mm x 3 mm
• Oscillator stop detection monitors clock
operation
• Serial interface supports I2C bus (400 kHz)
VSOJ20 (47.6mm2)
• 350 nA timekeeping current at 3 V
2
GND Plane Guard Ring (21.5mm )
SMT
CRYSTAL
1
XI
2
XO
• Low operating current of 35 µA (at 400 kHz)
• Timekeeping down to 1.0 V
• 1.3 V to 4.4 V I2C bus operating voltage
3
4
• Software clock calibration to compensate
deviation of crystal due to temperature
ST QFN16
• Software programmable output (OUT)
• Operating temperature of –40 to 85 °C
Footprint comparison of ST’s QFN16 with
SMT crystal vs. competing VSOJ20 package
• Automatic leap year compensation
• Lead-free 16-pin QFN package
• Li-ion rechargeable operation
February 2013
This is information on a product in full production.
DocID10396 Rev 14
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www.st.com
28
Table of contents
M41T60
Table of contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
3
2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.3
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.4
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.5
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
Leap year . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5
Oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6
Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28
DocID10396 Rev 14
M41T60
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Examples using century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Crystals suitable for use with M41T6x series RTCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, mechanical data . . . 24
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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List of figures
M41T60
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
4/28
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
16-pin QFN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hardware hookup for SuperCap™ backup operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Alternate READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Century bits CB1 and CB0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC testing I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline . . . . . . . . . . . 24
QFN16, quad, flat package, no lead, 3 x 3 mm, recommended footprint . . . . . . . . . . . . . . 25
32 KHz crystal + QFN16 vs. VSOJ20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DocID10396 Rev 14
M41T60
1
Description
Description
The M41T60 is a low-power serial real-time clock (RTC) with a built-in 32.768 kHz oscillator
(external crystal controlled). Eight registers are used for the clock/calendar function and are
configured in binary-coded decimal (BCD) format. Addresses and data are transferred
serially via a two-line, bidirectional bus. The built-in address register is increased
automatically after each WRITE or READ data byte.
The eight clock address locations contain the century, year, month, date, day, hour, minute,
and second in 24-hour BCD format. Corrections for 28-, 29- (leap year), 30-, and 31-day
months are made automatically.
The M41T60 is supplied in a 16-lead QFN package.
Figure 1. Logic diagram
VCC
XI
FT(1)
XO
SCL
M41T60
OFIRQ/OUT(1)
SDA
VSS
AI08869
1. Open drain
Table 1. Signal names
XI
Oscillator input
XO
Oscillator output
FT
Frequency test output (open drain)
SDA
Serial data address input/output
SCL
Serial clock
OFIRQ/OUT
Oscillator fail interrupt/out output (open drain)
VCC
Supply voltage
VSS
Ground
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Description
M41T60
NC
NC
VCC
NC
Figure 2. 16-pin QFN connections
16
15
14
13
XO
2
11
OFIRQ/OUT(1)
VSS
3
10
SCL
(1)
4
9
SDA
FT
5
6
7
8
NC
NC
NC
12
NC
1
VSS
XI
AI08870
Figure 3. Block diagram
(1)
FT
FT
OUT
OFIE
1 Hz
(1)
OFIRQ/OUT
OSCILLATOR
FAIL DETECT
XI
OSCILLATOR
32.768 kHz
DIVIDER
SECONDS
XO
MINUTES
HOURS
CONTROL
LOGIC
VCC
VSS
DAY
DATE
SCL
CENTURY/
MONTH
SERIAL
BUS
INTERFACE
SDA
YEAR
ADDRESS
REGISTER
CALIBRATION
AI08871
1. Open drain output.
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DocID10396 Rev 14
M41T60
Description
Figure 4. Hardware hookup for SuperCap™ backup operation
VCC
MCU
M41T60
VCC
XI
XO
VSS
VCC
(1)
OFIRQ/OUT
(1)
FT
Port
Port
SCL
Serial Clock Line
SDA
Serial Data Line
AI10476b
1. Open drain output.
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Operation
2
M41T60
Operation
The M41T60 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 8 bytes
contained in the device can then be accessed sequentially in the following order:
2.1
1.
Seconds register
2.
Minutes register
3.
Hours register
4.
Day register
5.
Date register
6.
Century/month register
7.
Years register
8.
Calibration register
2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
•
Data transfer may be initiated only when the bus is not busy.
•
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line while the clock line is high will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain high.
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
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M41T60
2.1.4
Operation
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition. The
number of data bytes transferred between the start and stop conditions is not limited. The
information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is called “transmitter”, the receiving device
that gets the message is called “receiver”. The device that controls the message is called
“master”. The devices that are controlled by the master are called “slaves”.
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver, whereas the master generates an extra acknowledge
related clock pulse.
A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case, the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Figure 5. Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
DocID10396 Rev 14
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Operation
M41T60
Figure 6. Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
1
DATA OUTPUT
BY TRANSMITTER
2
8
MSB
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
2.2
READ mode
In this mode, the master reads the M41T60 slave after setting the slave address
(see Figure 7). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit,
the word address An is written to the on-chip address pointer. Next the START condition and
slave address are repeated, followed by the READ mode control bit (R/W = 1). At this point,
the master transmitter becomes the master receiver. The data byte which was addressed
will be transmitted and the master receiver will send an acknowledge bit to the slave
transmitter. The address pointer is only increased on reception of an acknowledge bit. The
M41T60 slave transmitter will now place the data byte at address An+1 on the bus. The
master receiver reads and acknowledges the new byte and the address pointer is increased
to An+2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (0h to 6h). The update will resume due to a stop condition or when the
pointer increments to any non-clock address (7h).
An alternate READ mode may also be implemented, whereby the master reads the M41T60
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 9 on page 11).
Figure 7. Slave address location
R/W
START
A
1
LSB
MSB
SLAVE ADDRESS
1
0
1
0
0
0
AI00602
10/28
DocID10396 Rev 14
M41T60
Operation
DATA n+1
ACK
DATA n
ACK
S
ACK
BUS ACTIVITY:
R/W
START
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 8. READ mode sequence
SLAVE
ADDRESS
STOP
SLAVE
ADDRESS
P
NO ACK
DATA n+X
AI00899
STOP
SLAVE
ADDRESS
DATA n+X
ACK
BUS ACTIVITY:
DATA n+1
ACK
DATA n
P
NO ACK
R/W
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 9. Alternate READ mode sequence
AI00895
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Operation
2.3
M41T60
WRITE mode
In this mode the master transmitter transmits to the M41T60 slave receiver. Bus protocol is
shown in Figure 10 on page 12. Following the START condition and slave address, a logic
'0' (R/W = 0) is placed on the bus and indicates to the addressed device that word address
An will follow and is to be written to the on-chip address pointer. The data word to be written
to the memory is strobed in next and the internal address pointer is increased to the next
address location on the reception of an acknowledge clock. The M41T60 slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
and again after it has received the word address and each data byte.
STOP
SLAVE
ADDRESS
12/28
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 10. WRITE mode sequence
AI00591
DocID10396 Rev 14
M41T60
3
Clock operation
Clock operation
The M41T60 is driven by a quartz-controlled oscillator with a nominal frequency of
32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz
crystal that is used as the time-base for the RTC. The eight-byte clock register (see Table 2
on page 15) is used to both set the clock and to read the date and time from the clock, in a
binary-coded decimal format. Seconds, minutes, and hours are contained within the first
three registers.
Bits D6 and D7 of clock register 05h (century/month register) contain the century bit 0 (CB0)
and the century bit 1 (CB1). See Table 3 on page 16 for additional explanation. Bits D0
through D2 of register 03h contain the day (day of the week). Registers 04h, 05h, and 06h
contain the date (day of the month), century/month, and years. The eighth clock register is
the calibration register (this is described in the clock calibration section). Bit D7 of register
00h contains the stop bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When
reset to a '0,' the oscillator restarts within one second (typical).
Note:
Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST
bit to '0.' This provides an additional “kick-start” to the oscillator circuit.
Bit D7 of register 01h contains the oscillator fail interrupt enable bit (OFIE - see the
description in the oscillator fail detection section).
Note:
A WRITE to ANY location within the first seven bytes of the clock register (0h-6h), including
the OFIE and ST bit, will result in an update of the system clock and a reset of the divider
chain. This could result in an inadvertent change of the current time. These non-clock
related bits should be written prior to setting the clock, and remain unchanged until such
time as a new clock time is also written.
The seven clock registers may be read one byte at a time, or in a sequential block. The
calibration register (address location 7h) may be accessed independently. A provision has
been made to ensure that a clock update does not occur while any of the clock addresses
are being read. If a clock address is being read, an update of the clock registers will be
halted. this will prevent a transition of data during the READ.
3.1
Calibrating the clock
The M41T60 is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. The accuracy of the clock is dependent upon the accuracy of the crystal, and the
match between the capacitive load of the oscillator circuit and the capacitive load for which
the crystal was trimmed. The M41T60 oscillator is designed for use with a 6 - 7 pF crystal
load capacitance. When the calibration circuit is properly employed, accuracy improves to
better than ±2 ppm at 25 °C.
The oscillation rate of crystals changes with temperature (see Figure 11 on page 15). The
M41T60 design employs periodic counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in
Figure 12 on page 16. The number of times pulses are blanked (subtracted, negative
calibration) or split (added, positive calibration) depends upon the value loaded into the five
calibration bits found in the calibration register. Adding counts speeds the clock up,
subtracting counts slows the clock down. The calibration bits occupy the five lower-order
bits (D4-D0) in the calibration register 07h.
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Clock operation
M41T60
These bits can be set to represent any value between 0 and 31 in binary format. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration.
Calibration occurs within a 64-minute cycle. The first 62 minutes in the cycle may, once per
minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If
a binary '1' is loaded into the register, only the first 2 minutes in the 64-minute cycle will be
modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each
calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every
125,829,120 actual oscillator cycles. That is, +4.068 or –2.034 ppm of adjustment per
calibration step in the calibration register. Assuming that the oscillator is running at exactly
32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35
seconds per day which corresponds to a total range of +5.5 or –2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M41T60 may
require:
Note:
14/28
•
The first involves setting the clock, letting it run for a month and comparing it to a
known accurate reference and recording deviation over a fixed period of time.
Calibration values, including the number of seconds lost or gained in a given period,
can be found in application note AN934, “TIMEKEEPER® calibration.” This allows the
designer to give the end user the ability to calibrate the clock as the environment
requires, even if the final product is packaged in a non-user serviceable enclosure. The
designer could provide a simple utility that accesses the calibration byte.
•
The second approach is better suited to a manufacturing environment, and involves the
use of the frequency test (FT) pin. The FT pin will toggle at 512 Hz when the ST bit is
set to '0,' and the OUT bit and FT bit are set to '1.' Any measured deviation from the
512 Hz frequency indicates the degree and direction of oscillator frequency shift at the
test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration
byte for correction.
Setting or changing the calibration byte does not affect the frequency test output frequency.
the FT pin is an open drain pin which requires a pull-up resistor to VCC for proper operation.
A 500-10 k resistor is recommended in order to control the rise time.
DocID10396 Rev 14
M41T60
Clock operation
Table 2. Register map
Data
Function/range
BCD format
Address
D7
D6
D5
D4
D3
D2
D1
D0
0
ST
10 seconds
Seconds
Seconds
00-59
1
OFIE
10 minutes
Minutes
Minutes
00-59
2
0
0
Hours
Hours
00-23
3
0
0
Day
01-07
4
0
0
Date
01-31
5
CB1
CB0
6
10 hours
0
0
0
Day
10 date
0
Date
10 M.
Month
10 Years
7
OUT
FT
Century/month 0-3/01-12
Years
S
Year
Calibration
•
0 = Must be set to '0'
•
CB0, CB1 = century bits
•
FT = frequency test bits
•
OFIE = oscillator fail interrupt enable bit
•
OUT = output level
•
S = sign bit
•
ST = stop bit
00-99
Calibration
Figure 11. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
ΔF = K x (T – T )2
O
F
–80
2
2
K = –0.036 ppm/°C ± 0.006 ppm/°C
–100
TO = 25°C ± 5°C
–120
–140
–160
–40
–30
–20
–10
0
10
20
30
Temperature °C
DocID10396 Rev 14
40
50
60
70
80
AI07888
15/28
Clock operation
M41T60
Figure 12. Calibration waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594b
3.2
Century bits
The two century bits, CB1 and CB0, are bits D7 and D6, respectively, in the century/month
register at address 06h. Together, they comprise a 2-bit counter which increments at the
turn of each century. CB1 is the most significant bit.
The user may arbitrarily assign the meaning of CB1:CB0 to represent any century value, but
the simplest way of using these bits is to extend the year register (07h) by mapping them
directly to bits 9 and 8. (The reader is reminded that the year register is in BCD format.)
Higher order year bits can be maintained in the application software.
Figure 13. Century bits CB1 and CB0
Example: 16-bit year value
CB1:CB0
00
01
MAINTAIN
ADDITIONAL
YEAR BITS IN
SOFTWARE
LOWER 8 BITS
CONTAINED IN
YEAR REGISTER
(07h)
11
CB1
CB0
b15
b14
b13
b12
b11
b10
b9
b8
D7
D6
D5
D4
D3
D2
D1
D0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10
LET CB1:CB0 REPRESENT
BITS 9 AND 8 TO EXTEND
THE YEAR REGISTER
Table 3. Examples using century bits
16/28
CB1
CB0
CENTURY
0
0
2000
0
1
2100
1
0
2200
1
1
2300
DocID10396 Rev 14
M41T60
3.3
Clock operation
Leap year
Leap year occurs every four years, in years which are multiples of 4. For example, 2012
was a leap year. An exception to that is any year which is a multiple of 100. For example,
the year 2100 is not a leap year. A further exception is that years which are multiples of 400
are indeed leap years. Hence, while 2100 is not a leap year, 2400 is.
During any year which is a multiple of 4, the M41T6x RTC will automatically insert leap day,
February 29. Therefore, the application software must correct for this during the exception
years (2100, 2200, etc.) as noted above.
3.4
Output driver pin
When the OFIE bit is not set to generate an interrupt, the OFIRQ/OUT pin becomes an
output driver that reflects the contents of D7 of the calibration register. In other words, when
D7 (OUT bit) is a '0,' then the OFIRQ/OUT pin will be driven low.
Note:
The OFIRQ/OUT pin is an open drain which requires an external pull-up resistor.
3.5
Oscillator stop detection
In the event that the oscillator has either stopped, or was stopped for some period of time,
and if the oscillator fail interrupt enable (OFIE) bit is set to a '1,' an interrupt will be
generated. This interrupt can be used to judge the validity of the clock and date data.
The interrupt will be active any time the oscillator stops while VCC is ≥ 1.0V. The following
conditions will cause the OFIRQ pin to be active:
•
the ST bit is set to '1.'
•
external interference or removal of the crystal.
The oscillator fail interrupt (OFIRQ) will remain active until the OFIE bit is reset to '0,' or the
oscillator restarts.
The oscillator must start and have run for at least 4 seconds before attempting to set the
OFIE bit to '1.'
3.6
Initial power-on defaults
Upon initial application of power to the device, the OUT bit will be set to a '1,' while the ST,
OFIE, and FT bits will be set to '0.' All other register bits will initially power-on in a random
state.
DocID10396 Rev 14
17/28
Maximum ratings
4
M41T60
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 4. Absolute maximum ratings
Symbol
Parameter
Conditions(1)
Value(2)
Unit
TSTG
Storage temperature (VCC off, oscillator off)
–55 to 125
°C
VCC
Supply voltage
–0.3 to 5.0
V
260
°C
–0.2 to
Vcc+0.3
V
TSLD(3)
Lead solder temperature for 10 seconds
VIO
Input or output voltages
IO
Output current
20
mA
PD
Power dissipation
1
W
VESD(HBM)
VESD(RCDM)
Electro-static discharge voltage
(Human Body Model)
TA = 25°C
>1500
V
Electro-static discharge voltage
(Robotic Charged Device Model)
TA = 25°C
>1000
V
1. Test conforms to JEDEC standard
2. Data based on characterization results, not tested in production
3. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
18/28
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M41T60
5
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 5. Operating and AC measurement conditions
Parameter
Note:
M41T60
Supply voltage (VCC)
1.3 V to 4.4 V
Ambient operating temperature (TA)
–40 to 85 °C
Load capacitance (CL)
50 pF
Input rise and fall times
≤ 5 ns
Input pulse voltages
0.2 VCC to 0.8 VCC
Input and output timing ref. voltages
0.3 VCC to 0.7 VCC
Output Hi-Z is defined as the point where data is no longer driven.
Figure 14. AC testing I/O waveform
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Figure 15. Crystal isolation example
Local Grounding Plane
(Layer 2)
XI
Crystal
XO
GND
AI09127
Note:
Substrate pad should be tied to VSS.
DocID10396 Rev 14
19/28
DC and AC parameters
M41T60
Table 6. Capacitance
Parameter (1)(2)
Symbol
CIN
COUT(3)
tLP
Min
Max
Unit
Input capacitance (SCL)
-
7
pF
Output capacitance (SDA, OUT)
-
10
pF
Low-pass filter input time constant (SDA and SCL)
-
50
ns
1. Effective capacitance measured with power supply at 3.6 V; sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz.
3. Outputs deselected.
Table 7. DC characteristics
Symbol
VCC(2)
Parameter
Operating voltage
Test condition(1)
Min
Clock (3)
I
2C
bus (400 kHz)
Typ
Max
Unit
1.0
4.4
V
1.3
4.4
V
100
µA
70
µA
VCC = 4.4 V
ICC1
ICC2
Supply current
Supply current
(Standby)
SCL = 400 kHz
(No load)
SCL = 0 Hz
All inputs
≥ VCC – 0.2 V
≤ VSS + 0.2 V
VCC = 3.6 V
50
VCC = 3.0 V
35
µA
VCC = 2.5 V
30
µA
VCC = 2.0 V
20
µA
4.4 V
950
nA
700
nA
3.6 V
375
3.0 V at 25 °C
350
nA
2.0 V at 25 °C
310
nA
VIL
Input low voltage
–0.2
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC + 0.3
V
VOL
Output low voltage
VCC = 4.4 V, IOL = 3 mA (SDA)
0.4
V
VCC = 4.4 V, IOL = 1 mA (OFIRQ/OUT)
0.4
V
Pull-up supply
voltage (open drain)
FT, OFIRQ/OUT
4.4
V
ILI
Input leakage current
0 V ≤ VIN ≤ VCC
–1.0
+1.0
µA
ILO
Output leakage
current
0 V ≤ VOUT ≤ VCC
–1.0
+1.0
µA
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 1.3 to 4.4 V (except where noted).
2. When using battery backup, VCC fall time should not exceed 10 mV/µs.
3. Oscillator startup guaranteed at 1.5 V only.
20/28
DocID10396 Rev 14
M41T60
DC and AC parameters
Table 8. Crystal electrical characteristics
Parameter (1)(2)
Symbol
Min
Typ
32.768
fO
Resonant frequency
-
RS
Series resistance
(TA = –40 to 70°C, oscillator startup at 2.0 V)
-
CL
Load capacitance
-
Max
Unit
kHz
75 (3)(4)
kΩ
6
pF
1. For the QFN16 package, user-supplied, external crystals are required. The 6 and 7 pF crystals listed in
Table 9 below have been evaluated by ST and have been found to be satisfactory for use with the M41T6x
series RTCs.
2. Load capacitors are integrated within the M41T60. Circuit board layout considerations for the 32.768 kHz
crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
3. Guaranteed by design.
4. RS (max) = 65 kΩ for TA = –40 to 85 °C and oscillator startup at 1.5 V.
Table 9. Crystals suitable for use with M41T6x series RTCs
Manufacturer’s specifications
Vendor
ESR
max
Temp.
range
(°C)
50 kΩ
–40/+85
±20 ppm
6 pF
3.2 x 1.5 x 0.9 mm SMT 70 kΩ
–40/+85
±20 ppm
7 pF
Order number
Citizen
CMJ206T-32.768KDZB-UB
Citizen
CM315-32.768KDZY-UB
Package
8.3 x 2.5 mm
leaded SMT
Rated
Rated
tolerance load
at 25 °C
cap.
Ecliptek
E4WCDA06-32.768K
(1)
2.0 x 6.0 mm thru-hole
50 kΩ
–10/+60
±20 ppm
6 pF
Ecliptek
E5WSDC 07 - 32.768K
7 x 1.5 x 1.4 mm SMT
65 kΩ
–40/+85
±20 ppm
7 pF
ECS
ECS-.327-6-17X-TR
3.8 x 8.5 x 2.5 mm SMT 50 kΩ
–10/+60
±20 ppm
6 pF
ECS
ECS-.327-7-34B-TR
3.2 x 1.5 x 0.9 mm SMT 70 kΩ
–40/+85
±20 ppm
7 pF
ECS
ECS-.327-7-38-TR
7 x 1.5 x 1.4 mm SMT
65 kΩ
–40/+85
±20 ppm
7 pF
Epson
MC-146 32.7680KA-AG: ROHS(2)
7 x 1.5 x 1.4 mm SMT
65 kΩ
–40/+85
±20 ppm
7 pF
Fox
298LF-0.032768-19
1.5 x 5.0 mm thru-hole
50 kΩ
–20/+60
±20 ppm
6 pF
Fox
299LF-0.032768-37
2.0 x 6.0 mm thru-hole
50 kΩ
–20/+60
±20 ppm
6 pF
Fox
414LF-0.032768-12
3.8 x 8.5 x 2.5 mm SMT 50 kΩ
–40/+85
±20 ppm
6 pF
Fox
501LF-0.032768-5
Micro
Crystal
MS3V-T1R 32.768KHZ 7PF 20PPM
Pletronics SM20S - 32.768K - 6pF
7 x 1.5 x 1.4 mm SMT
65 kΩ
–40/+85
±20 ppm
7 pF
6.7 x 1.4 mm
leaded SMT
65 kΩ
–40/+85
±20 ppm
7 pF
3.8 x 8.5 x 2.5 mm SMT 50 kΩ
–40/+85
±20 ppm
6 pF
Seiko
SSPT7F-7PF20PPM
7 x 1.5 x 1.4 mm SMT
65 kΩ
–40/+85
±20 ppm
7 pF
Seiko
VT200F-6PF20PPM
2.0 x 6.0 mm thru-hole
50 kΩ
–10/+60
±20 ppm
6 pF
1. ST has been informed that this crystal has been terminated by the vendor.
2. Epson MC-146 32.7680KA-E: ROHS is 6 pF version.
DocID10396 Rev 14
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DC and AC parameters
M41T60
Table 10. Oscillator characteristics
Symbol
Parameter
VSTA
Oscillator start voltage
tSTA
Oscillator start time
Cg
XIN capacitance
Cd
XOUT capacitance
Conditions
Min
≤ 10 seconds
1.5
Typ
Max
V
VCC = 3.0 V
IC-to-IC frequency variation
(1)
Unit
1
s
12
pF
12
pF
–10
+10
ppm
1. Reference value. TA = 25 °C, VCC = 3.0 V, CMJ-145 (CL = 6 pF, 32,768 Hz) manufactured by
Citizen, CL = Cg • Cd / (Cg + Cd)
Figure 16. Bus timing requirements sequence
SDA
tBUF
tHD:STA
tHD:STA
tF
tR
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
SR
tSU:STA
P
tSU:STO
AI00589
Note:
P = STOP and S = START
Table 11. AC characteristics
Parameter(1)
Symbol
Min
Max
Unit
0
400
kHz
fSCL
SCL clock frequency
tLOW
Clock low period
1.3
µs
tHIGH
Clock high period
600
ns
tR
SDA and SCL rise time
300
ns
tF
SDA and SCL fall time
300
ns
tHD:STA
START condition hold time
(after this period the first clock pulse is generated)
600
ns
tSU:STA
START condition setup time
(only relevant for a repeated start condition)
600
ns
tSU:DAT
Data setup time
100
ns
Data hold time
0
µs
STOP condition setup time
600
ns
Time the bus must be free before a new transmission can
start
1.3
µs
tHD:DAT
(2)
tSU:STO
tBUF
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 1.3 to 4.4 V (except where
noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max.) of
the falling edge of SCL.
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DocID10396 Rev 14
M41T60
6
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID10396 Rev 14
23/28
Package mechanical data
M41T60
Figure 17. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline
D
E
A3
A
A1
ddd C
e
b
L
K
1
2
Ch
E2
3
K
D2
Note:
QFN16-A
Drawing is not to scale.
Table 12. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size,
mechanical data
mm
inches
Dim
Typ
Min
Max
Typ
Min
Max
A
0.90
0.80
1.00
0.035
0.032
0.039
A1
0.02
0.00
0.05
0.001
0.000
0.002
A3
0.20
–
–
0.008
–
–
b
0.25
0.18
0.30
0.010
0.007
0.012
D
3.00
2.90
3.10
0.118
0.114
0.122
D2
1.70
1.55
1.80
0.067
0.061
0.071
E
3.00
2.90
3.10
0.118
0.114
0.122
E2
1.70
1.55
1.80
0.067
0.061
0.071
e
0.50
–
–
0.020
–
–
K
0.20
–
–
0.008
–
–
L
0.40
0.30
0.50
0.016
0.012
0.020
ddd
–
0.08
–
–
0.003
–
Ch
–
0.33
–
–
0.013
–
N
24/28
16
DocID10396 Rev 14
16
M41T60
Package mechanical data
Figure 18. QFN16, quad, flat package, no lead, 3 x 3 mm, recommended footprint
1.60
3.55
2.0
0.28
Note:
AI09126
Substrate pad should be tied to VSS.
Figure 19. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data
7.0 ± 0.3
VSOJ20
6.0 ± 0.2
3.2
SMT
CRYSTAL
1
XI
2
XO
2.9
3
4
1.5
ST QFN16
2.9
AI11146
Note:
Dimensions shown are in millimeters (mm).
DocID10396 Rev 14
25/28
Part numbering
7
M41T60
Part numbering
Table 13. Ordering information scheme
Example:
M41T
60
Q
6
F
Device family
M41T
Device type and supply voltage
60 = VCC = 1.3 to 4.4 V
Package
Q = QFN16 (3 mm x 3 mm)
Temperature range
6 = –40 to 85 °C
Shipping method
F = ECOPACK® package, tape & reel
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
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DocID10396 Rev 14
M41T60
8
Revision history
Revision history
Table 14. Revision history
Date
Revision
13-Nov-2003
1
20-Nov-2003
1.1
25-Dec-2003
2
13-Jan-2004
2.1
Update characteristics (Figure 9, 10, 12; Table 7, 13)
26-Feb-2004
2.2
Update characteristics and mechanical dimensions (Figure 15, 18;
Table 4 , 7, 12)
02-Mar-2004
2.3
Update characteristics (Table 7)
26-Apr-2004
3
Reformat and republish
13-May-2004
4
Update characteristics (Table 7, 8; Figure 15 , 18)
06-Aug-2004
5
Update characteristics (Figure 2; Table 7, 10)
25-Oct-2004
6
Document status promotion; update characteristics (Figure 1;
Table 4 ,7, 8, 10, 12)
20-Dec-2004
7
Corrected footprint; update characteristics (Figure 4, 18; Table 7)
05-May-2005
8
Add package comparison and mechanical data (Figure 19)
31-Oct-2005
9
Update: bus operating voltage, characteristics (Figure 4;
Table 4, 7, 11, 13)
30-Nov-2005
10
Update ESD:HBM rating, crystal characteristics (Table 4, 8)
06-Jul-2006
11
New template
26-Jan-2010
12
Minor textual changes; updated footnote 3 of Table 4; updated footnote
1 of Table 8; added Table 9; updated Table 10, 11, Section 3.1; added
text to Section 6: Package mechanical data.
29-Apr-2010
13
Updated Table 9; minor textual change in Section 4.
14
Updated title of datasheet; updated Section 3.2: Century bits; added
Figure 13: Century bits CB1 and CB0; moved and modified Table 3:
Examples using century bits; added Section 3.3: Leap year; added
footnote 1 to Table 9: Crystals suitable for use with M41T6x series RTCs.
21-Feb-2013
Changes
First issue
Update characteristics (Figure 2, 3, 4; Table 1, 2, 5, 7, 11)
Reformatted; add crystal isolation, footprint (Figure 12)
DocID10396 Rev 14
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M41T60
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