M48T512V-85PM1

M48T512Y M48T512V 5.0 or 3.3 V, 4 Mbit (512 Kbit x 8) TIMEKEEPER® SRAM Not recommended for new design Features ■ Integrated ultra low power SRAM, real-time clock, power-fail control circuit, battery, and crystal ■ BCD coded year, month, day, date, hours, minutes, and seconds ■ Automatic power-fail chip deselect and WRITE protection ■ WRITE protect voltages: (VPFD = power-fail deselect voltage) – M48T512Y: VCC = 4.5 to 5.5 V; 4.2 V ≤ VPFD ≤ 4.5 V – M48T512V: VCC = 3.0 to 3.6 V; 2.7 V ≤ VPFD ≤ 3.0 V ) s ( ct u d o t e l o r P e 32 ■ Conventional SRAM operation; unlimited WRITE cycles ■ Software controlled clock calibration for high accuracy applications ■ 10 years of data retention and clock operation in the absence of power ■ Pin and function compatible with industry standard 512 K x 8 SRAMS ■ Self-contained battery and crystal in DIP package ■ RoHS compliant – Lead-free second level interconnect ) (s s b O t c u 1 PMDIP32 module d o r P e t e l o s b O June 2011 Doc ID 5747 Rev 7 This is information on a product still in production but not recommended for new designs. 1/23 www.st.com 1 Contents M48T512Y, M48T512V Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ) s ( ct Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 u d o 3.1 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Stopping and starting the oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 14 r P e t e l o s b O 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ) (s t c u d o r t e l o 8 s b O 9 2/23 P e Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Doc ID 5747 Rev 7 M48T512Y, M48T512V List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PMDIP32 – 32-pin plastic module DIP, package mechanical data. . . . . . . . . . . . . . . . . . . 20 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 5747 Rev 7 3/23 List of figures M48T512Y, M48T512V List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 32-pin DIP connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE AC waveforms, WRITE enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE AC waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PMDIP32 – 32-pin plastic module DIP, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 4/23 Doc ID 5747 Rev 7 M48T512Y, M48T512V 1 Description Description The M48T512Y/V TIMEKEEPER® RAM is a 512 Kb x 8 non-volatile static RAM and realtime clock organized as 524,288 words by 8 bits. The special DIP package provides a fully integrated battery-backed memory and real-time clock solution. The M48T512Y/V directly replaces industry standard 512 Kb x 8 SRAMs. It also provides the non-volatility of Flash without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. Figure 1. Logic diagram ) s ( ct VCC 19 A0-A18 DQ0-DQ7 W M48T512Y M48T512V G ) (s P e let E O o s b s b O VSS AI02262 Signal names d o r A0-A18 DQ0-DQ7 t c u r P e t e l o E Table 1. u d o 8 Address inputs Data inputs / outputs Chip enable input G Output enable input W WRITE enable input VCC Supply voltage VSS Ground Doc ID 5747 Rev 7 5/23 Description Figure 2. M48T512Y, M48T512V 32-pin DIP connections A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 3. )- s ( t c 32,768 Hz CRYSTAL e t e ol LITHIUM CELL u d o s b O u d o r P e AI02263 8x8 TIMEKEEPER REGISTERS A0-A18 POWER Pr 524,280 x 8 SRAM ARRAY DQ0-DQ7 E VOLTAGE SENSE AND SWITCHING CIRCUITRY W VPFD VCC 6/23 ) s ( ct t e l o Block diagram OSCILLATOR AND CLOCK CHAIN s b O VCC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 1 32 2 31 30 3 29 4 28 5 27 6 26 7 8 M48T512Y 25 9 M48T512V 24 23 10 22 11 21 12 20 13 19 14 18 15 17 16 G VSS Doc ID 5747 Rev 7 AI02384 M48T512Y, M48T512V 2 Operating modes Operating modes The 32-pin, 600 mil hybrid DIP houses a controller chip, SRAM, quartz crystal, and a long life lithium button cell in a single package. Figure 3 on page 6 illustrates the static memory array and the quartz controlled clock oscillator. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - compliant until the year 2100), 30, and 31 day months are made automatically. Byte 7FFF8h is the clock control register (see Table 5 on page 12). This byte controls user access to the clock information and also stores the clock calibration setting. The seven clock bytes (7FFFFh-7FFF9h) are not the actual clock counters; they are memory locations consisting of BiPORT™ READ/WRITE memory cells within the static RAM array. The M48T512Y/V includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T512Y/V also has its own power-fail detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER register data and SRAM, providing data security in the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored. ) s ( ct u d o Table 2. r P e Mode VCC E Deselect s b O VIH 4.5 to 5.5 V or 3.0 to 3.6 V WRITE READ VSO to VPFD u d o Deselect r P e ≤ )- s ( t c READ Deselect t e l o Operating modes (min)(1) VSO(1) G X W DQ0-DQ7 Power X High Z Standby VIL X VIL DIN Active VIL VIL VIH DOUT Active VIL VIH VIH High Z Active X X X High Z CMOS standby X X X High Z Battery backup mode 1. See Table 11 on page 18 for details. Note: 2.1 X = VIH or VIL; VSO = Battery backup switchover voltage. s b O t e l o READ mode The M48T512Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The unique address specified by the 19 address inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access times (tELQV) or output enable access time (tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain active, output data will remain valid for output data hold time (tAXQX) but will go indeterminate until the next address access. Doc ID 5747 Rev 7 7/23 Operating modes Figure 4. M48T512Y, M48T512V READ mode AC waveforms tAVAV VALID A0-A18 tAXQX tAVQV tELQV tEHQZ E tELQX tGLQV tGHQZ ) s ( ct G tGLQX DQ0-DQ7 u d o DATA OUT Note: WE = High. Table 3. READ mode AC characteristics r P e t e l o bs Parameter(1) Symbol O ) s ( t c AI02389 M48T512Y M48T512V –70 –85 Min Max Min Unit Max tAVAV READ cycle time tAVQV Address valid to output valid 70 85 ns tELQV Chip enable low to output valid 70 85 ns tGLQV Output enable low to output valid 55 ns du ro 70 85 40 ns tELQX(2) Chip enable low to output transition 5 5 ns tGLQX(2) tEHQZ(2) tGHQZ(2) Output enable low to output transition 5 5 ns tAXQX Address transition to output transition P e t e l o bs Chip enable high to output Hi-Z 25 30 ns Output enable high to output Hi-Z 25 30 ns 10 O 5 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. CL = 5 pF. 8/23 Doc ID 5747 Rev 7 ns M48T512Y, M48T512V 2.2 Operating modes WRITE mode The M48T512Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable) are low state after the address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls. Figure 5. ) s ( ct WRITE AC waveforms, WRITE enable controlled u d o tAVAV VALID A0-A18 r P e tAVWH tAVEL t e l o E s b O tWLWH tAVWL ) (s W tWHQX tWLQZ ct du DQ0-DQ7 tWHDX DATA INPUT ro P e t e l o Figure 6. s b O tWHAX tDVWH AI02386 WRITE AC waveforms, chip enable controlled tAVAV VALID A0-A18 tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DATA INPUT DQ0-DQ7 tDVEH AI02387 Doc ID 5747 Rev 7 9/23 Operating modes Table 4. M48T512Y, M48T512V WRITE mode AC characteristics M48T512Y M48T512V -70 -85 Parameter(1) Symbol Min Max Min Unit Max tAVAV WRITE cycle time 70 85 ns tAVWL Address valid to WRITE enable low 0 0 ns tAVEL Address valid to chip enable low 0 0 ns tWLWH WRITE enable pulse width 50 60 ns tELEH Chip enable low to chip enable high 55 65 ns tWHAX WRITE enable high to address transition 5 5 tEHAX Chip enable high to address transition 10 15 tDVWH Input valid to WRITE enable high 30 35 tDVEH Input valid to chip enable high 30 35 tWHDX WRITE enable high to input transition 5 tEHDX Chip enable high to input transition 10 tWLQZ(2)(3) WRITE enable low to output Hi-Z tAVWH Address valid to write enable high tAVEH Address valid to chip enable high tWHQX (2)(3) WRITE enable high to output transition e t e l Pr O ) o s b 60 ns ct u d o 25 60 (s) 5 ns ns ns 5 ns 15 ns 30 ns 70 ns 70 ns 5 ns 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. CL = 5pF. s ( t c 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. u d o 2.3 Data retention mode r P e With valid VCC applied, the M48T512Y/V operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting itself when VCC falls between VPFD (max) and VPFD (min). All outputs become high impedance and all inputs are treated as “Don't care.” bs t e l o Note: O 10/23 A power failure during a WRITE cycle may corrupt data at the current addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T512Y/V may respond to transient noise spikes on VCC that cross into the deselect window during the time the device is sampling VCC.Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery, preserving data and powering the clock. The internal energy source will maintain data in the M48T512Y/V for an accumulated period of at least 10 years at room temperature. As system power rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus tREC (min). Normal RAM operation can resume tREC after VCC exceeds VPFD (max). Refer to application note (AN1012) on the ST website for more information on battery life. Doc ID 5747 Rev 7 M48T512Y, M48T512V Clock operations 3 Clock operations 3.1 Reading the clock Updates to the TIMEKEEPER® registers should be halted before clock data is read to prevent reading data in transition (see Table 5 on page 12). The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the control register (7FFF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. The next update occurs 1 second after the READ bit is reset to a '0.' ) s ( ct 3.2 u d o r P e Setting the clock Bit D7 of the control register (7FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 5 on page 12). Resetting the WRITE bit to a '0' then transfers the values of all time registers 7FFFFh7FFF9h to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur approximately one second later. t e l o ) (s s b O Note: Upon power-up, both the WRITE bit and the READ bit will be reset to '0.' 3.3 Stopping and starting the oscillator. t c u d o r The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is located at bit D7 within 7FFF9h. Setting it to a '1' stops the oscillator. The M48T512Y/V is shipped from STMicroelectronics with the STOP bit set to a '1.' When reset to a '0,' the M48T512Y/V oscillator starts after approximately one second. P e Note: s b O t e l o It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST bit (FT) or the STOP bit (ST). Doc ID 5747 Rev 7 11/23 Clock operations Table 5. M48T512Y, M48T512V Register map Data Function/range Address D7 D6 7FFFEh 0 0 0 7FFFDh 0 0 10 date 7FFFCh 0 0 0 7FFFBh 0 0 10 hours 7FFFAh 0 7FFF9h ST 7FFF8h W 7FFFFh D5 D4 D3 D2 10 years D1 BCD format D0 Year Year 00-99 Month Month 01-12 Date Date 01-31 Day 01-07 Hours Hours 00-23 10 minutes Minutes Minutes 00-59 10 seconds Seconds Seconds 00-59 R 10 M 0 S 0 Day Calibration Keys: u d o S = SIGN bit r P e R = READ bit W = WRITE bit t e l o ST = STOP bit 0 = Must be set to '0' 3.4 ) s ( ct Control Calibrating the clock ) (s s b O The M48T512Y/V is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are factory calibrated at 25 °C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25 °C, which equates to about ±1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than +1/–2 ppm at 25 °C. The oscillation rate of crystals changes with temperature. The M48T512Y/V design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage (see Figure 8 on page 13). t c u d o r P e t e l o s b O The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration bits occupy the five lower order bits (D4-D0) in the control register 7FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles; that is, +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. 12/23 Doc ID 5747 Rev 7 M48T512Y, M48T512V Clock operations One method for ascertaining how much calibration a given M48T512Y/V may require involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in STMicroelectronics’ application note AN934, “TIMEKEEPER® calibration.” This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the calibration bits. For more information on calibration see application note AN934, “TIMEKEEPER® calibration” on the ST website. Figure 7. Crystal accuracy across temperature ) s ( ct Frequency (ppm) 20 u d o 0 r P e –20 –40 t e l o –60 –80 )- –120 u d o –160 –40 e t e ol s b O T0 = 25 °C s ( t c –140 Figure 8. s b O ΔF = -0.038 ppm (T - T )2 ± 10% 0 F C2 –100 –30 Pr –20 –10 0 10 20 30 Temperature °C 40 50 60 70 80 AI00999 Calibration waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B Doc ID 5747 Rev 7 13/23 Clock operations 3.5 M48T512Y, M48T512V VCC noise and negative going transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. A ceramic bypass capacitor value of 0.1 µF is recommended to filter these spikes. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount). Figure 9. ) s ( ct Supply voltage protection VCC u d o VCC 0.1µF r P e DEVICE t e l o VSS Caution: ) (s s b O Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode. t c u d o r P e t e l o s b O 14/23 AI02169 Doc ID 5747 Rev 7 M48T512Y, M48T512V 4 Maximum ratings Maximum ratings Stressing the device above the ratings listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Absolute maximum ratings Symbol Parameter Ambient operating temperature TA Storage temperature (VCC off, oscillator off) TSTG TSLD(1)(2) Input or output voltages VCC Supply voltage IO Output current PD Power dissipation Unit 0 to 70 °C ) s ( ct –40 to 85 Lead solder temperature for 10 seconds VIO Value 260 du –0.3 to VCC +0.3 ro M48T512Y P e M48T512V t e l o °C °C V –0.3 to 7.0 V –0.3 to 4.6 V 20 mA 1 W s b O 1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries. 2. For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid damaging the crystal. Caution: ) (s Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode. t c u d o r P e t e l o s b O Doc ID 5747 Rev 7 15/23 DC and AC parameters 5 M48T512Y, M48T512V DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions Parameter Supply voltage (VCC) M48T512Y M48T512V Unit 4.5 to 5.5 3.0 to 3.6 V 0 to 70 0 to 70 Load capacitance (CL) Ambient operating temperature (TA) 100 50 Input rise and fall times ≤5 ≤5 Input pulse voltages ns 0 to 3 V 1.5 V bs O ) s ( t c du t e l o Figure 10. AC measurement load circuit DEVICE UNDER TEST P e 1.5 °C pF ro 0 to 3 Input and output timing ref. voltages ) s ( ct 650Ω (1) 1.75V CL u d o r P e let o s b O CL includes JIG capacitance AI03971 1. CL = 50 pF for M48T512V. Table 8. Capacitance Parameter(1)(2) Min Max Unit Input capacitance - 20 pF Input / output capacitance - 20 pF Symbol CIN CIO(3) 1. Effective capacitance measured with power supply at 5 V (M48T512Y) or 3.3 V (M48T512V). Sampled only, not 100% tested. 2. At 25 °C, f = 1 MHz. 3. Outputs deselected. 16/23 Doc ID 5747 Rev 7 M48T512Y, M48T512V Table 9. DC and AC parameters DC characteristics Symbol M48T512Y M48T512V –70 –85 Test condition(1) Parameter Min ILI ILO (2) 0 V ≤ VIN ≤ VCC Input leakage current Output leakage current ICC Supply current ICC1 Supply current (standby) TTL ICC2 Supply current (standby) CMOS Max Min Unit Max ±2 ±2 µA 0 V ≤ VOUT ≤ VCC ±2 ±2 µA Outputs open 115 60 mA E = VIH 8 4 mA E ≥ VCC – 0.2 V 4 3 mA VIL Input low voltage –0.3 0.8 –0.3 0.4 V VIH Input high voltage 2.2 VCC +0.3 2.2 VCC +0.3 V VOL Output low voltage IOL = 2.1 mA VOH Output high voltage IOH = –1 mA 0.4 c u d ) s ( t 0.4 2.4 2.2 V V o r P 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. Outputs deselected. e t e ol Figure 11. Power down/up mode AC waveforms VCC VPFD (max) VPFD (min) VSO VSS tF t c u tFB INPUTS od RECOGNIZED (Including E) r P e OUTPUTS ) (s s b O tDR tR tRB DON'T CARE RECOGNIZED HIGH-Z VALID VALID let o s b tREC AI02385 O Doc ID 5747 Rev 7 17/23 DC and AC parameters Table 10. M48T512Y, M48T512V Power down/up AC characteristics Parameter(1) Symbol tF(2) VPFD (max) to VPFD (min) VCC fall time tFB(3) VPFD (min) to VSS VCC fall time Min Max Unit 300 µs M48T512Y 10 µs M48T512V 150 µs tR VPFD (min) to VPFD (max) VCC rise time 10 µs tRB VSS to VPFD (min) VCC rise time 1 µs tREC E recovery time 40 200 ms 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min). ) s ( ct 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. Table 11. u d o Power down/up trip points DC characteristics Parameter(1)(2) Symbol Min M48T512Y VPFD Power-fail deselect voltage VSO Battery backup switchover voltage tDR(3) Expected data retention time 4.2 1. All voltages referenced to VSS. M48T512Y ) (s s b O 2.7 Pr 4.35 e t e ol M48T512V M48T512V Typ 2.9 Max Unit 4.5 V 3.0 V 3.0 V VPFD –100mV V 10 2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 3. At 25 °C, VCC = 0 V. t c u d o r P e t e l o s b O 18/23 Doc ID 5747 Rev 7 YEARS M48T512Y, M48T512V 6 Environmental information Environmental information Figure 12. Recycling symbols ) s ( ct u d o r P e This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. t e l o Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. ) (s s b O t c u d o r P e t e l o s b O Doc ID 5747 Rev 7 19/23 Package mechanical data 7 M48T512Y, M48T512V Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. PMDIP32 – 32-pin plastic module DIP, package outline A A1 B S L eA e1 u d o e3 r P e D N t e l o E 1 Note: Drawing is not to scale. Table 12. PMDIP mm inches Min Max 9.52 0.365 0.375 0.38 – 0.015 – 0.43 0.59 0.017 0.023 C 0.20 0.33 0.008 0.013 D 42.42 43.18 1.670 1.700 E 18.03 18.80 0.710 0.740 2.29 2.79 0.090 0.110 0.590 0.630 A A1 e t e l B 20/23 ct u d o Typ O s b O PMDIP32 – 32-pin plastic module DIP, package mechanical data Symb o s b ) (s ) s ( ct C Pr e1 e3 Min Max 9.27 38.1 Typ 0.100 1.500 eA 14.99 16.00 L 3.05 3.81 0.120 0.150 S 1.91 2.79 0.075 0.110 N 32 Doc ID 5747 Rev 7 0.600 32 M48T512Y, M48T512V 8 Part numbering Part numbering Table 13. Ordering information scheme Example: M48T 512Y –70 PM 1 Device type M48T Supply voltage and write protect voltage ) s ( ct 512Y(1) = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V 512V(1) = VCC = 3.0 to 3.6 V; VPFD = 2.7 to 3.0 V u d o Speed r P e –70 = 70 ns (512Y) –85 = 85 ns (512V) t e l o Package PM = PMDIP32 ) (s Temperature range s b O t c u 1 = 0 to 70 °C d o r Shipping method Blank = ECOPACK® package, tubes P e t e l o 1. Device is not recommended for new design. Contact local ST sales office for availability. s b O For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Doc ID 5747 Rev 7 21/23 Revision history 9 M48T512Y, M48T512V Revision history Table 14. Document revision history Date Revision June-1998 1 03-Dec-1999 1.1 11-Dec-2000 2 20-Jul-2001 2.1 Segments re-ordered; temp./voltage info. added to tables (Table 8, 9, 3, 4, 10, 11) 07-Aug-2001 2.2 Text re-ordered from last adjustment (“Operating modes” section) 20-May-2002 2.3 Add countries to disclaimer 07-Aug-2002 2.4 Add marketing status 31-Mar-2003 3 v2.2 template applied; data retention condition updated (Table 11) 22-Feb-2005 4 Reformatted; IR reflow update (Table 6) 25-Mar-2008 5 Reformatted document, minor text changes; updated cover page and Table 13 concerning availability of M48T512V (3.3 V version); updated Figure 9, 10, 11, Table 9, 12, Section 7: Package mechanical data. 21-Jun-2010 6 Updated Features, Section 4, Table 12, 13; text in Section 7; added Section 6: Environmental information; reformatted document. 7 Devices are not recommended for new design (updated cover page and Table 13); updated footnote of Table 6; updated Section 6: Environmental information. 24-Jun-2011 Changes First issue M48T512Y: VPFD (Min) changed; AC measurement load circuit changed (Figure 10); tFB and tRB changed (Figure 11, Table 10) Reformatted u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 22/23 ) s ( ct Doc ID 5747 Rev 7 M48T512Y, M48T512V ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. 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