M48Z128Y-70PM1

M48Z128 M48Z128Y 5.0 V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM Not recommended for new design Features ■ Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of power ■ Battery internally isolated until power is first applied ■ Automatic power-fail chip deselect and WRITE protection ■ WRITE protect voltages: (VPFD = power-fail deselect voltage) – M48Z128: VCC = 4.75 to 5.5 V; 4.5 V ≤ VPFD ≤ 4.75 V – M48Z128Y: VCC = 4.5 to 5.5 V; 4.2 V ≤ VPFD ≤ 4.5 V ) (s ) s ( ct r P e 32 t e l o s b O u d o 1 PMDIP32 module t c u ■ Pin and function compatible with JEDEC standard 128 K x 8 SRAMs ■ RoHS compliant – Lead-free second level interconnect d o r P e t e l o s b O September 2011 Doc ID 2426 Rev 6 This is information on a product still in production but not recommended for new designs. 1/20 www.st.com 1 Contents M48Z128, M48Z128Y Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11 ) s ( ct u d o 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 2/20 Doc ID 2426 Rev 6 M48Z128, M48Z128Y List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PMDIP32 – 32-pin plastic DIP module, package mechanical data. . . . . . . . . . . . . . . . . . . 16 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 2426 Rev 6 3/20 List of figures M48Z128, M48Z128Y List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8 Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PMDIP32 – 32-pin plastic DIP module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 4/20 Doc ID 2426 Rev 6 M48Z128, M48Z128Y 1 Description Description The M48Z128/Y ZEROPOWER® RAM is a 128 Kbit x 8 non-volatile static RAM organized as131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic, 32-pin DIP module to provide a highly integrated batterybacked memory solution. The M48Z128/Y is a non-volatile pin and function equivalent to any JEDEC standard 128 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 32-pin, 600 mil DIP module houses the M48Z128/Y silicon with a long-life lithium button cell in a single package. Figure 1. ) s ( ct Logic diagram u d o VCC 17 A0-A16 t e l o E ) (s t e l o O bs s b O od VSS A0-A16 Address inputs r P e Table 1. t c u DQ0-DQ7 M48Z128 M48Z128Y W G r P e 8 AI01194 Signal names DQ0-DQ7 Data inputs / outputs E Chip enable input G Output enable input W WRITE enable input VCC Supply voltage VSS Ground NC Not connected internally Doc ID 2426 Rev 6 5/20 Description M48Z128, M48Z128Y Figure 2. DIP connections NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 3. 1 32 2 31 30 3 29 4 28 5 27 6 26 7 8 M48Z128 25 9 M48Z128Y 24 23 10 22 11 21 12 20 13 19 14 18 15 17 16 bs VCC O ) s ( t c VOLTAGE SENSE AND SWITCHING CIRCUITRY e t e ol o r P du POWER u d o AI01195 A0-A16 131,072 x 8 DQ0-DQ7 SRAM ARRAY E W G INTERNAL BATTERY s b O 6/20 ) s ( ct r P e t e l o Block diagram E VCC A15 NC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS Doc ID 2426 Rev 6 AI01196 M48Z128, M48Z128Y 2 Operating modes Operating modes The M48Z128/Y also has its own power-fail detect circuit. The control circuitry constantly monitors the single VCC supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the switchover voltage (VSO), the control circuitry connects the battery which maintains data until valid power returns. Table 2. Operating modes Mode VCC Deselect WRITE 4.75 to 5.5 V or 4.5 to 5.5 V READ READ VSO to VPFD Deselect VSO(1) ≤ Deselect (min)(1) E G W DQ0-DQ7 VIH X X High Z Standby VIL X VIL DIN Active VIL VIL VIH DOUT VIL VIH VIH High Z X X X High Z X X e t e ol 1. See Table 10 on page 15 for details. X Note: X = VIH or VIL; VSO = battery backup switchover voltage. 2.1 READ mode ) (s Power ) s ( ct du o r P High Z Active Active CMOS standby Battery backup mode s b O The M48Z128/Y is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The device architecture allows ripple-through access of data from eight of 1,048,576 locations in the static storage array. Thus, the unique address specified by the 17 address inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E and G (output enable) access times are also satisfied. If the E and G access times are not met, valid data will be available after the later of chip enable access time (tELQV) or output enable access time (tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain low, output data will remain valid for output data hold time (tAXQX) but will go indeterminate until the next address access. t c u d o r P e s b O t e l o Doc ID 2426 Rev 6 7/20 Operating modes M48Z128, M48Z128Y Figure 4. Chip enable or output enable controlled, READ mode AC waveforms tAVAV A0-A16 VALID tAXQX tAVQV tELQV tEHQZ E tELQX tGLQV tGHQZ G ) s ( ct tGLQX DATA OUT DQ0-DQ7 Note: WRITE enable (W) = high. Figure 5. AI01197 o r P Address controlled, READ mode AC waveforms e t e ol tAVAV A0-A16 VALID tAVQV ) (s DQ0-DQ7 s b O tAXQX DATA VALID ct Note: u d o AI01078 Chip enable (E) and output enable (G) = low, WRITE enable (W) = high. Pr Table 3. e t e l READ mode AC characteristics Symbol so b O du Parameter M48Z128/Y M48Z128/Y M48Z128/Y –70 –85 –120 (1) Min Max Min Max Min Unit Max tAVAV READ cycle time tAVQV Address valid to output valid 70 85 120 ns tELQV Chip enable low to output valid 70 85 120 ns tGLQV Output enable low to output valid 35 45 60 ns 70 85 120 ns tELQX(2) Chip enable low to output transition 5 5 5 ns tGLQX(2) Output enable low to output transition 3 3 3 ns tEHQZ(2) Chip enable high to output Hi-Z 30 35 45 ns tGHQZ(2) Output enable high to output Hi-Z 20 25 35 ns tAXQX Address transition to output transition 5 5 10 ns 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 2. CL = 5 pF. 8/20 Doc ID 2426 Rev 6 M48Z128, M48Z128Y 2.2 Operating modes WRITE mode The M48Z128/Y is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX or tEHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. Figure 6. ) s ( ct WRITE enable controlled, WRITE AC waveforms tAVAV u d o VALID A0-A16 r P e tAVWH tAVEL t e l o E tWLWH tAVWL W )- s b O tWHQX tWLQZ t(s c u d DQ0-DQ7 tWHAX tWHDX DATA INPUT tDVWH AI01198 o r P Output enable (G) = high. Note: e t e l Figure 7. o s b Chip enable controlled, WRITE AC waveforms tAVAV VALID A0-A16 O tAVEH tELEH tAVEL tEHAX E tAVWL W tEHDX DATA INPUT DQ0-DQ7 tDVEH Note: AI01199 Output enable (G) = high. Doc ID 2426 Rev 6 9/20 Operating modes Table 4. Symbol M48Z128, M48Z128Y WRITE mode AC characteristics M48Z128/Y M48Z128/Y M48Z128/Y –70 –85 –120 Parameter(1) Min Max Min Max Min Unit Max tAVAV WRITE cycle time 70 85 120 ns tAVWL Address valid to WRITE enable Low 0 0 0 ns tAVEL Address valid to chip enable low 0 0 0 ns tWLWH WRITE enable pulse width 55 65 85 ns tELEH Chip enable low to chip enable high 55 75 100 tWHAX WRITE enable high to address transition 5 5 5 tEHAX Chip enable high to address transition 15 15 15 tDVWH Input valid to WRITE enable high 30 35 45 tDVEH Input valid to chip enable high 30 35 tWHDX WRITE enable high to input transition 0 0 tEHDX Chip enable high to input transition 10 tWLQZ(2)(3) e t e ol 25 tAVWH Address valid to WRITE enable high tAVEH Address valid to chip enable high tWHQX(2)(3) 10 WRITE enable low to output Hi-Z 65 s b O 65 WRITE enable high to output transition 5 ns ) s ( ct ns ns ns u d o 45 Pr ns 0 ns 10 30 ns 40 ns 75 100 ns 75 100 ns 5 5 ns 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 2. CL = 5 pF. ) (s 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. 2.3 t c umode Data retention d o r P e t e ol With valid VCC applied, the M48Z128/Y operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as “Don't care.” bs O If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, write protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data. The internal coin cell will maintain data in the M48Z128/Y after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on battery storage life refer to the application note AN1012. 10/20 Doc ID 2426 Rev 6 M48Z128, M48Z128Y 2.4 Operating modes VCC noise and negative going transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (see Figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface-mount). Figure 8. ) s ( ct u d o Supply voltage protection r P e VCC VCC t e l o 0.1µF ) (s DEVICE s b O VSS AI02169 t c u d o r P e t e l o s b O Doc ID 2426 Rev 6 11/20 Maximum ratings 3 M48Z128, M48Z128Y Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol Parameter Ambient operating temperature TA Value Unit 0 to 70 °C TSTG Storage temperature (VCC off, oscillator off) –40 to 85 TBIAS Temperature under bias –10 to 70 TSLD(1) Lead solder temperature for 10 seconds VIO Input or output voltages VCC Supply voltage IO Output current PD Power dissipation du 260 ro –0.3 to 7 P e t e l o s b O ) s ( ct °C °C °C V –0.3 to 7.0 V 20 mA 1 W 1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries. Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode. ) (s t c u d o r P e t e l o s b O 12/20 Doc ID 2426 Rev 6 M48Z128, M48Z128Y 4 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. Operating and AC measurement conditions Parameter Supply voltage (VCC) M48Z128/Y Unit 4.75 to 5.5 V or 4.5 to 5.5 V Ambient operating temperature (TA) 100 Input rise and fall times ≤5 Input pulse voltages °C pF du ns ro 0 to 3 P e Input and output timing ref. voltages Note: ) s ( ct 0 to 70 Load capacitance (CL) 1.5 V V t e l o Output Hi-Z is defined as the point where data is no longer driven. Figure 9. AC measurement load circuit DEVICE UNDER TEST ) (s t c u s b O t e l o Table 7. CL includes JIG capacitance CIO (3) AI03630 Capacitance Parameter(1)(2) Symbol CIN 1.75V CL = 100pF d o r P e s b O 650Ω Min Max Unit Input capacitance - 10 pF Input / output capacitance - 10 pF 1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested. 2. At 25 °C, f = 1 MHz. 3. Outputs deselected. Doc ID 2426 Rev 6 13/20 DC and AC parameters Table 8. M48Z128, M48Z128Y DC characteristics M48Z128/Y Sym Test condition(1) Parameter –70 / –85 / –120 Min Input leakage current ILI ILO(2) Output leakage current Unit Max 0 V ≤ VIN ≤ VCC ±1 µA 0 V ≤ VOUT ≤ VCC ±1 µA E = VIL Outputs open 105 mA E = VIH 7 mA E = VCC – 0.2 V 4 mA ICC Supply current ICC1 Supply current (standby) TTL ICC2 Supply current (standby) CMOS VIL Input low voltage –0.3 0.8 V VIH Input high voltage 2.2 VCC + 0.3 V VOL Output low voltage IOL = 2.1 mA 0.4 V VOH Output high voltage IOH = –1 mA Pr u d o 2.4 ) s ( ct 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). e t e ol 2. Outputs deselected. ) (s s b O t c u d o r P e t e l o s b O 14/20 Doc ID 2426 Rev 6 V M48Z128, M48Z128Y DC and AC parameters Figure 10. Power down/up mode AC waveforms VCC VPFD (max) VPFD (min) VSO tF tR tDR tFB tRB tER tWP E DON'T CARE RECOGNIZED RECOGNIZED ) s ( ct HIGH-Z VALID OUTPUTS VALID u d o (PER CONTROL INPUT) Table 9. (PER CONTROL INPUT) r P e Power down/up AC characteristics Parameter(1) Symbol tF(2) VPFD (max) to VPFD (min) VCC fall time tFB(3) VPFD (min) to VSS VCC fall time t e l o Min s b O Max AI01031 Unit 300 µs 10 µs tR VPFD (min) to VPFD (max) VCC rise time 10 µs tRB VSS to VPFD (min) VCC rise time 1 µs tWP Write protect time 40 150 µs tER E recovery time 40 120 ms ) (s t c u 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). d o r 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after VCC passes VPFD (min). P e 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. t e l o Table 10. s b O Power down/up trip points DC characteristics Parameter(1)(2) Symbol VPFD Power-fail deselect voltage VSO Battery backup switchover voltage tDR(3) Expected data retention time Min Typ Max Unit M48Z128 4.5 4.6 4.75 V M48Z128Y 4.2 4.3 4.5 V M48Z128/Y 3.0 10 V YEARS 1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 3. At 25 °C; VCC = 0 V. Doc ID 2426 Rev 6 15/20 Package mechanical data 5 M48Z128, M48Z128Y Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 11. PMDIP32 – 32-pin plastic DIP module, package outline A A1 B S L eA e1 u d o e3 r P e D N t e l o E 1 Note: Drawing is not to scale. Table 11. PMDIP mm inches Min Max 9.52 0.365 0.375 0.38 – 0.015 – 0.43 0.59 0.017 0.023 C 0.20 0.33 0.008 0.013 D 42.42 43.18 1.670 1.700 E 18.03 18.80 0.710 0.740 e1 2.29 2.79 0.090 0.110 A A1 e t e l B 16/20 ct u d o Typ O s b O PMDIP32 – 32-pin plastic DIP module, package mechanical data Symb o s b ) (s ) s ( ct C e3 Pr Min Max 9.27 38.1 Typ 1.5 eA 14.99 16.00 0.590 0.630 L 3.05 3.81 0.120 0.150 S 1.91 2.79 0.075 0.110 N 32 Doc ID 2426 Rev 6 32 M48Z128, M48Z128Y 6 Part numbering Part numbering Table 12. Ordering information scheme Example: M48Z 128Y –70 PM 1 Device type M48Z Supply voltage and write protect voltage ) s ( ct 128(1) = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V 128Y(1) = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V u d o Speed r P e –70 = 70 ns –85 = 85 ns t e l o –120(2) = 120 ns Package PM = PMDIP32 ) (s s b O t c u Temperature range 1 = 0 to 70 °C d o r Shipping method P e blank = ECOPACK® package, tubes t e l o O bs 1. Device is not recommended for new design. Contact local ST sales office for availability. 2. Contact local ST sales office for availability. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Doc ID 2426 Rev 6 17/20 Environmental information 7 M48Z128, M48Z128Y Environmental information Figure 12. Recycling symbols ) s ( ct u d o r P e This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. t e l o Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. ) (s s b O t c u d o r P e t e l o s b O 18/20 Doc ID 2426 Rev 6 M48Z128, M48Z128Y 8 Revision history Revision history Table 13. Revision history Date Revision Changes May-1999 1 First issue Document layout changed; surface-mount chip set solution added 13-Apr-2000 2 20-Jun-2000 2.1 tGLQX changed (Table 3) 19-Jul-2000 2.2 M48Z128V added 14-Sep-2001 3 07-Nov-2001 3.1 Remove chipset option from ordering Information (Table 12) 20-May-2002 3.2 Modify reflow time and temperature footnotes (Table 5) 18-Nov-2002 3.3 Modifying SMT solution text (Figure 2, 4;Table 2) 17-Sep-2003 3.4 Remove references to M68ZXXX (obsolete) parts (Figure 4; Table 2); update disclaimer 22-Feb-2005 4 Reformatted; IR reflow, SO package updates (Table 5) 20-Jul-2010 5 Reformatted document; updated Features, Section 3: Maximum ratings, Table 11, 12; added ECOPACK® text to Section 5; added Section 7: Environmental information; removed SOH28, SNAPHAT® housing and all references from datasheet. 26-Sep-2011 6 Devices are not recommended for new design (updated cover page, Table 12); updated footnote of Table 5: Absolute maximum ratings; updated Section 7: Environmental information; removed M48Z128V. Reformatted; added temperature information (Table 7, 8, 3, 4, 9, 10) ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 2426 Rev 6 19/20 M48Z128, M48Z128Y ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. r P e All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. t e l o No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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