M48Z2M1V-85PL1

M48Z2M1Y M48Z2M1V 5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER® SRAM Not recommended for new design Features ■ Integrated, ultra low power SRAM, power-fail control circuit, and batteries ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of power ■ Automatic power-fail chip deselect and WRITE protection ■ WRITE protect voltages (VPFD = power-fail deselect voltage): – M48Z2M1Y: VCC = 4.5 to 5.5 V; 4.2 V ≤ VPFD ≤ 4.5 V – M48Z2M1V: VCC = 3.0 to 3.6 V; 2.8 V ≤ VPFD ≤ 3.0 V ) (s Batteries are internally isolated until power is applied ■ Pin and function compatible with JEDEC standard 2 Mb x 8 SRAMs ■ RoHS compliant – Lead-free second level interconnect u d o 36 1 r P e t e l o ■ ) s ( ct PLDIP36 module s b O t c u d o r P e t e l o s b O June 2011 Doc ID 5135 Rev 6 This is information on a product still in production but not recommended for new designs. 1/20 www.st.com 1 Contents M48Z2M1Y, M48Z2M1V Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11 ) s ( ct u d o 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 2/20 Doc ID 5135 Rev 6 M48Z2M1Y, M48Z2M1V List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PLDIP36 – 36-pin plastic DIP long module, package mechanical data . . . . . . . . . . . . . . . 16 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 5135 Rev 6 3/20 List of figures M48Z2M1Y, M48Z2M1V List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8 WRITE enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PLDIP36 – 36-pin plastic DIP long module, package outline . . . . . . . . . . . . . . . . . . . . . . . 16 Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 4/20 Doc ID 5135 Rev 6 M48Z2M1Y, M48Z2M1V 1 Description Description The M48Z2M1Y/V ZEROPOWER® RAM is a non-volatile 16,777,216-bit, static RAM organized as 2,097,152 words by 8 bits. The device combines two internal lithium batteries, CMOS SRAMs and a control circuit in a plastic 36-pin DIP, long module. The ZEROPOWER RAM replaces industry standard SRAMs. It provides the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. Figure 1. Logic diagram ) s ( ct VCC 21 8 A0-A20 W r P e M48Z2M1Y M48Z2M1V E t e l o G bs VSS Table 1. Address inputs s ( t c DQ0-DQ7 du E ro G let P e o s b AI02048 O ) Signal names A0-A20 u d o DQ0-DQ7 Data inputs / outputs Chip enable Output enable W WRITE enable VCC Supply voltage VSS Ground NC Not connected internally O Doc ID 5135 Rev 6 5/20 Description M48Z2M1Y, M48Z2M1V Figure 2. DIP connections NC A20 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 3. 1 36 2 35 34 3 33 4 5 32 6 31 30 7 29 8 M48Z2M1Y 9 M48Z2M1V 28 27 10 26 11 25 12 24 13 14 23 15 22 16 21 20 17 19 18 ) s ( ct t e l o s b O POWER ) (s VOLTAGE SENSE AND SWITCHING CIRCUITRY E t c u d o r u d o r P e Block diagram VCC 2048K x 8 SRAM ARRAY AI02049 A0-A20 DQ0-DQ7 E W G INTERNAL BATTERIES P e VSS t e l o s b O 6/20 VCC A19 NC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 Doc ID 5135 Rev 6 AI02050 M48Z2M1Y, M48Z2M1V 2 Operation modes Operation modes The M48Z2M1Y/V has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operations brought on by low VCC. As VCC falls below approximately 3 V, the control circuitry connects the batteries which sustain data until valid power returns. Table 2. Operating modes Mode VCC Deselect 3.0 to 3.6 V or 4.5 to 5.5 V WRITE READ READ Deselect VSO to VPFD ≤ VSO Deselect (min)(1) (1) E G W DQ0DQ7 Power VIH X X High Z Standby VIL X VIL DIN VIL VIL VIH DOUT VIL VIH VIH High Z X X X High Z CMOS standby X X X High Z Battery backup mode e t e l ) s ( ct Pr u d o Active Active Active o s b 1. See Table 10 on page 15 for details. Note: X = VIH or VIL; VSO = battery backup switchover voltage. 2.1 READ mode O ) s ( t c The M48Z2M1Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The device architecture allows ripple-through access of data from eight of 16,777,216 locations in the static storage array. Thus, the unique address specified by the 21 address inputs defines which one of the 2,097,152 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E (chip enable) and G (output enable) access times are also satisfied. If the E and G access times are not met, valid data will be available after the later of chip enable access time (tELQV) or output enable access time (tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain low, output data will remain valid for output data hold time (tAXQX) but will go indeterminate until the next address access. u d o r P e t e l o s b O Figure 4. Address controlled, READ mode AC waveforms A0-A20 tAVAV tAVQV DQ0-DQ7 tAXQX DATA VALID AI02051 Note: Chip enable (E) and output enable (G) = low, WRITE enable (W) = high. Doc ID 5135 Rev 6 7/20 Operation modes M48Z2M1Y, M48Z2M1V Figure 5. Chip enable or output enable controlled, READ mode AC waveforms tAVAV VALID A0-A20 tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 ) s ( ct DATA OUT AI02052 Note: WRITE enable (W) = high. Table 3. READ mode AC characteristics Pr M48Z2M1Y ete Parameter(1) Symbol –70 ol Min bs READ cycle time tAVAV tAVQV(2) Address valid to output valid tAXQX(2) Address transition to output transition tEHQZ (3) tELQV(2) tELQX(3) tGHQZ(3) tGLQV(2) tGLQX(3) e t e ol O ) s ( t c u d o Max 70 M48Z2M1V –85 Min Unit Max 85 70 5 ns 85 5 ns ns Chip enable high to output Hi-Z 30 35 ns Chip enable low to output valid 70 85 ns du Chip enable low to output transition 5 5 ns Output enable high to output Hi-Z 25 35 ns Output enable low to output valid 35 45 ns o r P Output enable low to output transition 5 5 ns 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). s b O 8/20 2. CL = 100 pF or 50 pF (see Figure 9 on page 13). 3. CL = 5 pF (see Figure 9 on page 13). Doc ID 5135 Rev 6 M48Z2M1Y, M48Z2M1V 2.2 Operation modes WRITE mode The M48Z2M1Y/V is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. Figure 6. ) s ( ct WRITE enable controlled, WRITE mode AC waveforms tAVAV u d o VALID A0-A20 tAVWH r P e tAVEL E t e l o tWLWH tAVWL W bs tWLQZ O ) DQ0-DQ7 t(s Note: tWHQX tWHDX DATA INPUT tDVWH AI02053 Output enable (G) = high. o r P Figure 7. ete ol bs O c u d tWHAX Chip enable controlled, WRITE mode AC waveforms tAVAV A0-A20 VALID tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI02054 Note: Output enable (G) = high. Doc ID 5135 Rev 6 9/20 Operation modes Table 4. M48Z2M1Y, M48Z2M1V WRITE mode AC characteristics M48Z2M1Y M48Z2M1V –70 –85 Parameter(1) Symbol Min Max Min Unit Max tAVAV WRITE cycle time 70 85 ns tAVEH Address valid to chip enable high 65 75 ns tAVEL Address valid to chip enable low 0 0 ns tAVWH Address valid to WRITE enable high 65 75 ns tAVWL Address valid to WRITE enable low 0 0 ns tDVEH Input valid to chip enable high 30 35 tDVWH Input valid to WRITE enable high 30 35 tEHAX Chip enable high to address transition 15 tEHDX Chip enable high to input transition 10 tELEH Chip enable low to chip enable high 55 tWHAX WRITE enable high to address transition 5 tWHDX WRITE enable high to input transition tWHQX(2)(3) tWLQZ(2)(3) WRITE enable high to output transition o s b WRITE enable low to output Hi-Z WRITE enable pulse width tWLWH e t e l O ) 0 15 ns ct u d o 15 Pr 5 55 (s) ns ns ns 75 ns 5 ns 0 ns 5 ns 25 30 65 ns ns 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6V (except where noted). s ( t c 2. CL = 5 pF (see Figure 9 on page 13). 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. u d o 2.3 Data retention mode r P e With valid VCC applied, the M48Z2M1Y/V operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as “Don't care.” t e l o s b O If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, write protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data. The internal coin cells will maintain data in the M48Z2M1Y/V after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the batteries are disconnected, and the power supply is switched to external VCC. Write protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on battery storage life refer to the application note AN1012. 10/20 Doc ID 5135 Rev 6 M48Z2M1Y, M48Z2M1V 2.4 Operation modes VCC noise and negative going transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in Figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 8. ) s ( ct u d o Supply voltage protection r P e VCC t e l o VCC 0.1µF )- s b O DEVICE VSS AI02169 s ( t c u d o r P e t e l o s b O Doc ID 5135 Rev 6 11/20 Maximum ratings 3 M48Z2M1Y, M48Z2M1V Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol Parameter Ambient operating temperature Storage temperature (VCC off) Temperature under bias Lead solder temperature for 10 seconds TA TSTG TBIAS TSLD(1) VIO Input or output voltages M48Z2M1Y M48Z2M1V VCC Supply voltage M48Z2M1Y M48Z2M1V IO s b O Unit 0 to 70 –40 to 85 –40 to 85 260 °C °C °C °C –0.3 to 7 –0.3 to 4.6 V V –0.3 to 7 –0.3 to 4.6 V V 20 1 mA W ) s ( ct u d o r P e t e l o Output current Power dissipation PD Value 1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries. Caution: ) (s Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode. t c u d o r P e t e l o s b O 12/20 Doc ID 5135 Rev 6 M48Z2M1Y, M48Z2M1V 4 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. Operating and AC measurement conditions Parameter M48Z2M1Y M48Z2M1V Unit 4.5 to 5.5 3.0 to 3.6 V Supply voltage (VCC) 0 to 70 0 to 70 Load capacitance (CL) Ambient operating temperature (TA) 100 50 Input rise and fall times ≤5 ≤5 Input pulse voltages Note: ro 0 to 3 Input and output timing ref. voltages P e 1.5 du ) s ( ct °C pF ns 0 to 3 V 1.5 V t e l o Output Hi-Z is defined as the point where data is no longer driven. Figure 9. AC testing load circuit s b O 5V ) (s ct u d o let r P e o s b 1.9kΩ DEVICE UNDER TEST 1kΩ OUT CL = 100pF or 5pF (Y) 50pF or 5pF (V) CL includes JIG capacitance AI07816 O Doc ID 5135 Rev 6 13/20 DC and AC parameters Table 7. M48Z2M1Y, M48Z2M1V Capacitance Parameter(1)(2) Symbol CIN CIO (3) Min Max Unit Input capacitance - 40 pF Input / output capacitance - 40 pF 1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested. 2. Outputs deselected. 3. At 25 °C. Table 8. DC characteristics Sym Test condition(1) Parameter M48Z2M1Y Unit Min ILI(2) ILO Input leakage current (2) Output leakage current ICC Supply current ICC1 Supply current (standby) TTL ICC2 Supply current (standby) CMOS VIL Input low voltage VIH Input high voltage VOL Output low voltage VOH Output high voltage Max 0 V ≤ VIN ≤ VCC ±4 0 V ≤ VOUT ≤ VCC ±4 E = VIL, Outputs open 140 e t e l E = VIH 10 E ≥ VCC – 0.2 V o s b O ) s ( t c Min Max c u d o r P 8 ±4 µA ±4 µA 70 mA 2 mA 1 mA –0.3 0.8 –0.3 0.6 V 2.2 VCC + 0.3 2.2 VCC + 0.3 V 0.4 V IOL = 2.1 mA IOH = –1 mA ) s ( t M48Z2M1V 0.4 2.4 2.2 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). u d o 2. Outputs deselected. r P e t e l o s b O 14/20 Doc ID 5135 Rev 6 V M48Z2M1Y, M48Z2M1V DC and AC parameters Figure 10. Power down/up mode AC waveforms VCC VPFD (max) VPFD (min) VSO tDR tF tR tFB tRB tWP E tER DON'T CARE RECOGNIZED RECOGNIZED HIGH-Z VALID OUTPUTS VALID (PER CONTROL INPUT) Table 9. Power down/up AC characteristics u d o Parameter(1) Symbol tER E recovery time tF(2) VPFD (max) to VPFD (min) VCC fall time tFB(3) VPFD (min) to VSO VCC fall time tWP -O Write protect time from VCC = VPFD ) s ( ct Pr AI01031 Min Max Unit 40 120 ms 300 µs M48Z2M1Y 10 µs M48Z2M1V 150 µs 10 µs e t e l o s b VPFD (min) to VPFD (max) VCC rise time tR ) s ( ct (PER CONTROL INPUT) M48Z2M1Y 40 150 µs M48Z2M1V 40 250 µs 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after VCC passes VPFD (min). u d o 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. Pr Table 10. e t e ol Power down/up trip points DC characteristics Symbol s b O VPFD VSO tDR (3) Parameter(1)(2) Power-fail deselect voltage Battery backup switchover voltage Min Typ Max Unit M48Z2M1Y 4.2 4.3 4.5 V M48Z2M1V 2.8 2.9 3.0 V M48Z2M1Y 3.0 V M48Z2M1V 2.45 V Expected data retention time 10 YEARS 1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 3. At 25 °C; VCC = 0 V. Doc ID 5135 Rev 6 15/20 Package mechanical data 5 M48Z2M1Y, M48Z2M1V Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 11. PLDIP36 – 36-pin plastic DIP long module, package outline A A1 B S L eA e1 u d o e3 r P e D t e l o N E 1 Note: Table 11. od r P e A t e l o s b O t c u s b O PMDIP PLDIP36 – 36-pin plastic DIP long module, package mechanical data Symb Typ mm inches Min Max 9.27 Typ Min Max 9.52 0.3650 0.3748 A1 0.38 B 0.43 0.59 0.0169 0.0232 C 0.20 0.33 0.0079 0.0130 D 52.58 53.34 2.0701 2.1000 E 18.03 18.80 0.7098 0.7402 e1 2.30 2.81 0.0906 0.1106 0.5902 0.6299 e3 eA 16/20 ) (s Drawing is not to scale. ) s ( ct C 0.0150 43.18 1.7 14.99 16.00 L 3.05 3.81 0.1201 0.1500 S 4.45 5.33 0.1752 0.2098 N 36 Doc ID 5135 Rev 6 36 M48Z2M1Y, M48Z2M1V 6 Part numbering Part numbering Table 12. Ordering information scheme Example: M48Z 2M1Y –70 PL 1 Device type M48Z Supply voltage and write protect voltage ) s ( ct 2M1Y(1) = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V 2M1V(1) = VCC = 3.0 to 3.6 V; VPFD = 2.8 to 3.0 V u d o Speed r P e –70 = 70 ns (Y) –85 = 85 ns (V) t e l o Package PL = PLDIP36 ) (s Temperature range s b O t c u 1 = 0 to 70°C 9 = extended temperature d o r Shipping method P e blank = ECOPACK® package, tubes s b O t e l o 1. Not recommended for new design. Contact ST sales office for availability. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. Doc ID 5135 Rev 6 17/20 Environmental information 7 M48Z2M1Y, M48Z2M1V Environmental information Figure 12. Recycling symbols ) s ( ct u d o r P e This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. t e l o Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. ) (s s b O t c u d o r P e t e l o s b O 18/20 Doc ID 5135 Rev 6 M48Z2M1Y, M48Z2M1V 8 Revision history Revision history Table 13. Document revision history Date Revision Jul-1999 1 31-Aug-2000 2 From preliminary data to datasheet 20-Mar-2002 3 Reformatted; temperature information added to tables (Table 7, 8, 3, 4, 9, 10) 29-May-2002 3.1 Modified “VCC noise and negative going transients” text 28-Mar-2003 3.2 Remove 5 V/5%, add 3 V part (Figure 1, 2, 9; Table 5, 6, 8, 2, 3, 4, 9, 10, 12) 02-Jul-2003 3.3 Changed characteristic (Table 8) 18-Feb-2005 4 Reformatted; IR reflow update (Table 5) 02-Aug-2010 5 Updated Features, Section 3, Table 12; added ECOPACK® text to Section 5; added Section 7: Environmental information. 6 Devices are not recommended for new design (updated cover page, Table 12); updated footnote of Table 5: Absolute maximum ratings; updated Section 7: Environmental information. 24-Jun-2011 Changes First issue ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 5135 Rev 6 19/20 M48Z2M1Y, M48Z2M1V ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. r P e All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. t e l o No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. ) (s s b O UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. t c u UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. d o r P e t e l o Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. s b O ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 20/20 Doc ID 5135 Rev 6