M48Z35, M48Z35Y
256 Kbit (32 Kbit x 8) ZEROPOWER® SRAM
Datasheet - production data
• SOIC package provides direct connection for a
SNAPHAT® top which contains the battery
• RoHS compliant
• Lead-free second level interconnect
28
1
Description
PDIP 28.7
The M48Z35/Y ZEROPOWER® RAM is a 32 K x
8, non-volatile static RAM that integrates powerfail deselect circuitry and battery control logic on a
single die. The monolithic chip is available in two
special packages to provide a highly integrated
battery-backed memory solution.
Battery CAPHAT™
The M48Z35/Y is a non-volatile pin and function
equivalent to any JEDEC standard 32 K x 8
SRAM. It also easily fits into many ROM,
EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement
for special WRITE timing or limitations on the
number of WRITEs that can be performed. The
28-pin 600 mil DIP CAPHAT™ houses the
M48Z35/Y silicon with a long life lithium button
cell in a single package.
SNAPHAT® battery
28
1
SOH28
Features
• Integrated, ultra low power SRAM, power-fail
control circuit, and battery
• READ cycle time equals WRITE cycle time
• Automatic power-fail chip deselect and WRITE
protection
• WRITE protect voltages:
(VPFD = power-fail deselect voltage)
• M48Z35: VCC = 4.75 to 5.5 V;
4.5 V ≤ VPFD ≤ 4.75 V
• M48Z35Y: 4.5 to 5.5 V;
4.2 V ≤ VPFD ≤ 4.5 V
The 28-pin 330 mil SOIC provides sockets with
gold plated contacts at both ends for direct
connection to a separate SNAPHAT® housing
containing the battery. The unique design allows
the SNAPHAT battery package to be mounted on
top of the SOIC package after the completion of
the surface mount process. Insertion of the
SNAPHAT housing after reflow prevents potential
battery damage due to the high temperatures
required for device surface-mounting. The
SNAPHAT housing is keyed to prevent reverse
insertion.
• Self-contained battery in the CAPHAT™ DIP
package
The SOIC and battery packages are shipped
separately in plastic anti-static tubes or in tape &
reel form.
• Packaging includes a 28-lead SOIC and
SNAPHAT® top (to be ordered separately)
For the 28-lead SOIC, the battery package (i.e.
SNAPHAT) part number is “M4Z28-BR00SH1.”.
• Pin and function compatible with JEDEC
standard 32 K x 8 SRAMs
October 2020
This is information on a product in full production.
DocID02608 Rev 11
1/20
www.st.com
Contents
M48Z35, M48Z35Y
Contents
1
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . .11
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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DocID02608 Rev 11
M48Z35, M48Z35Y
1
Diagram
Diagram
Figure 1. Logic diagram
VCC
15
8
A0-A14
DQ0-DQ7
W
M48Z35
M48Z35Y
E
G
VSS
AI01616D
Table 1. Signal names
A0-A14
DQ0-DQ7
Address inputs
Data inputs / outputs
E
Chip enable input
G
Output enable input
W
WRITE enable input
VCC
Supply voltage
VSS
Ground
DocID02608 Rev 11
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Pin connection
2
M48Z35, M48Z35Y
Pin connection
Figure 2. DIP connections
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
M48Z35 22
8 M48Z35Y 21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI01617D
Figure 3. SOIC connections
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
4/20
1
28
27
2
26
3
25
4
5
24
6
23
22
7
M48Z35Y
21
8
9
20
10
19
11
18
12
17
13
16
14
15
DocID02608 Rev 11
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI02303C
M48Z35, M48Z35Y
Pin connection
Figure 4. Block diagram
A0-A14
LITHIUM
CELL
POWER
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
32K x 8
SRAM ARRAY
DQ0-DQ7
E
VPFD
W
G
VCC
VSS
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AI01619B
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Operation modes
3
M48Z35, M48Z35Y
Operation modes
The M48Z35/Y also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low VCC. As VCC falls below
approximately 3 V, the control circuitry connects the battery which maintains data until valid
power returns.
Table 2. Operating modes
Mode
VCC
Deselect
WRITE
READ
4.75 to 5.5 V
or
4.5 to 5.5 V
READ
Deselect
VSO to
Deselect
VPFD(min)(1)
≤ VSO
(1)
E
G
W
DQ0DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
X
X
X
High Z
CMOS standby
X
X
X
High Z
Battery backup mode
1. See Table 6 for details.
Note:
X = VIH or VIL; VSO = battery backup switchover voltage.
3.1
READ mode
The M48Z35/Y is in the READ mode whenever W (WRITE enable) is high, E (chip enable)
is low. The device architecture allows ripple-through access of data from eight of 264,144
locations in the static storage array. Thus, the unique address specified by the 15 address
inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be
available at the data I/O pins within address access time (tAVQV) after the last address input
signal is stable, providing that the E and G access times are also satisfied. If the E and G
access times are not met, valid data will be available after the latter of the chip enable
access time (tELQV) or output enable access time (tGLQV).
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If
the address inputs are changed while E and G remain active, output data will remain valid
for output data hold time (tAXQX) but will go indeterminate until the next address access.
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M48Z35, M48Z35Y
Operation modes
Figure 5. READ mode AC waveforms
tAVAV
VALID
A0-A14
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00925
WRITE enable (W) = high.
Note:
Table 3. READ mode AC characteristics
M48Z02/M48Z12
Parameter(1)
Symbol
Unit
Min.
tAVAV
tAVQV
(2)
tELQV(2)
tGLQV
(2)
tELQX(3)
tGLQX
(3)
READ cycle time
Max.
70
ns
Address valid to output valid
70
ns
Chip enable low to output valid
70
ns
Output enable low to output valid
35
ns
Chip enable low to output transition
5
ns
Output enable low to output transition
5
ns
tEHQZ (3)
Chip enable high to output Hi-Z
25
ns
tGHQZ(3)
Output enable high to output Hi-Z
25
ns
tAXQX
(2)
Address transition to output transition
10
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. CL = 100 pF
3. CL = 5 pF
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Operation modes
3.2
M48Z35, M48Z35Y
WRITE mode
The M48Z35/Y is in the WRITE mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of tEHAX from chip enable or tWHAX from WRITE enable prior
to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the
end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE
cycles to avoid bus contention; although, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ after W falls.
Figure 6. WRITE enable controlled, WRITE AC waveform
tAVAV
VALID
A0-A14
tAVWH
tAVEL
tWHAX
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00926
Figure 7. Chip enable controlled, WRITE AC waveforms
tAVAV
A0-A14
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
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AI00927
M48Z35, M48Z35Y
Operation modes
Table 4. WRITE mode AC characteristics
M48Z35/M48Z35Y
Symbol
Parameter(1)
-70
Min.
Unit
Max.
tAVAV
WRITE cycle time
70
ns
tAVWL
Address valid to WRITE enable low
0
ns
tAVEL
Address valid to chip enable 1 low
0
ns
tWLWH
WRITE enable pulse width
50
ns
tELEH
Chip enable low to chip enable 1 high
55
ns
tWHAX
WRITE enable high to address transition
0
ns
tEHAX
Chip enable high to address transition
0
ns
tDVWH
Input valid to WRITE enable high
30
ns
tDVEH
Input valid to chip enable high
30
ns
tWHDX
WRITE enable high to input transition
5
ns
tEHDX
Chip enable high to input transition
5
ns
tWLQZ
(2)(3)
WRITE enable low to output Hi-Z
25
ns
tAVWH
Address valid to WRITE enable high
60
ns
tAVEH
Address valid to chip enable high
60
ns
WRITE enable high to output transition
5
ns
tWHQX(2)(3)
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
3.3
Data retention mode
With valid VCC applied, the M48Z35/Y operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “don't care.”
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48Z35/Y may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery which
preserves data. The internal button cell will maintain data in the M48Z35/Y for an
accumulated period of at least 11 years when VCC is less than VSO.
As system power returns and VCC rises above VSO, the battery is disconnected, and the
power supply is switched to external VCC. Write protection continues until VCC reaches
VPFD (min) plus trec (min). E should be kept high as VCC rises past VPFD (min) to prevent
inadvertent write cycles prior to system stabilization. Normal RAM operation can resume trec
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20
Operation modes
M48Z35, M48Z35Y
after VCC exceeds VPFD (max). For more information on battery storage life refer to the
application note AN1012.
Figure 8. Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tRB
tDR
tPD
INPUTS
trec
DON'T CARE
RECOGNIZED
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01168C
Table 5. Power down/up AC characteristics
Parameter(1)
Symbol
tPD
E or W at VIH before power down
tF(2)
tFB(3)
Min.
Max.
Unit
0
µs
VPFD (max) to VPFD (min) VCC fall time
300
µs
VPFD (min) to VSS VCC fall time
10
µs
tR
VPFD (min) to VPFD (max) VCC rise time
10
µs
tRB
VSS to VPFD (min) VCC rise time
1
µs
trec
VPFD (max) to inputs recognized
40
200
ms
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 6. Power down/up trip points DC characteristics
Parameter(1)
Symbol
VPFD
Power-fail deselect voltage
VSO
Battery backup switchover voltage
tDR(2)
Expected data retention time
Min.
Typ.
Max.
M48Z35
4.5
µs
M48Z35Y
4.2
µs
M48Z35/Y
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
10/20
µs
µs
2. At 25 °C, VCC = 0 V.
Note:
Unit
All voltages referenced to VSS.
DocID02608 Rev 11
M48Z35, M48Z35Y
3.4
Operation modes
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 9) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS).
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
Figure 9. Supply voltage protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
DocID02608 Rev 11
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20
Maximum ratings
4
M48Z35, M48Z35Y
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 7. Absolute maximum ratings
Symbol
TA
TSTG
TSLD(1) (2)
Parameter
Value
Unit
0 to 70
°C
SNAPHAT® top
–40 to 85
°C
CAPHAT® DIP
–40 to 85
°C
SOH28
–40 to 85
°C
260
°C
Ambient operating temperature
Storage temperature (VCC off, oscillator off)
Lead solder temperature for 10 seconds
VIO
Input or output voltages
–0.3 to 7
V
VCC
Supply voltage
–0.3 to 7
V
IO
Output current
20
mA
PD
Power dissipation
1
W
1. For DIP package, soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds.
Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of
wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage
to the batteries.
2. For SOH28 package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260 °C (the time above
255 °C must not exceed 30 seconds).
Caution:
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Caution:
Do NOT wave solder SOIC to avoid damaging SNAPHAT® sockets.
12/20
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M48Z35, M48Z35Y
5
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in Table 8.
Designers should check that the operating conditions in their projects match the
measurement conditions when using the quoted parameters.
Table 8. Operating and AC measurement conditions
Parameter
M48Z35
M48Z35Y
Unit
4.75 to 5.5
4.5 to 5.5
V
0 to 70
0 to 70
°C
Load capacitance (CL)
100
100
pF
Input rise and fall times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Supply voltage (VCC)
Ambient operating temperature (TA)
Input pulse voltages
Input and output timing ref. voltages
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 10. AC measurement load circuit
645Ω
DEVICE
UNDER
TEST
CL = 100pF or
5pF
1.75V
CL includes JIG capacitance
AI03211
Table 9. Capacitance
Parameter(1)(2)
Symbol
CIN
CIO
(3)
Min.
Max.
Unit
Input capacitance
-
10
pF
Input / output capacitance
-
10
pF
1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested.
2. Outputs deselected.
3. At 25°C.
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Package mechanical data
6
M48Z35, M48Z35Y
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 11. PDIP 28.7 – 28-pin plastic DIP, battery CAPHAT™, package outline
A2
A
A1
B1
B
L
C
e1
eA
e3
D
N
E
1
PCDIP
Note:
Drawing is not to scale.
Table 10. PDIP 28.7 – 28 pin plastic DIP, battery CAPHAT™, package mech. data
mm
inches
Symb
Typ.
Min.
Max.
A
8.89
A1
Min.
Max.
9.65
0.350
0.380
0.38
0.76
0.015
0.030
A2
8.38
8.89
0.330
0.350
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
39.37
39.88
1.550
1.570
E
17.83
18.34
0.702
0.722
e1
2.29
2.79
0.090
0.110
e3
14/20
33.02
Typ.
1.3
eA
15.24
16.00
0.600
0.630
L
3.05
3.81
0.120
0.150
N
28
DocID02608 Rev 11
28
M48Z35, M48Z35Y
Package mechanical data
Table 11. SOH28 – 28-lead plastic small outline, battery SNAPHAT®, pack. outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note:
Drawing is not to scale.
Table 12. SOH28 – 28-lead plastic small outline, battery SNAPHAT®, pack. mech. data
mm
inches
Symbol
Typ.
Min.
A
Max.
Typ.
Min.
3.05
Max.
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
a
0°
8°
0°
8°
N
28
e
CP
1.27
0.050
28
0.10
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20
Package mechanical data
M48Z35, M48Z35Y
Table 13. SH – 4-pin SNAPHAT® housing for 48 mAh battery, package outline
A1
A2
A3
A
eA
B
L
eB
D
E
SHZP-A
Note:
Drawing is not to scale.
Table 14. SH – 4-pin SNAPHAT® housing for 48 mAh battery, pack. mech. data
mm
inches
Symbol
Typ.
Min.
A
Typ.
Min.
9.78
Max.
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
16/20
Max.
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
DocID02608 Rev 11
M48Z35, M48Z35Y
7
Part numbering
Part numbering
Table 15. Ordering information
Order code
M48Z35-70PC1
M48Z35Y-70PC1
M48Z35Y-70MH1F
Caution:
Package
PDIP 28.7
Temperature
range
Speed
Supply voltage
VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V
0 to 70 °C
70
SOH28
VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V
VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V
Do not place the SNAPHAT battery package “M4Zxx-BR00SH1” in conductive foam as it will
drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Table 16. SNAPHAT® battery table
Part number
M4Z28-BR00SH1
M4Z32-BR00SH1
Description
Lithium battery (48 mAh) SNAPHAT®
Lithium battery (120 mAh)
SNAPHAT®
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Package
SH
SH
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Environmental information
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M48Z35, M48Z35Y
Environmental information
Figure 12. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
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Revision history
Revision history
Table 17. Document revision history
Date
Revision
Changes
Aug-1999
1
21-Apr-2000
1.1
10-May-2001
2
29-May-2002
2.1
02-Apr-2003
3
v2.2 template applied; test condition updated (Table 6)
03-Mar-2004
4
Reformatted; updated with Lead-free information (Table 7, 15)
20-Aug-2004
5
Reformatted; remove references to ‘crystal’ (cover page)
09-Jun-2005
6
Removal of SNAPHAT®, industrial temperature sales types (Table 3,
4, 5, 6, 7, 8, 10, 15).
02-Nov-2007
7
Reformatted; added lead-free second level interconnect information to
cover page and Section 5: Package mechanical data; updated Table
7, 15, 16
25-Mar-2009
8
Updated Table 7, text in Section 5: Package mechanical data; added
Section 7: Environmental information.
19-Aug-2010
9
Updated Section 3, Table 11; reformatted document.
07-Jun-2011
10
Updated footnote 1 of Table 7: Absolute maximum ratings; updated
Section 7: Environmental information.
06-Oct-2020
11
Added Table 15: Ordering information.
Updated package name.
First issue
SH and SH28 packages for 2-pin and 2-socket removed
Reformatted; added temperature information (Table 9, 10, 3, 4, 5, 6)
Modified reflow time and temperature footnotes (Table 7)
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