M48Z512A
M48Z512AY, M48Z512AV
4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM
Not recommended for new design
Features
■
Integrated, ultra low power SRAM, power-fail
control circuit, and battery
■
Conventional SRAM operation; unlimited
WRITE cycles
■
10 years of data retention in the absence of
power
■
Automatic power-fail chip deselect and WRITE
protection
■
Two WRITE protect voltages:
(VPFD = power-fail deselect voltage)
– M48Z512A: VCC = 4.75 to 5.5 V;
4.5 V ≤ VPFD ≤ 4.75 V
– M48Z512AY: VCC = 4.5 to 5.5 V;
4.2 V ≤ VPFD ≤ 4.5 V
– M48Z512AV: VCC = 3.0 to 3.6 V;
2.8 V ≤ VPFD ≤ 3.0 V
1
PMDIP32 module
Description
The M48Z512A/Y/V ZEROPOWER® RAM is a
non-volatile, 4,194,304-bit static RAM organized
as 524,288 words by 8 bits. The devices combine
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic, 32-pin DIP module.
■
Battery internally isolated until power is applied
■
Pin and function compatible with JEDEC
standard 512 K x 8 SRAMs
■
PMDIP32 is an ECOPACK® package
■
RoHS compliant
– Lead-free second level interconnect
June 2011
32
Doc ID 5146 Rev 9
This is information on a product still in production but not recommended for new designs.
1/21
www.st.com
1
Contents
M48Z512A, M48Z512AY, M48Z512AV
Contents
1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
Doc ID 5146 Rev 9
M48Z512A, M48Z512AY, M48Z512AV
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PMDIP32 – 32-pin plastic DIP module, package mechanical data. . . . . . . . . . . . . . . . . . . 17
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Doc ID 5146 Rev 9
3/21
List of figures
M48Z512A, M48Z512AY, M48Z512AV
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
4/21
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8
Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PMDIP32 – 32-pin plastic DIP module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Doc ID 5146 Rev 9
M48Z512A, M48Z512AY, M48Z512AV
1
Device overview
Device overview
Figure 1.
Logic diagram
VCC
19
8
A0-A18
W
E
DQ0-DQ7
M48Z512A
M48Z512AY
M48Z512AV
G
VSS
Table 1.
AI02043
Signal names
A0-A18
DQ0-DQ7
Address inputs
Data inputs/outputs
E
Chip enable input
G
Output enable input
W
WRITE enable input
VCC
Supply voltage
VSS
Ground
Doc ID 5146 Rev 9
5/21
Device overview
Figure 2.
M48Z512A, M48Z512AY, M48Z512AV
DIP connections
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
M48Z512A
8
M48Z512AY
9 M48Z512AV
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI02044
Figure 3.
Block diagram
VCC
A0-A18
POWER
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
512K x 8
SRAM ARRAY
DQ0-DQ7
E
W
G
INTERNAL
BATTERY
VSS
6/21
Doc ID 5146 Rev 9
AI02045
M48Z512A, M48Z512AY, M48Z512AV
2
Operating modes
Operating modes
The M48Z512A/Y/V also has its own power-fail detect circuit. The control circuitry constantly
monitors the single VCC supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit WRITE protects the SRAM, providing a high degree of data security in
the midst of unpredictable system operation brought on by low VCC. As VCC falls below the
switchover voltage (VSO), the control circuitry connects the battery which maintains data
until valid power returns.
The ZEROPOWER® RAM replaces industry standard SRAMs. It provides the nonvolatility of
PROMs without any requirement for special WRITE timing or limitations on the number of
WRITEs that can be performed.
Table 2.
Operating modes
Mode
Deselect
WRITE
READ
READ
Deselect
VCC
E
G
W
DQ0-DQ7
Power
4.75 to 5.5 V
or
4.5 to 5.5 V
or
3.0 to 3.6 V
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
X
X
X
High Z
CMOS standby
X
X
X
High Z
Battery backup mode
VSO to VPFD
Deselect
≤
(min)(1)
VSO(1)
1. X = VIH or VIL; VSO = battery backup switchover voltage.
Note:
See Table 10 on page 16 for details.
2.1
READ mode
The M48Z512A/Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
4,194,304 locations in the static storage array. Thus, the unique address specified by the 19
address inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (tAVQV) after the last
address input signal is stable, providing that the E (chip enable) and G (output enable)
access times are also satisfied. If the E and G access times are not met, valid data will be
available after the later of chip enable access time (tELQV) or output enable access Time
(tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the
outputs are activated before tAVQV, the data lines will be driven to an indeterminate state
until tAVQV. If the address inputs are changed while E and G remain low, output data will
remain valid for output data hold time (tAXQX) but will go indeterminate until the next address
access.
Doc ID 5146 Rev 9
7/21
Operating modes
Figure 4.
M48Z512A, M48Z512AY, M48Z512AV
Chip enable or output enable controlled, READ mode AC waveforms
tAVAV
VALID
A0-A18
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI01221
1. WRITE enable (W) = high
Figure 5.
Address controlled, READ mode AC waveforms
A0-A18
tAVAV
tAVQV
DQ0-DQ7
tAXQX
DATA VALID
AI01220
1. Chip enable (E) and output enable (G) = low, WRITE enable (W) = high
8/21
Doc ID 5146 Rev 9
M48Z512A, M48Z512AY, M48Z512AV
Table 3.
Operating modes
READ mode AC characteristics
(1)
Symbol
Parameter
M48Z512A/Y
–70
Min
Max
M48Z512A/Y/V
–85
Min
Unit
Max
tAVAV
READ cycle time
tAVQV
Address valid to output valid
70
85
ns
tELQV
Chip enable low to output valid
70
85
ns
tGLQV
Output enable low to output valid
35
45
ns
(2)
70
85
ns
Chip enable low to output transition
5
5
ns
tGLQX(2)
Output enable low to output transition
5
5
ns
tEHQZ(2)
Chip enable high to output Hi-Z
tELQX
tGHQZ(2) Output enable high to output Hi-Z
tAXQX
Address transition to output transition
5
30
35
ns
20
25
ns
5
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V,
or 3.0 to 3.6 V (except where noted).
2. CL = 5 pF.
2.2
WRITE mode
The M48Z512A/Y/V is in the WRITE mode whenever W and E are active. The start of a
WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated
by the earlier rising edge of W or E.
The addresses must be held valid throughout the cycle. E or W must return high for a
minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE
cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for
tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus
contention; although, if the output bus has been activated by a low on E and G, a low on W
will disable the outputs tWLQZ after W falls.
Doc ID 5146 Rev 9
9/21
Operating modes
Figure 6.
M48Z512A, M48Z512AY, M48Z512AV
WRITE enable controlled, WRITE AC waveforms
tAVAV
A0-A18
VALID
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01222
1. Output enable (G) = high.
Figure 7.
Chip enable controlled, WRITE AC waveforms
tAVAV
A0-A18
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01223
1. Output enable (G) = high.
10/21
Doc ID 5146 Rev 9
M48Z512A, M48Z512AY, M48Z512AV
Table 4.
Symbol
Operating modes
WRITE mode AC characteristics
(1)
Parameter
M48Z512A/Y
–70
Min
Max
M48Z512A/Y/V
–85
Min
Unit
Max
tAVAV
WRITE cycle time
70
85
ns
tAVWL
Address valid to WRITE enable low
0
0
ns
tAVEL
Address valid to chip enable low
0
0
ns
tWLWH
WRITE enable pulse width
55
65
ns
tELEH
Chip enable low to chip enable high
55
75
ns
tWHAX
WRITE enable high to address transition
5
5
ns
tEHAX
Chip enable high to address transition
15
15
ns
tDVWH
Input valid to WRITE enable high
30
35
ns
tDVEH
Input valid to chip enable high
30
35
ns
tWHDX
WRITE enable high to input transition
0
0
ns
tEHDX
Chip enable high to input transition
10
10
ns
tWLQZ(2)(3)
WRITE enable low to output Hi-Z
25
30
ns
tAVWH
Address valid to WRITE enable high
65
75
ns
tAVEH
Address valid to chip enable high
65
75
ns
WRITE enable high to output transition
5
5
ns
tWHQX(2)(3)
1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V
or 3.0 to 3.6 V (except where noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48Z512A/Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect,
WRITE protecting itself tWP after VCC falls below VPFD. All outputs become high impedance,
and all inputs are treated as “don't care.”
If power fail detection occurs during a valid access, the memory cycle continues to
completion. If the memory cycle fails to terminate within the time tWP, WRITE protection
takes place. When VCC drops below VSO, the control circuit switches power to the internal
energy source which preserves data.
The internal coin cell will maintain data in the M48Z512A/Y/V after the initial application of
VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system
power returns and VCC rises above VSO, the battery is disconnected, and the power supply
is switched to external VCC. WRITE protection continues for tER after VCC reaches VPFD to
allow for processor stabilization. After tER, normal RAM operation can resume.
For more information on battery storage life refer to the application note AN1012.
Doc ID 5146 Rev 9
11/21
Operating modes
2.4
M48Z512A, M48Z512AY, M48Z512AV
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (see Figure 8)
is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, ST recommends connecting a schottky
diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817
is recommended for through hole and MBRS120T3 is recommended for surface-mount).
Figure 8.
Supply voltage protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
12/21
Doc ID 5146 Rev 9
M48Z512A, M48Z512AY, M48Z512AV
3
Maximum ratings
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.
Absolute maximum ratings
Symbol
Parameter
TA
Ambient operating temperature
TSTG
Storage temperature (VCC off)
TBIAS
Temperature under bias
TSLD(1)
Value
Grade 1
0 to 70
Grade 6
-40 to 85
Unit
°C
–40 to 85
Grade 1
0 to 70
Grade 6
–40 to 85
°C
°C
Lead solder temperature for 10 seconds
260
°C
–0.3 to 7
V
M48Z512A/512AY
–0.3 to 7.0
V
M48Z512AV
–0.3 to 4.6
V
VIO
Input or output voltages
VCC
Supply voltage
IO
Output current
20
mA
PD
Power dissipation
1
W
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices
shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST
recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.
Caution:
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Doc ID 5146 Rev 9
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DC and AC parameters
4
M48Z512A, M48Z512AY, M48Z512AV
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 6.
Operating and AC measurement conditions
Parameter
M48Z512A/512AY
Supply voltage (VCC)
4.75 to 5.5 V or 4.5 to 5.5
3.0 to 3.6
Grade 1
0 to 70
0 to 70
Grade 6
–40 to 85
–40 to 85
Load capacitance (CL)
100
50
pF
Input rise and fall times
≤5
≤ 5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Ambient operating temperature (TA)
V
°C
Input pulse voltages
Input and output timing ref. voltages
Note:
M48Z512AV Unit
Output Hi-Z is defined as the point where data is no longer driven.
Figure 9.
AC measurement load circuit
650Ω
DEVICE
UNDER
TEST
CL = 100 pF
(1)
or 30 pF
1.75V
CL includes JIG capacitance
AI03903
1. Excluding open drain output pins; 50 pF for M48Z512AV.
Table 7.
Capacitance
Parameter(1)(2)
Symbol
CIN
CIO(3)
Min
Max
Unit
Input capacitance
-
10
pF
Input/output capacitance
-
10
pF
1. Effective capacitance measured with power supply at 5 V (M48Z512A/Y) or 3.3 V (M48Z512AV); sampled
only, not 100% tested.
2. Outputs deselected.
3. At 25 °C.
14/21
Doc ID 5146 Rev 9
M48Z512A, M48Z512AY, M48Z512AV
Table 8.
DC and AC parameters
DC characteristics
Test condition(1)
Sym
Parameter
M48Z512A/Y
–70
Min
ILI(2)
Input leakage current
ILO(2)
Output leakage current
M48Z512AV
–85
Max
Min
Unit
Max
0 V ≤ VIN ≤ VCC
±1
±1
µA
0 V ≤ VOUT ≤ VCC
±1
±1
µA
E = VIL
outputs open
115
50
mA
E = VIH
10
4
mA
E ≥ VCC – 0.2 V
5
3
mA
ICC
Supply current
ICC1
Supply current (standby) TTL
ICC2
Supply current (standby) CMOS
VIL
Input low voltage
–0.3
0.8
–0.3
0.6
V
VIH
Input high voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VOL
Output low voltage
IOL = 2.1 mA
0.4
V
VOH
Output high voltage
IOH = –1 mA
0.4
2.4
2.2
V
1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V
(except where noted).
2. Outputs deselected.
Figure 10. Power down/up mode AC waveforms
tF
VCC
VPFD (max)
VPFD (min)
VSO
VSS
tWP
tDR
tR
tFB
INPUTS
RECOGNIZED
(Including E)
tRB
DON'T CARE
tER
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
AI02385
Doc ID 5146 Rev 9
15/21
DC and AC parameters
Table 9.
M48Z512A, M48Z512AY, M48Z512AV
Power down/up AC characteristics
Parameter(1)
Symbol
Min
tF(2)
VPFD (max) to VPFD (min) VCC fall time
tFB(3)
VPFD (min) to VSS VCC fall time
Max
300
M48Z512A/Y
10
M48Z512AV
150
Unit
µs
µs
tR
VPFD (min) to VPFD (max) VCC rise time
10
µs
tRB
VSS to VPFD (min) VCC rise time
1
µs
tWPT
tER
M48Z512A/Y
40
150
M48Z512AV
40
250
40
120
WRITE protect time
µs
E recovery time
ms
1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V,
or 3.0 to 3.6 V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/WRITE protection not occurring
until 200 µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10.
Power down/up trip points DC characteristics
Parameter(1)(2)
Symbol
VPFD
VSO
tDR
(3)
Power-fail deselect voltage
Min
Typ
Max
Unit
M48Z512A
4.5
4.6
4.75
V
M48Z512AY
4.2
4.3
4.5
V
M48Z512AV
2.8
2.9
3.0
V
M48Z512A/Y
3.0
V
M48Z512AV
2.5
V
Battery backup switchover voltage
Expected data retention time
10
Years
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V,
or 3.0 to 3.6 V (except where noted).
3. At 25 °C; VCC = 0 V.
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5
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 11. PMDIP32 – 32-pin plastic DIP module, package outline
A
A1
B
S
L
C
eA
e1
e3
D
N
E
1
PMDIP
1. Drawing is not to scale.
Table 11.
PMDIP32 – 32-pin plastic DIP module, package mechanical data
mm
inches
Symb
Typ
Min
Max
A
9.27
9.52
A1
0.38
B
0.43
0.59
0.017
0.023
C
0.20
0.33
0.008
0.013
D
42.42
43.18
1.670
1.700
E
18.03
18.80
0.710
0.740
e1
2.29
2.79
0.090
0.110
e3
Typ
Min
Max
0.365
0.375
0.015
38.10
1.50
eA
14.99
16.00
0.590
0.630
L
3.05
3.81
0.120
0.150
S
1.91
2.79
0.075
0.110
N
32
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Part numbering
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M48Z512A, M48Z512AY, M48Z512AV
Part numbering
Table 12.
Ordering information scheme
Example:
M48Z
512AY –70
PM
1
Device type
M48Z
Supply voltage and WRITE protect voltage
512A(1) = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V
512AY(1) = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V
512AV(1) = VCC = 3.0 to 3.6 V; VPFD = 2.8 to 3.0 V
Speed
–70 = 70 ns (for M48Z512A/Y)
–85 = 85 ns (for M48Z512A/Y/V)
Package
PM = PMDIP32
Temperature range
1 = 0 to 70 °C
6 = –40 to 85 °C
1. Device is not recommended for new design. Contact ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
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7
Environmental information
Environmental information
Figure 12. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
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Revision history
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Revision history
Table 13.
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M48Z512A, M48Z512AY, M48Z512AV
Revision history
Date
Revision
Changes
Mar-2000
1
19-Jul-2000
1.1
M48Z12AV added
15-Jan-2001
1.2
Changed LPSRAM device (Table 2)
19-Dec-2001
2
08-Feb-2002
2.1
Remove 85ns speed grade (Table 3, Table 4, and Table 8)
29-May-2002
2.2
Modify reflow time and temperature footnotes (Table 5)
18-Nov-2002
2.3
Modified SMT text (Figure 1, Figure , and Table 2)
17-Sep-2003
2.4
Remove references to M68xxx (obsolete) part (Figure and Table 2);
update disclaimer
30-Nov-2004
3
Reformatted; remove extended temperature references (Table 12)
21-Dec-2004
4
Update Marketing Status for qualification, correct drawing (Figure and
Table 12)
22-Feb-2005
5
IR reflow, SO package updates (Table 5)
21-Dec-2006
6
Document reformatted.
ECOPACK package text added on coverpage.
Note 2 concerning Leaded SOIC package removed below Table 5.
Updated PMDIP32 package mechanical data in Section 5: Package
mechanical data; updated TA to include Grade 1 (0 to 70°C) and Grade
6 (-40 to 85°C).
7-Nov-2008
7
Indicated that M48Z512AV is Not for New Design; removed all
SNAPHAT® battery and SOIC package references; updated Section 5:
Package mechanical data.
02-Aug-2010
8
Updated Features, Section 3, Table 12, ECOPACK® text in Section 5;
added Section 7: Environmental information.
24-Jun-2011
9
Devices are not recommended for new design (updated cover page,
Table 12); updated footnote of Table 5: Absolute maximum ratings;
updated Section 7: Environmental information.
First issue
Reformatted; added temperature information (Table 3, Table 4, Table 7,
Table 8, Table 9, and Table 10); remove chipset option from Ordering
Information (Table 12); remove reference to “clock”
Doc ID 5146 Rev 9
M48Z512A, M48Z512AY, M48Z512AV
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