M68AW031AM70N6T

M68AW031A 256 Kbit (32K x8) 3.0V Asynchronous SRAM FEATURES SUMMARY ■ SUPPLY VOLTAGE: 2.7 to 3.6V ■ 32K x 8 bits SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIME: 70ns ■ LOW STANDBY CURRENT ■ LOW VCC DATA RETENTION: 1.5V ■ TRI-STATE COMMON I/O ■ AUTOMATIC POWER DOWN Figure 1. Packages SO28 (MS) 330 mm TSOP28 (N) 8 x 13.4 mm TSOP28 Reverse (NS) 8 x 13.4 mm November 2003 1/19 M68AW031A TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. TSOP Connections (Reverse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 5. TSOP Connections (Normal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . 10 Figure 11. Chip Enable Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 12. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 13. Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 14. Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SO28 - 28 lead Plastic Small Outline, 330 mils body width, Package Outline . . . . . . . . . . . . . . . . 15 SO28 - 28 lead Plastic Small Outline, 330 mils body width, Package Mechanical Data . . . . . . . . . 15 TSOP28 - 28 lead Normal and Reverse Pinout Plastic Small Outline, Package Outline . . . . . . . . 16 TSOP28 - 28 lead Normal and Reverse Pinout Plastic Small Outline, Package Mechanical Data . 16 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 M68AW031A SUMMARY DESCRIPTION The M68AW031A is a 256 Kbit (262,144 bit) CMOS SRAM, organized as 32,768 bytes by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has an au- tomatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AW031A is available in SO28 (28-lead Small Outline) and TSOP28 (28-lead Thin Small Outline, Standard and Reverse Pinout) packages. Figure 2. Logic Diagram Table 1. Signal Names VCC 15 8 A0-A14 DQ0-DQ7 W M68AW031A E A0-A14 Address Inputs DQ0-DQ7 Data Input/Output E Chip Enable G Output Enable W Write Enable VCC Supply Voltage VSS Ground G VSS AI05935c 3/19 M68AW031A Figure 3. SO Connections A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DQ0 DQ1 DQ2 VSS Figure 5. TSOP Connections (Normal) 1 28 27 2 26 3 25 4 24 5 23 6 22 7 M68AW031A 21 8 20 9 19 10 18 11 17 12 13 16 14 15 VCC W A4 A3 A2 A1 G A0 E DQ7 DQ6 DQ5 DQ4 DQ3 AI04836c 22 21 28 M68AW031A 15 (Reverse) 14 1 7 8 AI05989D 4/19 22 21 VCC A5 A6 A7 A8 A9 A10 A11 28 M68AW031A 15 (Normal) 14 1 7 8 AI05959D Figure 4. TSOP Connections (Reverse) A11 A10 A9 A8 A7 A6 A5 VCC W A4 A3 A2 A1 G G A1 A2 A3 A4 W A12 A13 A14 DQ0 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ7 E A0 A0 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A14 A13 A12 M68AW031A Figure 6. Block Diagram A14 ROW DECODER MEMORY ARRAY A7 DQ7 I/O CIRCUITS COLUMN DECODER DQ0 A0 A6 E W G AI05919 5/19 M68AW031A OPERATION The M68AW031A has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E = High). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cy- cles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E as summarized in the Operating Modes table (see Table 2). Table 2. Operating Modes Operation E W G DQ0-DQ7 Power Deselected VIH X X Hi-Z Standby (ISB) Read VIL VIH VIL Data Output Active (ICC) Write VIL VIL X Data Input Active (ICC) Output Disabled VIL VIH VIH Hi-Z Active (ICC) Note: X = VIH or VIL. Read Mode The M68AW031A is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data of the 262,144 locations in the static memory array, specified by the 15 address inputs. Valid data will be available at the eight output pins within tAVQV after the last stable address, providing G is Low and E is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX but data lines will always be valid at tAVQV. See Figures 9, 10, 11 and Table 7 for details on Read mode AC timings and Characteristics. Write Mode The M68AW031A is in the Write mode whenever the W and E are Low. Either the Chip Enable input (E) or the Write Enable input (W) must be de- 6/19 asserted during Address transitions for subsequent write cycles. When E (W) is Low, write cycle begins on the W (E)'s falling edge. Therefore, address setup time is referenced to Write Enable or Chip Enable as tAVWL and tAVEL respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E or W. If the Output is enabled (E = Low, G = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E, whichever occurs first, and remain valid for tWHDX and tEHDX respectively. See Figures 12, 10 and Table 8 for details on Write mode AC timings and Characteristics. M68AW031A MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for periods greater than 1s periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Absolute Maximum Ratings Symbol Value Unit 20 mA Ambient Operating Temperature –55 to 125 °C TSTG Storage Temperature –65 to 150 °C TLEAD Lead Temperature during Soldering(2) 260(3) °C –0.5 to 4.6 V –0.5 to VCC +0.5 V 1 W IO (1) TA VCC VIO (4) PD Note: 1. 2. 3. 4. Parameter Output Current Supply Voltage Input or Output Voltage Power Dissipation One output at time not to exceed 1 second duration. Compliant with the ECOPACK® 7191395 specification for Lead-free soldering processes. Not exceeding 250°C for more than 30s, and peaking at 260°C. Up to a maximum operating VCC of 3.6V only. 7/19 M68AW031A DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 4. Operating and AC Measurement Conditions Parameter M68AW031A VCC Supply Voltage 2.7 to 3.6V Range 1 0 to 70°C Range 6 –40 to 85°C Ambient Operating Temperature Load Capacitance (CL) 30pF Output Circuit Protection Resistance (R1) 3.0kΩ Load Resistance (R2) 3.1kΩ Input Rise and Fall Times 1ns/V 0 to VCC Input Pulse Voltages Input and Output Timing Ref. Voltages VCC/2 Output Transition Timing Ref. Voltages VRL = 0.3VCC; VRH = 0.7VCC Figure 7. AC Measurement I/O Waveform Figure 8. AC Measurement Load Circuit VCC I/O Timing Reference Voltage R1 VCC VCC/2 0V DEVICE UNDER TEST OUT CL Output Timing Reference Voltage VCC 0V R2 0.7VCC 0.3VCC AI05831 CL includes probe capacitance AI05932 8/19 M68AW031A Table 5. Capacitance CIN COUT Test Condition Parameter(1,2) Symbol Input Capacitance on all pins (except DQ) Output Capacitance Min Max Unit VIN = 0V 6 pF VOUT = 0V 8 pF Note: 1. Sampled only, not 100% tested. 2. At TA = 25°C, f = 1 MHz, VCC = 3.0V. Table 6. DC Characteristics Symbol Parameter Test Condition Min Typ Max Unit 30 mA ICC1 (1,2) Operating Supply Current VCC = 3.6V, f = 1/tAVAV, IOUT = 0mA ICC2 (3) Operating Supply Current VCC = 3.6V, f = 1MHz, IOUT = 0mA 2 5 mA VCC = 3.6V, f = 0, E ≥ VCC –0.2V or VIN = 0.2V or VIN = VCC –0.2V 4 10 µA ISB Standby Supply Current CMOS ILI Input Leakage Current ILO (4) Output Leakage Current 0V ≤ VIN ≤ VCC –1 1 µA 0V ≤ VOUT ≤ VCC –1 1 µA VIH Input High Voltage 2.2 VCC + 0.3 V VIL Input Low Voltage –0.3 0.6 V VOH Output High Voltage IOH = –1.0mA VOL Output Low Voltage IOL = 2.1mA Note: 1. 2. 3. 4. 2.4 V 0.4 V Average AC current, cycling at tAVAV minimum. E = VIL, VIN = VIL or VIH. E ≤ 0.2V, VIN ≤ 0.2V or VIN ≥ VCC –0.2V. Output disabled. 9/19 M68AW031A Figure 9. Address Controlled, Read Mode AC Waveforms tAVAV A0-A14 VALID tAVQV tAXQX DATA VALID DQ0-DQ7 AI05939 Note: E = Low, G = Low, W = High. Figure 10. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. tAVAV VALID A0-A14 tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI05940 Note: Write Enable (W) = High. Figure 11. Chip Enable Controlled, Standby Mode AC Waveforms E ICC ISB tPU tPD 50% AI05956 10/19 M68AW031A Table 7. Read and Standby Mode AC Characteristics M68AW031A Symbol Parameter Unit 70 tAVAV Read Cycle Time Min 70 ns tAVQV Address Valid to Output Valid Max 70 ns tAXQX (1) Data hold from address change Min 10 ns tEHQZ (2,3) Chip Enable High to Output Hi-Z Max 25 ns tELQV Chip Enable Low to Output Valid Max 70 ns Chip Enable Low to Output Transition Min 10 ns tGHQZ (2,3) Output Enable High to Output Hi-Z Max 25 ns tGLQV Output Enable Low to Output Valid Max 35 ns Output Enable Low to Output Transition Min 5 ns tPD (4) Chip Enable High to Power Down Max 70 ns tPU (4) Chip Enable Low to Power Up Min 0 ns tELQX (1) tGLQX (1) Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. 2. At any given temperature and voltage condition, tGHQZ is less than tGLQX and tEHQZ is less than tELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. Tested initially and after any design or process changes that may affect these parameters. 11/19 M68AW031A Figure 12. Write Enable Controlled, Write AC Waveforms tAVAV VALID A0-A14 tAVWH tELWH tWHAX E tWLWH tAVWL W tWLQZ tWHQX tWHDX DQ0-DQ7 DATA (1) DATA (1) DATA INPUT tDVWH AI05941 Note: 1. During this period DQ0-DQ7 are in output state and input signals should not be applied. Figure 13. Chip Enable Controlled, Write AC Waveforms tAVAV A0-A14 VALID tAVEH tAVEL tELEH tEHAX E tWLEH W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI05942 12/19 M68AW031A Table 8. Write Mode AC Characteristics M68AW031A Symbol Parameter Unit 70 tAVAV Write Cycle Time Min 70 ns tAVEH Address Valid to Chip Enable High Min 60 ns tAVEL Address valid to Chip Enable Low Min 0 ns tAVWH Address Valid to Write Enable High Min 60 ns tAVWL Address Valid to Write Enable Low Min 0 ns tDVEH Input Valid to Chip Enable High Min 30 ns tDVWH Input Valid to Write Enable High Min 30 ns tEHAX Chip Enable High to Address Transition Min 0 ns tEHDX Chip enable High to Input Transition Min 0 ns tELEH Chip Enable Low to Chip Enable High Min 60 ns tELWH Chip Enable Low to Write Enable High Min 60 ns tWHAX Write Enable High to Address Transition Min 0 ns tWHDX Write Enable High to Input Transition Min 0 ns tWHQX(1) Write Enable High to Output Transition Min 5 ns tWLEH Write Enable Low to Chip Enable High Min 60 ns Write Enable Low to Output Hi-Z Max 25 ns Write Enable Low to Write Enable High Min 60 ns tWLQZ(1,2) tWLWH Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 13/19 M68AW031A Figure 14. Low VCC Data Retention AC Waveforms DATA RETENTION MODE 3.6V VCC 2.7V VDR > 1.5V tCDR tR E ≥ VDR – 0.2V E AI05905 Table 9. Low VCC Data Retention Characteristics Symbol Parameter ICCDR (1) Supply Current (Data Retention) Test Condition VCC = 1.5V, E ≥ VCC –0.2V, f = 0 (3) Chip Deselected to Data tCDR (1,2) Retention Time tR (2) VDR (1) Operation Recovery Time Supply Voltage (Data Retention) Min E ≥ VCC –0.2V, f = 0 Typ Max Unit 6 µA 0 ns tAVAV ns 1.5 V Note: 1. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤ 0.2V. 2. Tested initially and after any design or process changes that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.2V. 14/19 M68AW031A PACKAGE MECHANICAL Figure 15. SO28 - 28 lead Plastic Small Outline, 330 mils body width, Package Outline D 28 15 c E1 E θ 1 14 A1 A2 b L A L1 ddd e SO-G Note: Drawing is not to scale. Table 10. SO28 - 28 lead Plastic Small Outline, 330 mils body width, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 2.850 A1 0.1122 0.100 A2 2.489 b 0.406 c 2.362 Max 0.0039 2.620 0.0980 0.0930 0.1031 0.0079 0.0142 0.0160 0.200 0.360 D 18.110 18.618 0.7130 0.7330 E 11.811 12.116 0.4650 0.4770 E1 8.407 e 1.270 – – 0.0500 – – L 0.914 0.711 1.117 0.0360 0.0280 0.0440 L1 1.702 1.499 1.905 0.0670 0.0590 0.0750 0 10 0 10 Q 0.3310 15/19 M68AW031A Figure 16. TSOP28 - 28 lead Normal and Reverse Pinout Plastic Small Outline, Package Outline A2 22 21 e 28 1 E B 7 8 D1 A CP D DIE C A1 TSOP-c α L Note: Drawing is not to scale. Table 11. TSOP28 - 28 lead Normal and Reverse Pinout Plastic Small Outline, Package Mechanical Data millimeters inches Symbol Typ Min Typ Min Max A 1.250 0.0492 A1 0.200 0.0079 A2 0.950 1.150 0.0374 0.0453 B 0.170 0.270 0.0067 0.0106 C 0.100 0.210 0.0039 0.0083 CP 0.100 0.0039 D 13.200 13.600 0.5197 0.5354 D1 11.700 11.900 0.4606 0.4685 E 7.900 8.100 0.3110 0.3189 – – – – L 0.500 0.700 0.0197 0.0276 α 0° 5° 0° 5° N 28 e 16/19 Max 0.550 0.0217 28 M68AW031A PART NUMBERING Table 12. Ordering Information Scheme Example: M68AW031 A L 70 MS 6 U Device Type M68 Mode A = Asynchronous Operating Voltage W = 2.7 to 3.6V Array Organization 031 = 256 Kbit (32K x8) Option 1 A = 1 Chip Enable Option 2 L = L-Die M = M-Die Speed Class 70 = 70 ns Package MS = SO28 N = TSOP28 8x13.4mm NS = TSOP28 8x13.4mm (Reverse Pinout) Operative Temperature 6 = –40 to 85 °C 1 = 0 to 70 °C Shipping U = Tube T = Tape and Reel For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 17/19 M68AW031A REVISION HISTORY Table 13. Document Revision History Date Version January 2002 1.0 First Issue 07-Feb-2002 2.0 TSOP28 Package Order Code clarified 08-Feb-2002 3.0 AC Measurement Load Circuit clarified (Figure 8) 06-Mar-2002 4.0 Document status changed to Data Sheet 5.0 Absolute Maximum Ratings table clarified (Table 3) Operating and AC Measurement Conditions table clarified (Table 4) DC Characteristics table clarified (Table 6) Low VCC Data Retention AC Waveforms and Characteristics table clarified (Figure 14, Table 4) 01-Jun-2002 6.0 TSOP28 8x13.4mm Standard pinout added (Figure 5, Table 12) Block Diagram clarified (Figure 6) TA clarified in Absolute Maximum Ratings (Table 3) Operating and AC Measurement Conditions table clarified (Table 4) ICC2 Max added in DC Characteristics (Table 6) tPD, tPU clarified in Read and Standby Mode AC Characteristics (Table 7) tWLEH, tWLWH clarified in Write Mode AC Characteristics (Table 8) 09-Sep-2002 6.1 Load Capacitance (CL) changed from 100pF to 30pF (Table 4) 02-Oct-2002 6.2 New part number added. 09-Oct-2002 6.3 Part number modified. 22-May-2003 6.4 Temperature range 1 added to Ordering Information Scheme. TSOP pin numbering corrected 02-Jul-2003 6.5 Value of ISB(typ) changed in DC Characteristics table 6.6 SO28 package modified. Part numbering scheme updated. TLEAD parameter added in Table 3, Absolute Maximum Ratings. AC, DC Characteristics and waveforms grouped together. tPD maximum value and tPU minimum value updated in Table 7, Read and Standby Mode AC Characteristics. 20-May-2002 25-Nov-2003 18/19 Revision Details M68AW031A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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