M7010R-066ZA1T

M7010R 16K x 68-bit Entry NETWORK SEARCH ENGINE FEATURES SUMMARY s 16K ENTRIES IN 68-BIT MODE s Figure 1. 272-ball PBGA Package s TABLE MAY BE PARTITIONED INTO UP TO FOUR (4) QUADRANTS (Data entry width in each quadrant is configurable as 34, 68, 136, or 272 bits.) UP TO 83 MILLION SUSTAINED SEARCHES PER SECOND IN 68-BIT and 136-BIT CONFIGURATIONS UP TO 41.5 MILLION SEARCHES PER SECOND IN 34-BIT and 272-BIT CONFIGURATIONS SEARCHES ANY SUB-FIELD IN A SINGLE CYCLE OFFERS BIT-BY-BIT and GLOBAL MASKING SYNCHRONOUS, PIPELINED OPERATION UP TO 31 SEARCH ENGINES CASCADABLE WITHOUT PERFORMANCE DEGRADATION WHEN CASCADED, THE DATABASE ENTRIES CAN SCALE FROM 124K to 992K DEPENDING ON THE SIZE OF THE ENTRY GLUELESS INTERFACE TO INDUSTRYSTANDARD SRAMS SIMPLE HARDWARE INSTRUCTION INTERFACE IEEE 1149.1 TEST ACCESS PORT OPERATING SUPPLY VOLTAGES INCLUDE: VDD (Operating Supply Voltage) = 1.8V VDDQ (Operating Supply Voltage for I/O) = 2.5 or 3.3V 272 BALL, 27mm x 27mm, CAVITY-UP BGA 272 PBGA 27mm x 27mm 1.27mm ball pitch s s s s s s s s s s s July 2002 1/67 M7010R TABLE OF CONTENTS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Range (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch/Router Implementation Using the M7010R (Figure 2.) . . . . . Signal Names (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M7010R Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... .....6 .....6 .....6 .....6 .....6 .....7 .....8 .....9 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute Maximum Ratings (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC and AC Measurement Conditions (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 M7010R 2.5V AC Testing Load (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 M7010R 2.5V Input Waveform (Figure 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 M7010R 2.5V Output Load Equiv. (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 M7010R 3.3V AC Testing Load (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 M7010R 3.3V Input Waveform (Figure 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 M7010R 3.3V Output Load Equiv. (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Capacitance (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC Timing Waveforms with CLK2X (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC Timing Parameters with CLK2X (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Command Bus and DQ Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Database Entry (Data Array and Mask Array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Arbitration Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pipeline and SRAM Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Full Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Connections Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/67 M7010R CLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Clocks (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Register Overview (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Comparand Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Comparand Register Selection During SEARCH and LEARN (Figure 13.). . . . . . . . . . . . . . . . . . . 19 Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Addressing the Global Mask Register (GMR) Array (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SEARCH-Successful Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SEARCH-Successful Register (SSR) Description (Table 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 The Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Command Register Field Descriptions (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SEARCH PROCEDURE FOR 32-BIT WIDE PREFIXES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Global Mask Register Patterns (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Storing left half of a Data or Mask Array (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 The Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Information Register Field Descriptions (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 The READ Burst Address Register (RBURREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 READ Burst Register Description (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 The WRITE Burst Address Register (WBURREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 WRITE Burst Register Description (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 The NFA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 NFA Register (Table 14.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SEARCH ENGINE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data and Mask Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 M7010R Database Configuration (Figure 17.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Bit Position Match (Table 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Multi-width Configuration Example (Figure 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 M7010R Data and Mask Array Addressing (Figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 COMMAND CODES AND PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Commands and Command Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Command Codes (Table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Command Parameters (Table 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 READ COMMAND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Single Location READ Cycle Timing (Figure 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Burst READ of the Data and Mask Arrays (BLEN = 4) (Figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . 29 READ Command Parameters (Table 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Data and Mask Array, SRAM READ Address Format (Table 19.) . . . . . . . . . . . . . . . . . . . . . . . . . 30 READ Address Format for Internal Registers (Table 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 READ Address Format for Data and Mask Arrays (Table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3/67 M7010R WRITE COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Single Location WRITE Cycle Timing (Figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Burst WRITE of the Data and Mask Arrays (BLEN = 4) (Figure 23.). . . . . . . . . . . . . . . . . . . . . . . . 32 (Single) WRITE Address Format for Data and Mask Arrays or SRAM (Table 22.) . . . . . . . . . . . . . 33 WRITE Address Format for Internal Registers (Table 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 WRITE Address Format for Data and Mask Array (Burst WRITE) (Table 24.) . . . . . . . . . . . . . . . . 33 SEARCH COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 68-bit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Hardware Diagram for a Table with a Single Device (68-bit Operation) (Figure 24.) . . . . . . . . . . . 34 68-Bit Configuration SEARCH Timing Diagram (One Device) (Figure 25.). . . . . . . . . . . . . . . . . . . 35 Right-Shift of 68-bit Signals for TLSZ Values (Table 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Shift of SSF and SSV from SADR (for different HLAT Values) (Table 26.) . . . . . . . . . . . . . . . . . . . 36 Latency of SEARCH from Instruction to SRAM Access Cycle (68-bit Mode) (Table 27.) . . . . . . . . 36 68-bit Logical SEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 x68 Table with One Device (Figure 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 136-bit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Hardware Diagram for a Table with One Device (136-bit Operation) (Figure 27.) . . . . . . . . . . . . . 38 136-Bit Configuration SEARCH Timing Diagram (One Device) (Figure 28.). . . . . . . . . . . . . . . . . . 39 Right-Shift of 136-bit Signals for TLSZ Values (Table 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Shift of SSF and SSV from SADR (for different HLAT values) (Table 29.) . . . . . . . . . . . . . . . . . . . 40 Latency of SEARCH from Instruction to SRAM Access Cycle (136-bit Mode) (Table 30.) . . . . . . . 40 136-bit Logical SEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 x136 Table with One Device (Figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 272-bit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Hardware Diagram for a Table with One Device (272-bit Operation) (Figure 30.) . . . . . . . . . . . . . 42 272-Bit Configuration SEARCH Timing Diagram (One Device) (Figure 31.). . . . . . . . . . . . . . . . . . 43 Right-Shift of 272-bit Signals for TLSZ Values (Table 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Shift of SSF and SSV from SADR (for different HLAT Values) (Table 32.) . . . . . . . . . . . . . . . . . . . 44 Latency of SEARCH from Instruction to SRAM Access Cycle (272-bit Mode) (Table 33.) . . . . . . . 44 272-bit Logical SEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 x272 Table with One Device (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Mixed-sized Searches on Tables Configured with Different Width Using an M7010R Device 46 Multiwidth Configuration Example (Figure 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Timing Diagram for Mixed SEARCH (One Device) (Figure 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 LRAM and LDEV Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 LEARN COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 LEARN Command Timing Diagram (TLSZ = 00) (Figure 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 LEARN Timing Diagram (TLSZ = 1, except on Last Device) (Figure 36.) . . . . . . . . . . . . . . . . . . . . 50 LEARN Timing Diagram on Device Number 7 (TLSZ = 01) (Figure 37.). . . . . . . . . . . . . . . . . . . . . 51 SRAM WRITE Cycle Latency from Second Cycle of LEARN Instruction (Table 34.) . . . . . . . . . . . 51 4/67 M7010R DEPTH-CASCADING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Depth-Cascading Up to Eight Devices (One Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Depth-Cascading Up to 31 Devices (4 Blocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Depth-Cascading to Generate a “FULL” State for a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Depth-Cascading to Form a Single Block (8 Devices) (Figure 38.) . . . . . . . . . . . . . . . . . . . . . . . . . 53 Four Blocks (31 Devices Cascaded) SEARCH, 68-bit Configured with LDEV = 1 (Figure 39.) . . . 54 “FULL” State Generation in a Cascaded Table (Figure 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Timing Diagram for Arbitration Within a Block (Figure 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Timing for Arbitration for Two or More Blocks for the Last Device (Figure 42.). . . . . . . . . . . . . . . . 57 SRAM ADDRESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 SRAM PIO Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 SRAM READ Access for One M7010R Device (Figure 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 SRAM WRITE Access for One M7010R Device (Figure 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 SRAM Bus Address Generation (Table 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Right-Shift of SRAM Signals for TLSZ Values (Table 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Right-Shift of SRAM Signals for HLAT Values (Table 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 JTAG (1149.1) TESTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Test Access Port Controller Instructions (Table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 TAP Device ID Register (Table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 POWER DISTRIBUTION GUIDELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Network Search Engine Power Distribution (Figure 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5/67 M7010R DESCRIPTION Overview The M7010R is a feature-rich, TCAM-based hardware search engine optimized for networking and communications applications. It incorporates leading-edge Associative Processing Technology (APT, trademark of Cypress Semiconductor, Inc.) and Advanced Power Management. The data table may be partitioned into up to four (4) quadrants, allowing the user to configure each quadrant with different table entry widths (x34, x68, x136, or x272-bit). It is also programmable to accelerate performance. Performance The M7010R outperforms competitive solutions using software sequential search algorithms in conjunction with SRAMs or ASICs, or hardware implementation with ASICs and CAMs. The latter solution, while faster than a software-based soluTable 1. Product Range Part Number M7010R-083ZA1 M7010R-066ZA1 Operating Supply Voltage 1.8V 1.8V Operating I/O Voltage 2.5 or 3.3V 2.5 or 3.3V Speed 83MHz 66MHz tion, still suffers from performance degradation when depth-cascaded and is unable to scale to next-generation requirements. The M7010Rbased solutions overcome all of these drawbacks. Applications The performance and features of the M7010R makes it ideal in applications such as enterprise LAN switches, broadband switching and routing equipment, supporting multiple data rates from OC–48 and beyond. Figure 2 illustrates how a search engine subsystem can be optimized using a host bridge ASIC, the M7010R, and synchronous or non-synchronous SRAMs. It also illustrates how this system fits into a switch-router implementation. Figure 2. Switch/Router Implementation Using the M7010R Sys tem Bus m Progra ry Memo Host ASIC Switch Fabric h Searc e Engin SRAM Bank Ne two rk L ine Inte Switch or rocess P rfac es AI04272 6/67 M7010R Table 2. Signal Names Symbol Type Connection Name LHI[6:0] LHO[1:0] BHI[2:0] BHO[2:0] FULI[6:0] FULO[1:0] FULL Cascade Interface I O I O I O O Local Hit In Local Hit Out Block Hit In Block Hit Out Full In Full Out Full Flag Clocks and Reset CLK2X PHS_L RST_L I I I Master Clock Phase Reset Command and DQ Bus CMD[8:0] CMDV DQ[67:0] ACK(1) EOT(1) SSF SSV SADR[21:0] CE_L WE_L OE_L ALE_L I I I/O T T T T T T T T T Command Bus Command Valid Address/Data Bus READ Acknowledge End of Transfer SEARCH Successful Flag SEARCH Successful Flag Valid SRAM Address SRAM Chip Enable SRAM WRITE Enable SRAM Output Enable Address Latch Enable Device Identification ID[4:0] I Device Identification Test Access Port TDI TCK TDO TMS TRST_L I I T I I Test Access Port’s Test Data In Test Access Port’s Test Clock Test Access Port’s Test Data Out Test Access Port’s Test Mode Select Test Access Port’s Reset Note: Signal types are: I = Input only; I/O = Input or Output; O = Output; and T = Tristate 1. ACK and EOT Signals require a pull-down resistor of 47 ohms. 7/67 M7010R Figure 3. Connections NC NC DQ64 DQ62 GND NC NC NC EOT ACK NC VDD NC NC FULL NC NC VDD FULI5 FULI4 FULI1 BHO0 VDD FULO1 NC NC BHI0 LHI6 NC LHI3 VDD LHI2 ID2 ID0 TMS TCK TDO TDI NC NC VDD NC NC NC DQ65 FULI6 FULI2 BHO1 BHI2 VDDQ LHI5 NC VDDQ BHO2 VDD LHO1 ID3 ID1 VDDQ VDD VDDQ GND RSTL DQ66 LHI4 VDDQ LHI0 LHI1 ID4 NC FULO0 GND FULI3 FULI0 BHI1 LHO0 GND TOP T RST_L GND DQ63 DQ61 DQ57 NC DQ53 DQ60 VDDQ VDD NC DQ67 DQ59 DQ56 DQ58 VDDQ DQ55 DQ49 VDD DQ47 VDDQ DQ51 VDDQ GND GND GND GND GND GND GND RIGHT GND GND GND GND GND GND VDDQ NC NC DQ29 VDD NC DQ45 DQ43 DQ50 VDDQ DQ52 DQ54 NC DQ46 DQ48 GND DQ40 DQ42 VDDQ DQ44 VDD NC DQ36 DQ38 LEFT VDDQ DQ34 DQ32 DQ30 NC DQ28 VDDQ DQ26 DQ20 GND DQ41 DQ39 VDD DQ37 VDDQ DQ35 DQ33 DQ31 GND GND GND GND DQ23 DQ25 DQ27 DQ24 VDD GND DQ19 VDDQ DQ21 VDDQ NC DQ15 DQ17 DQ22 DQ16 DQ14 VDDQ VDD DQ18 VDDQ DQ6 NC DQ10 DQ2 NC NC DQ12 DQ8 NC DQ4 NC NC DQ0 NC BOTTOM DQ9 DQ11 DQ13 VDD DQ1 DQ5 NC DQ7 NC NC VDDQ DQ3 NC NC VDDQ GND VDD NC SADR SADR V GND VDDQ CMD4 CMD2 GND WE_L CLK2X VDD 15 DDQ GND 5 SADR SADR SADR SADR SADR SADR SADR NC 21 18 6 16 9 7 12 SADR V DDQ 19 NC SADR SADR NC 10 11 SSF CMD6 CMD3 CMD0 AE_L OE_L SADR V DD 0 NC SSV CMD5 CMD1 CMDV VDDQ PHS_L VDDQ NC CE_L NC SADR SADR 4 3 CMD8 CMD7 VDDQ VDD VDD SADR SADR SADR SADR VDD SADR VDDQ SADR SADR 2 1 20 14 8 17 13 AI04270 Note: This diagram is TOP VIEW perspective (view through package). 8/67 M7010R Figure 4. M7010R Block Diagram PHS_L CLK2X RST_L Comparand Registers[15:0] Global Mask Registers [7:0] Information and Command Register Burst Read Register Burst Write Register Next Free Address Register Search Successful Index Registers [7:0] (All registers are 68-bit-wide) TAP Controller TAP DQ [67:0] Compare/PIO Data Cmd Compare/PIO Data Address Decode CMD [8:0] CMDV ACK EOT Priority Encode Match Logic Command Decode and PIO Access Configurable as 32K x 34 16K x 68 8K x 136 4K x 272 Data Array Configurable as 32K x 34 16K x 68 8K x 136 4K x 272 Mask Array SADR [21:0] Pipeline and SRAM Control OE_L WE_L CE_L ALE_L ID [4:0] FULL [6:0] Full Logic FULL LHI [6:0] BHI [2:0] Arbitration Logic FULO [1:0] LHO [1:0] BHO [2:0] SSF SSV AI04273 9/67 M7010R MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 3. Absolute Maximum Ratings Symbol TSTG TSLD (1) VDDQ VDD IO PD Parameter Storage Temperature (VDD Off) Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation Value –0 to 70 235 3.3 –0.4 to 2.7 100