M74HC112C1R

M 54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS112 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC112F1R M74HC112M1R M74HC112B1R M74HC112C1R DESCRIPTION The M54/74HC112 is a high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The M54HC112/M74HC112 dual JK flip-flop features individual J,K, clock, and asynchronous set and clearinputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is high and the bistable will function as shown in the truth table. Input data is transferred to the input on the negative going edge of the clock pulse. All inputs are equipped withprotection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection October 1992 1/11 M54/M74HC112 TRUTH TABLE INPUTS CLR L H L H H H H H X: Don’t Care OUTPUTS K X X X L L H H X CK X X X Q L H H Qn H L Qn Qn Q H L H Qn L H Qn Qn PR H L L H H H H H J X X X L H L H X FUNCTION CLEAR PRESET NO CHANGE TOGGLE NO CHANGE P IN DESCRIPTION PIN No 1, 13 2, 12 3, 11 4, 10 5, 9 6, 7 15, 14 8 16 SYMBOL 1CK, 2CK 1K, 2K 1J, 2J 1PR, 2PR 1Q, 2Q 1Q, 2Q 1CLR, 2CLR GND V CC NAME AND FUNCTION Clock Input (HIGH to LOW edge triggered) Data Inputs: Flip-Flop 1 and 2 Data Inputs: Flip-Flop 1 and 2 Set Inputs True Flip-Flop Outputs Complement Flip-Flop Outputs Reset inputs Ground (0V) Positive Supply Voltage IEC LOGIC SYMBOL LOGIC DIAGRAM (1/2 Package) 2/11 M54/M74HC112 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO ICC or IGND PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source Sink Current Per Output Pin DC VCC or Ground Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 25 ± 50 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mW o o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied. (*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC R ECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top tr, tf Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature: M54HC Series M74HC Series Input Rise and Fall Time Value 2 to 6 0 to VCC 0 to VCC -55 to +125 -40 to +85 0 to 1000 0 to 500 0 to 400 Unit V V V C o C ns o VCC = 2 V VCC = 4.5 V VCC = 6 V 3/11 M54/M74HC112 D C SPECIFICATIONS Test Conditions Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 V OH High Level Output Voltage 2.0 4.5 6.0 4.5 VOL Low Level Output Voltage 6.0 2.0 4.5 6.0 4.5 6.0 II ICC Input Leakage Current Quiescent Supply Current 6.0 6.0 VI = IO=-20 µA VIH or V IL IO=-4.0 mA IO=-5.2 mA VI = IO= 20 µA VIH or V IL IO= 4.0 mA IO= 5.2 mA VI = VCC or GND VI = VCC or GND 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 ±0.1 2 TA = 25 C 54HC and 74HC Min. Typ. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 ±1 20 o Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 ±1 40 µA µA V V 1.5 3.15 4.2 0.5 1.35 1.8 V V Unit VIH High Level Input Voltage Low Level Input Voltage V IL 4/11 M54/M74HC112 A C ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns) Test Conditions Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 tREM Minimum Removal Time (CLR, PR) Input Capacitance Power Dissipation Capacitance 2.0 4.5 6.0 24 4 3 5 33 8 40 47 TA = 25 C 54HC and 74HC Min. Typ. Max. 30 8 7 52 16 14 68 17 14 16 68 79 20 5 4 20 5 4 28 7 6 75 15 13 75 15 13 75 15 13 0 0 0 50 10 9 10 75 15 13 125 25 21 135 27 23 6.4 32 38 95 19 16 95 19 16 95 19 16 0 0 0 60 12 10 10 o Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 95 19 16 155 31 26 170 34 29 5.4 27 32 110 22 19 110 22 19 110 22 19 0 0 0 70 14 12 10 pF pF ns ns ns ns MHz 110 22 19 190 38 32 205 41 35 ns ns ns Unit tTLH tTHL tPLH tPHL tPLH tPHL fMAX Output Transition Time Propagation Delay Time (CK - Q, Q) Propagation Delay Time (CLR, PR - Q, Q) Maximum Clock Frequency Minimum Pulse Width (CLOCK) Minimum Pulse Width (CLR, PR) Minimum Set-up Time Minimum Hold Time tW(H) tW(L) tW(L) ts th ns CIN CPD (*) (*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/2 (per FLIP/FLOP) 5/11 M54/M74HC112 SWITCHING CHARACTERISTICS TEST WAVEFORM TEST CIRCUIT (Opr.) INPUT TRANSITION TIME IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICS TEST 6/11 M54/M74HC112 Plastic DIP16 (0.25) MECHANICAL DATA mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX. DIM. P001C 7/11 M54/M74HC112 Ceramic DIP16/1 MECHANICAL DATA mm MIN. A B D E e3 F G H L M N P Q 7.8 2.29 0.4 1.17 0.22 0.51 0.38 17.78 2.79 0.55 1.52 0.31 1.27 10.3 8.05 5.08 0.307 0.090 0.016 0.046 0.009 0.020 3.3 0.015 0.700 0.110 0.022 0.060 0.012 0.050 0.406 0.317 0.200 TYP. MAX. 20 7 0.130 MIN. inch TYP. MAX. 0.787 0.276 DIM. P053D 8/11 M54/M74HC112 SO16 (Narrow) MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8° (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45° (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 P013H 9/11 M54/M74HC112 PLCC20 MECHANICAL DATA mm MIN. A B D d1 d2 E e e3 F G M M1 1.27 1.14 7.37 1.27 5.08 0.38 0.101 0.050 0.045 9.78 8.89 4.2 2.54 0.56 8.38 0.290 0.050 0.200 0.015 0.004 TYP. MAX. 10.03 9.04 4.57 MIN. 0.385 0.350 0.165 0.100 0.022 0.330 inch TYP. MAX. 0.395 0.356 0.180 DIM. P027A 10/11 M54/M74HC112 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A 11/11