M74HC165M1R

M74HC165 8 BIT PISO SHIFT REGISTER s s s s s s s HIGH SPEED : tPD = 15ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 165 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC165B1R M74HC165M1R T&R M74HC165RM13TR M74HC165TTR DESCRIPTION The M74HC165 is an high speed CMOS 8 BIT PISO SHIFT REGISTER fabricated with silicon gate C2MOS technology. This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide over-riding asynchronous parallel entry. Parallel data enters when the shift/load input is low. The parallel data can change while shift/load is low, provided that the recommended set-up and hold times are observed. For clocked operation, shift/load must be high. The two clock input perform identically; one can be used as a clock inhibit by applying a high signal; to permit this operation clocking is accomplished through a 2 input nor gate. To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise the rising inhibit signal will cause the same response as rising clock edge. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12 M74HC165 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2 7 9 SYMBOL NAME AND FUNCTION 10 11, 12, 13, A to H 14, 3, 4, 5, 6 15 CLOCK INH 8 GND 16 Vcc SHIFT/LOAD Data Inputs Complementary Output QH QH Serial Output Clock Input (LOW to CLOCK HIGH, Edge Triggered SI Serial Data Inputs Parallel Data Inputs Clock Inhibit Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS SHIFT / LOAD L H H H H H H X H CLOCK INH X L L L L H X CLOCK X SI X H L H L X X A..........H a..........h X X X X X X INTERNAL OUTPUTS QA a H L H L QB b QAn QAn QAn QAn NO CHANGE NO CHANGE OUTPUTS QH h QGn QGn QGn QGn a........h : The level of steady input voltage at inputs a through respectively QAn - QGn : The level of QA - QG, respectively. before the most-recent transition of the clock LOGIC DIAGRAM 2/12 M74HC165 TIMING CHART ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 25 ± 50 500(*) -65 to +150 300 Unit V V V mA mA mA mA mW °C °C ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg TL Storage Temperature Lead Temperature (10 sec) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C 3/12 M74HC165 RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2.0V VCC = 4.5V VCC = 6.0V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 0 to 1000 0 to 500 0 to 400 Unit V V V °C ns ns ns DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage 2.0 4.5 6.0 4.5 6.0 II ICC Input Leakage Current Quiescent Supply Current 6.0 6.0 IO=-20 µA IO=-20 µA IO=-20 µA IO=-4.0 mA IO=-5.2 mA IO=20 µA IO=20 µA IO=20 µA IO=4.0 mA IO=5.2 mA VI = VCC or GND VI = VCC or GND TA = 25°C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 ± 0.1 4 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 ±1 40 Typ. Max. Value -40 to 85°C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 ±1 80 µA µA V V Max. -55 to 125°C Min. 1.5 3.15 4.2 0.5 1.35 1.8 Max. V Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL V VOH 4/12 M74HC165 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 20 5 4 TA = 25°C Min. Typ. 30 8 7 55 18 15 65 21 18 52 17 14 15 60 71 24 6 5 32 8 7 24 6 5 Max. 75 15 13 150 30 26 165 33 28 135 27 23 6.0 30 35 75 15 13 75 15 13 75 15 13 0 0 0 75 15 13 95 19 16 95 19 16 95 19 16 0 0 0 95 19 16 Value -40 to 85°C Min. Max. 95 19 16 190 38 33 205 41 35 170 34 29 4.8 24 28 110 22 19 110 22 19 110 22 19 0 0 0 110 22 19 -55 to 125°C Min. Max. 110 22 19 225 45 38 250 50 43 205 41 35 ns ns ns Unit tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CLOCK - QH, QH) tPLH tPHL Propagation Delay Time (SHIFT/LOAD QH, QH) tPLH tPHL Propagation Delay Time (H - QH, QH) fMAX Maximum Clock Frequency Minimum Pulse Width (CLOCK) Minimum Pulse Width (SHIFT/LOAD) Minimum Set-up Time (PI - SHIFT/LOAD) (SI - CLOCK) (SHIFT/LOAD - CK) Minimum Hold Time (PI - SHIFT/LOAD) (SI - CLOCK) (SHIFT/LOAD - CK) Minimum Removal Time (CLOCK - CK INH) ns 7.4 37 44 MHz tW(H) tW(L) tW(L) ns ns ts ns th ns tREM ns CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) 5.0 5.0 TA = 25°C Min. Typ. 5 55 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF Unit CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC 5/12 M74HC165 TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: SERIAL MODE PROPAGATION DELAY (f=1MHz; 50% duty cycle) 6/12 M74HC165 WAVEFORM 2: PARALLEL MODE PROPAGATION DELAY (f=1MHz; 50% duty cycle) W AVEFORM 3: MINIMUM PULSE WIDTH (S/L), PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) 7/12 M74HC165 WAVEFORM 4: SETUP AND HOLD TIME (PI TO S/L) (f=1MHz; 50% duty cycle) W AVEFORM 5: MINIMUM REMOVAL TIME (CK INH TO CK) (f=1MHz; 50% duty cycle) 8/12 M74HC165 Plastic DIP-16 (0.25) MECHANICAL DATA mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch P001C 9/12 M74HC165 SO-16 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8° (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45° (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 PO13H 10/12 M74HC165 TSSOP16 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0° 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8° 0.75 0° 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8° 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 11/12 M74HC165 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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