M74HC173RM13TR

M74HC173 QUAD D-TYPE REGISTER (3 STATE) ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 84MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL =6mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 173 DESCRIPTION The M74HC173 is an high speed CMOS QUAD D-TYPE REGISTER (3-STATE) fabricated with silicon gate C2MOS technology. This device is composed of a four-bit register including D-TYPE flip-flops and 3-state buffers. The four flip-flops are controlled by a common clock input (CLOCK) and a common reset input (CLEAR). Signals applied to the data inputs (D1 D4) are stored at the respective flip-flops on the positive going transition of the clock input, only DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP M74HC173B1R M74HC173M1R T&R M74HC173RM13TR M74HC173TTR when both clock control inputs (G1 and G2) are held low. The reset feature is asynchronous and active high. The stored data are provided on each output only when both output control inputs (M and N) are held low, otherwise the outputs go to the high-impedance state. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12 M74HC173 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 2 M, N 3, 4, 5, 6 7 1Q to 4Q CLOCK 9, 10 G1, G2 14, 13, 12, 11 15 1D to 4D Output Enable Input (Active Low) 3-State Flip-Flop Outputs Clock Input (Low to HIGH, Edge-triggered) Data Enable Inputs (Active Low) Data Inputs 8 16 GND VCC CLEAR Asynchronous Master Reset (Active High) Ground (0V) Positive Supply Voltage TRUTH TABLE DATA ENABLE CLEAR OUTPUT CONTROL Dn G1 G2 X X X X X X L X L Qn M N X X X H X L X H L Z Z L X X L L Q0 H X X L L Q0 L X H X L L Q0 L L L H L L H L L L L L L L X X H X : Don’t Care Z : High Impedance 2/12 CLOCK X X X M74HC173 LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage IIK DC Input Diode Current -0.5 to VCC + 0.5 ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 35 mA ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) V ± 70 mA 500(*) mW -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C 3/12 M74HC173 RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Value Supply Voltage VI Input Voltage VO Output Voltage Top Operating Temperature Input Rise and Fall Time tr, tf Unit 2 to 6 V 0 to VCC V 0 to VCC V -55 to 125 °C VCC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOL II IOZ ICC 4/12 Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 4.5 6.0 2.0 4.5 6.0 Typ. Max. 1.5 3.15 4.2 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 Max. 1.5 3.15 4.2 0.5 1.35 1.8 Unit V 0.5 1.35 1.8 2.0 IO=-20 µA 1.9 2.0 1.9 1.9 4.5 IO=-20 µA 4.4 4.5 4.4 4.4 6.0 IO=-20 µA 5.9 6.0 5.9 5.9 4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10 6.0 IO=-5.2 mA 5.68 5.8 5.63 5.60 2.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=20 µA 0.0 0.1 0.1 0.1 V V 6.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=4.0 mA 0.17 0.26 0.33 0.40 6.0 IO=5.2 mA 0.18 0.26 0.33 0.40 6.0 VI = VCC or GND ± 0.1 ±1 ±1 µA 6.0 VI = VIH or VIL VO = VCC or GND ± 0.5 ± 5.0 ± 10 µA 6.0 VI = VCC or GND 4 40 80 µA V M74HC173 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CLOCK - Q) tPLH tPHL Propagation Delay Time (CLEAR - Q) fMAX Maximum Clock Frequency tPZL tPZH Output Enable Time tPLZ tPHZ Output Disable Time tW(H) tW(L) Minimum Pulse Width (CLOCK) tW(L) Minimum Pulse Width (CLEAR) ts ts th tREM Minimum Set-up Time (G1, G2) Minimum Set-up Time (D) Minimum Hold Time (G1 ,G2, D) Minimum Removal Time VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Value TA = 25°C CL (pF) Min. 50 50 150 50 150 8.6 43 51 50 50 RL = 1 KΩ 150 RL = 1 KΩ 50 RL = 1 KΩ 50 50 50 50 50 50 Typ. Max. 25 7 6 50 14 12 65 18 15 50 14 12 65 18 15 20 67 84 50 14 12 65 18 15 36 15 13 16 4 3 16 4 3 40 10 9 24 6 5 60 12 10 115 23 20 145 29 25 115 23 20 145 29 25 -40 to 85°C -55 to 125°C Min. Min. Max. 75 15 13 145 29 25 180 36 31 145 29 25 180 36 31 6.8 34 40 115 23 20 145 29 25 105 21 18 75 15 13 75 15 13 100 20 17 75 15 13 0 0 0 5 5 5 Max. 90 18 15 175 35 30 220 44 37 175 35 30 220 44 37 5.8 29 34 145 29 25 180 36 31 130 26 22 95 19 16 95 19 16 125 25 21 95 19 16 0 0 0 5 5 5 Unit ns ns ns ns ns MHz 175 35 30 220 44 37 160 32 27 110 22 19 110 22 19 150 30 26 110 22 19 0 0 0 5 5 5 ns ns ns ns ns ns ns ns ns 5/12 M74HC173 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter Value TA = 25°C VCC (V) Min. Typ. Max. 10 CIN Input Capacitance 5.0 5 CPD Power Dissipation Capacitance (note 1) 5.0 50 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 10 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (Per Circuit) TEST CIRCUIT TEST tPLH, tPHL SWITCH Open tPZL, tPLZ VCC tPZH, tPHZ GND CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) 6/12 M74HC173 WAVEFORM 1: PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CLOCK), SETUP AND HOLD TIME (Dn TO CLOCK) (f=1MHz; 50% duty cycle) WAVEFORM 2: MINIMUM PULSE WIDTH (CLEAR) AN DREMOVAL TIME (CLEAR TO CLOCK) (f=1MHz; 50% duty cycle) 7/12 M74HC173 WAVEFORM 3: OUTPUT ENABLE AND DISABLE TIME(f=1MHz; 50% duty cycle) WAVEFORM 4: INPUT WAVEFORMS(f=1MHz; 50% duty cycle) 8/12 M74HC173 Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 9/12 M74HC173 SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8° (max.) PO13H 10/12 M74HC173 TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.60 0.0256 BSC 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 11/12 M74HC173 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 12/12