M74HC181

M 74HC181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR . . . . . . . . HIGH SPEED tPD = 13 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) at TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS181 B1R (Plastic Package) M1R (Micro Package) ORDER CODES : M74HC181M1R M74HC181B1R DESCRIPTION The 74HC181 is a high speed CMOS ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR fabricated with silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. These circuits perform 16 binary arithmetic operations on two 4-bit words as shown in tables 1 and 2. These operations are selected by the four function-select lines (S0, S1, S2, S3) and include addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries must be enabled by applying a low-level voltage to the mode control input (M). A full carry look-ahead scheme is made available in these devices for fast, simultaneous carry generation by means of two cascade-outputs (pins 15 and 17) for the four bits in the package. When used in conjunction with the M54HC182 or M74HC182, full carry look-ahead circuits, high-speed arithmetic operations can be performed. These circuits will accomodate active-high or active-low data, if the pin designations are interpreted as shown below. Subtraction is accomplished by 1,s complement addition where the 1’s complement of the subtrahend is generated internally. The resultant output is 1–B–1, which requires an endaround or forced carry to produce A–B. The 181 can also be utilized as a comparator. The A = B output is internally decoded from the function outputs (F0, F1, F2, F3) so that when two words of equal magnitude are applied at the A and B inputs, it will assume a high level to indicated equality (A = B). The ALU should be October 1993 PIN CONNECTIONS (top view) * Open drain Output Structure 1/13 M74HC181 D ESCRIPTION (continued) in the subtract mode with Cn = H when performing this comparison. The A = B output is open-drain so that it can be wire-AND connected to give a comparison for more that four bits. The carry output (Cn + 4) can also be used to supply relative magnitude information. Again, the ALU should be placed in the subtract mode by placing the function select inputs S3, S2, S1, S0 at L, H, H, L, respectively. These circuits have been designed to not only incorporate all of the designer’s reINPUT AND OUTPUT EQUIVALENT CIRCUITS quirements for arithmetic operations, but also to provide 16 possible functions of two Boolean variables without the use of external circuitry. These logic functions are selected by use of the four function-select inputs (S0, S1, S2, S3) with the mode-control input (M) at a high level to disable the internal carry. All inputs are equipped with protection circuits against static discharge and transient excess voltage. ONLY OUTPUT A = B IEC LOGIC SYMBOLS PIN DESCRIPTION PIN No 2, 23, 21, 19 1, 22, 20, 18 6, 5, 4, 3 7 8 9, 10, 11, 13 14 15 16 17 12 24 SYMBOL A0 to A3 B0 to B3 S0 to S3 Cn M F0 to F3 A=B P Cn + 4 G GND VCC 9 F0 F0 10 F1 F1 11 F2 F2 13 F3 F3 NAME AND FUNCTION Word A Inputs Word B Inputs Function Select Inputs Inv. Carry Input Mode Control Input Function Outputs Comparator Output Carry Propagate Output Inv. Carry Output Carry Generate Output Ground (0V) Positive Supply Voltage 7 Cn Cn 16 Cn + 4 Cn + 4 15 P X 17 G Y PIN NUMBER ACTIVE LOW DATA (Table 1) 2 A0 1 B0 B0 23 A1 A1 22 B1 B1 21 A2 A2 20 B2 B2 19 A3 A3 18 B3 B3 ACTIVE HIGH DATA (Table 1) A0 Input Cn H H L L 2/13 Output Cn + 4 H L H L Active LOW Data (Figure 1) A≥B AB A≤B Active HIGH Data (Figure 2) A≤B A>B A