M74HC195C1R

M74HC195C1R

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

  • 描述:

    M74HC195C1R - 8 BIT PIPO SHIFT REGISTER - STMicroelectronics

  • 详情介绍
  • 数据手册
  • 价格&库存
M74HC195C1R 数据手册
M 54HC195 M74HC195 8 BIT PIPO SHIFT REGISTER . . . . . . . . HIGH SPEED tPD = 13 ns (TYP.) at VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) at TA = 25 °C 6 V HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS195 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC195F1R M74HC195M1R M74HC195B1R M74HC195C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC195 is a high speed CMOS 4 BIT PIPO SHIFT REGISTER fabricated in silicon gate 2 C MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This shift register features parallel inputs, parallel outputs, J-K serial inputs, a SHIFT/LOAD control input, and a direct overriding CLEAR. This shift register can operate in two modes : Parallel Load ; Shift from QA towards QD. Parallel loading is accomplished by applying the four bits of data, and taking the SHIFT/LOAD control input low. The data is loaded into the associated flip flops and appears at the outputs after the positive transition of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the SHIFT/LOAD control input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K or TOGGLE flip flop as shown in the truthtable. All inputs are equipped with protection circuits against static discharge transient excess voltage. October 1992 NC = No Internal Connection 1/13 M54/M74HC195 I NPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2 3 4, 5, 6, 7 9 10 11 15, 14, 13, 12 8 16 SYMBOL CLEAR J K NAME AND FUNCTION Reset Input (Active LOW) First Stage J Input (Active LOW) First Stage K Input (Active LOW) IEC LOGIC SYMBOL A to D Parallel Data Input SHIFT/LOAD Control Input CLOCK QD QA to QD GND VCC Clock Input (LOW to HIGH Edge-triggered) Inverted Output From The Last Stage Paralle Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE CLEAR SHIFT/ LOAD L H H H H H H X L H H H H H INPUTS SERIAL J X X X X L L H H K X X X H L H L A X a X X X X X OUTPUS PARALLEL B X b X X X X X C X c X X X X X D X d X X X X X L a QA0 QA0 L H QAn L b QB0 QA0 QAn QAn QAn L c QC0 QBn QBn QBn QBn L d QD0 QCn QCn QCn QCn L d QD0 QCn QCn QCn QCn QA QB QC QD QD CLOCK X: Don’t Care: The level of QA, QB, QC, respectively, before the mst recent positive transition of the clock. 2/13 M54/M74HC195 LOGIC DIAGRAM 3/13 M54/M74HC195 TIMING CHART 4/13 M54/M74HC195 A BSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO ICC or IGND PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source Sink Current Per Output Pin DC VCC or Ground Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 25 ± 50 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mW o o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied. (*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top tr, tf Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature: M54HC Series M74HC Series Input Rise and Fall Time Value 2 to 6 0 to VCC 0 to VCC -55 to +125 -40 to +85 0 to 1000 0 to 500 0 to 400 Unit V V V C o C ns o VCC = 2 V VCC = 4.5 V VCC = 6 V 5/13 M54/M74HC195 D C SPECIFICATIONS Test Conditions Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 V OH High Level Output Voltage 2.0 4.5 6.0 4.5 VOL Low Level Output Voltage 6.0 2.0 4.5 6.0 4.5 6.0 II ICC Input Leakage Current Quiescent Supply Current 6.0 6.0 VI = IO=-20 µA VIH or V IL IO=-4.0 mA IO=-5.2 mA VI = IO= 20 µA VIH or V IL IO= 4.0 mA IO= 5.2 mA VI = VCC or GND VI = VCC or GND 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 ±0.1 4 TA = 25 oC 54HC and 74HC Min. Typ. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 ±1 40 Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 ±1 80 µA µA V V 1.5 3.15 4.2 0.5 1.35 1.8 V V Unit VIH High Level Input Voltage Low Level Input Voltage V IL 6/13 M54/M74HC195 A C ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns) Test Conditions Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 5 72 TA = 25 C 54HC and 74HC Min. Typ. 30 8 7 48 16 14 45 15 13 15 60 71 20 5 4 20 5 4 28 7 6 28 7 6 Max. 75 15 13 125 25 21 120 24 20 6 30 35 75 15 13 75 15 13 75 15 13 75 15 13 0 0 0 5 5 5 10 95 19 16 95 19 16 95 19 16 95 19 16 0 0 0 5 5 5 10 o Value -40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. 95 19 16 155 31 26 150 30 26 5 25 30 115 23 20 115 23 20 115 23 20 115 23 20 0 0 0 5 5 5 10 Min. Max. 115 23 20 190 38 32 180 36 31 Unit tTLH tTHL tPLH tPHL tPLH tPHL fMAX Output Transition Time Propagation Delay Time (CLOCK- Qn, QD) Propagation Delay Time (CLEAR- Qn, QD) Maximum Clock Frequency Minimum Pulse Width (CLOCK) Minimum Pulse Width (CLEAR) Minimum Set-up Time (PI) Minimum Set-up Time (J, K, S/L) Minimum Hold Time Minimum Removal Time Input Capacitance Power Dissipation Capacitance ns ns ns 7.6 38 45 MHz tW(H) tW(L) tW(L) ns ns ts ns ts ns th ns tREM ns pF pF CIN CPD (*) (*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC 7/13 M54/M74HC195 SWITCHING CHARACTERISTICS TEST WAVEFORM TEST CIRCUIT ICC (Opr.) TRANSITION TIME OF INPUT WAVEFORM IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICS TEST. 8/13 M54/M74HC195 Plastic DIP16 (0.25) MECHANICAL DATA mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX. DIM. P001C 9/13 M54/M74HC195 Ceramic DIP16/1 MECHANICAL DATA mm MIN. A B D E e3 F G H L M N P Q 7.8 2.29 0.4 1.17 0.22 0.51 0.38 17.78 2.79 0.55 1.52 0.31 1.27 10.3 8.05 5.08 0.307 0.090 0.016 0.046 0.009 0.020 3.3 0.015 0.700 0.110 0.022 0.060 0.012 0.050 0.406 0.317 0.200 TYP. MAX. 20 7 0.130 MIN. inch TYP. MAX. 0.787 0.276 DIM. P053D 10/13 M54/M74HC195 SO16 (Narrow) MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8° (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45° (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 P013H 11/13 M54/M74HC195 PLCC20 MECHANICAL DATA mm MIN. A B D d1 d2 E e e3 F G M M1 1.27 1.14 7.37 1.27 5.08 0.38 0.101 0.050 0.045 9.78 8.89 4.2 2.54 0.56 8.38 0.290 0.050 0.200 0.015 0.004 TYP. MAX. 10.03 9.04 4.57 MIN. 0.385 0.350 0.165 0.100 0.022 0.330 inch TYP. MAX. 0.395 0.356 0.180 DIM. P027A 12/13 M54/M74HC195 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A 13/13
M74HC195C1R
物料型号: - M54HC195F1R - M74HC195M1R - M74HC195B1R - M74HC195C1R

器件简介: M54/74HC195是一款高速CMOS 4位并行输入并行输出移位寄存器,采用硅门C2MOS技术制造。它结合了LSTTL的高速性能和真正的CMOS低功耗特性。该移位寄存器具有并行输入、并行输出、J-K串行输入、SHIFT/LOAD控制输入和直接清除功能。可以并行加载或从QA向QD方向移位。

引脚分配: 1. CLEAR:复位输入(低电平有效) 2. J:第一阶段J输入(低电平有效) 3. K:第一阶段K输入(低电平有效) 4-7. A-D:并行数据输入 9. SHIFT/LOAD:移位/加载控制输入 10. CLOCK:时钟输入(低到高边沿触发) 11. QD:最后阶段的反相输出 15-12. QA-QD:并行输出 8. GND:地(0V) 16. VCC:正供电电压

参数特性: - 工作电压范围:2V至6V - 典型功耗:4μA(最大值)在25°C时 - 输出驱动能力:可驱动10个LSTTL负载 - 对称输出阻抗:|IOH|=|IOL|=4mA(最小值) - 传播延迟平衡:tPLH=tPHL

功能详解: 该移位寄存器可以并行加载数据,也可以通过J-K输入进行串行移位。在并行加载模式下,通过将数据应用于数据输入引脚并拉低SHIFT/LOAD引脚来完成。在串行移位模式下,数据通过J-K输入进入,允许第一阶段作为J-K或T flip-flop工作。

应用信息: 所有输入都配备了防静电放电瞬态过电压保护电路。

封装信息: - Plastic Package:B1R - Ceramic Package:F1R - Micro Package:M1R - Chip Carrier:C1R
M74HC195C1R 价格&库存

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