M74HC40103RM13TR

M74HC40103 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 38MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 40103 DESCRIPTION The M74HC40103 is an high speed CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER fabricated with silicon gate C2MOS technology. The HC40103 consists of an 8 stage synchronous down counter with a single output which is active when the internal count is zero. The HC40103 contains a single 8-bit binary counter. This device has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT / ZERO DETECT output are active low logic. In normal operation the counter is decremented by one count on each positive transition of the CLOCK. Counting is DIP SOP TSSOP ORDER CODES PACKAG E DIP SOP TSSOP TUBE T&R M74HC40103B1R M74HC40103M1R M74HC40103RM13TR M74HC40103TTR inhibited when the CARRY-IN / COUNTER ENABLE (CI/CE) input is high. The CARRY-OUT / ZERO-DETECT (CO/ZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE) input is low, data at the J input is clocked into the counter on the next positive clock transition regardless of the state of the CI/CE input. When the ASYNCHRONOUS PRESET-ENABLE (APE) input is low, data at the J inputs is asynchronously forced into the counter regardless of the state of the SPE CI/CE or CLOCK inputs. J input J0-J7 represent a singular 8-bit binary word. When the CLEAR, CLR input is low, the counter is asynchronously cleared to its maximum count PIN CONNECTION AND IEC LOGIC SYMBOLS September 2001 1/16 M74HC40103 (25510) regardless of the state of any other input. The precedence relationship between control input is indicated in the truth table. If all control inputs are high at the time of zero count, the counters will jump to the maximum count giving a counting sequence of 256 clock pulses long. The HC40103 may be cascaded using the CI/CE input and the CO/ZD output, in either a synchronous or ripple mode. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 CLOCK 2 CLEAR 3 4, 5, 6, 7, 10, 11, 12, 13 CI/CE J0 to J9 9 APE 14 CO/ZD 15 SPE 8 16 GND Vcc NAME AND FUNCTION Clock Input (LOW to HIGH edge triggered) Asynchronous Master Reset Input (Active Low) Terminal Enable Input Jam Inputs Asynchronous Preset Enable Inputs(Active Low) Terminal Count Output (Active Low) Synchronous Preset Enable Input (Active Low) Ground (0V) Positive Supply Voltage TRUTH TABLE CONTROL INPUTS MODE CLEAR APE SPE CI/CE H H H H H H H L H H L X H L X X L X X X X : Don’t Care Maximum Count is "255" 2/16 COUNT INHIBIT REGULAR COUNT SYNCHRONOUS PRESET ASYNCHRONOUS PRESET CLEAR FUNCTIONAL DESCRIPTION EVEN IF CLOCK IS GIVEN, NO COUNT IS MADE DOWN COUNT AT RISING EDGE OF CLOCK DATA OF PI TERMINAL IS PRESET AT RISING EDGE OF CLOCK DATA OF PI TERMINAL IS ASYNCHRONOUSLY PRESET TO CLOCK COUNTER IS SET TO MAXIMUM COUNT M74HC40103 LOGIC DIAGRAM TIMING CHART 3/16 M74HC40103 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Supply Voltage Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ± 50 mA VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) V 500(*) mW -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Unit 2 to 6 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC V Top Operating Temperature -55 to 125 °C Input Rise and Fall Time tr, tf 4/16 Value Supply Voltage VCC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns M74HC40103 DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOL II ICC Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 4.5 6.0 2.0 4.5 6.0 Typ. Max. 1.5 3.15 4.2 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 Max. 1.5 3.15 4.2 0.5 1.35 1.8 V 0.5 1.35 1.8 2.0 IO=-20 µA 1.9 2.0 1.9 1.9 4.5 IO=-20 µA 4.4 4.5 4.4 4.4 6.0 IO=-20 µA 5.9 6.0 5.9 5.9 4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10 5.68 Unit V V 6.0 IO=-5.2 mA 2.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=20 µA 0.0 0.1 0.1 0.1 6.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=4.0 mA 0.17 0.26 0.33 0.40 6.0 IO=5.2 mA 0.18 0.26 0.33 0.40 6.0 VI = VCC or GND ± 0.1 ±1 ±1 µA 6.0 VI = VCC or GND 4 40 80 µA 5.8 5.63 5.60 V AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CK - CO/ZD) tPLH tPHL Propagation Delay Time (APE - CO/ZD) tPLH tPHL Propagation Delay Time (CL - CO/ZD) tPLH tPHL Propagation Delay Time (CI/CE - CO/ZD) VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Value TA = 25°C Min. Typ. Max. 30 8 7 96 24 20 116 29 25 104 26 22 48 12 10 75 15 13 185 37 31 225 45 38 200 40 34 95 19 16 -40 to 85°C -55 to 125°C Min. Min. Max. 95 19 16 230 46 39 280 56 48 250 50 43 120 24 20 Unit Max. 110 22 19 280 56 47 340 68 57 300 60 51 145 29 24 ns ns ns ns ns 5/16 M74HC40103 Test Condition Symbol fMAX tW tW tW tREM tSETUP tSETUP tSETUP thold thold thold Parameter Maximum Clock Frequency Clock Pulse Width HIGH or LOW CLEAR Pulse Width LOW Preset Enable Pulse Width APE, LOW Removal time CLEAR to CLOCK or APE to CLOCK Set Up Time SPE to CLOCK Set Up Time CI/CE to CLOCK Set Up Time Jn to CLOCK Hold Time SPE to CLOCK Hold Time CI/CE to CLOCK Hold Time Jn to CLOCK Value TA = 25°C VCC (V) Min. Typ. 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4 20 24 150 30 25 115 20 19 115 20 19 47 9 8 70 13 11 140 27 23 72 14 12 -14 -5 -4 -30 -11 -9 -17 -6 -5 8 32 38 20 7 5 35 12 10 31 11 9 12 4 3 20 7 5 40 14 12 20 8 6 0 0 0 0 0 0 0 0 0 Max. -40 to 85°C -55 to 125°C Min. Min. Max. 3 16 19 195 36 32 140 28 24 140 28 24 62 12 10 90 16 15 175 36 31 92 18 15 0 0 0 0 0 0 0 0 0 Unit Max. 2.6 13 15 235 45 40 175 35 30 175 35 30 70 13 11 110 20 16 205 42 36 105 20 18 0 0 0 0 0 0 0 0 0 MHz ns ns ns ns ns ns ns ns ns ns CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) Value TA = 25°C Min. Typ. Max. 10 CIN Input Capacitance 5.0 5 CPD Power Dissipation Capacitance (note 1) 5.0 60 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC 6/16 M74HC40103 FUNCTIONAL DESCRIPTION This device is an 8-stage presettable synchronous down counter. Carry Out/Zero Detect (CO/ZD) is output at the "L" level for the period of 1 bit when the readout becomes "0". This device adopts 8-bit-binary counter decimal notation, making setting up to 255 counts possible. COUNT OPERATION At the "H" level of control input of CLEAR, SPE and APE, the counter carriers out down count operation one by one at the rise of pulse given to CLOCK input. Count operation can be inhibited by setting Carry Input/Clock Enable CI/CE to the "H" level. CO/ZD is output at the "L" level when the readout becomes "0" but is not output even if the readout becomes "0" when CI/CE is at the "H" level, thus maintaining the "H" level. Synchronous cascade operation can be carried out by using CI/CE input and CO/ZD output. The contents of count jump to maximum count (255) if clock is given when the readout is "0". Therefore, operation of 256-frequency division is carried out when clock input alone is given without various kinds of preset operation. PRESET AND RESET OPERATION When Clear (CLEAR) input is set to the "L" level, the readout is set to the maximum count independently of other inputs. When Asynchronous Preset Enable (APE) input is set to the "L" level, readouts given on J0 to J7 can be preset asynchronously to the counter independently of inputs other than CLEAR input. When Synchronous Preset Enable (SPE) is set to the "L" level the readouts given on J0 to J7 can be preset to counter synchronously with the rise of clock. As to these operation mode, refer to the truth table. INPUTS OUTPUT CLEAR APE SPE J TE CLOCK Qn + 1 L H H X L L X X X X L H X X X X X X L L H H H L L X L H H L H X H H H L X X Qn H H H X L Qn H H H X H X Qn 7/16 M74HC40103 TYPICAL APPLICATIONS PROGRAMMABLE DIVIDE-BY-N COUNTER fOUT = fIN / (N+1) Timing Chart when N = "3" (J0, J1 = VCC , J2-J7 = GND HC40103 ... 1/2 to 1/256 are dividable PARALLEL CARRY CASCADING * At synchronous cascade connection, huzzerd occurs at C0 output after its second stage when digit place changes, due to delay arrival. Therefore, take gate from HC32 or the like, not from C0 output at the rear stage directly PROGRAMMABLE TIMER The above formula does not take into account the phase of clock input. Therefore, the real pulse width is the distance between the above formula-1/f IN ~ The above formula 8/16 M74HC40103 TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 9/16 M74HC40103 WAVEFORM 2 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) WAVEFORM 3 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) 10/16 M74HC40103 WAVEFORM 4 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) WAVEFORM 5 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle) 11/16 M74HC40103 WAVEFORM 6 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle) 12/16 M74HC40103 Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 13/16 M74HC40103 SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8° (max.) PO13H 14/16 M74HC40103 TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.60 0.0256 BSC 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 15/16 M74HC40103 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 16/16