M74HC40103TTR

M74HC40103 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER s s s s s s s HIGH SPEED : fMAX = 38MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 40103 DIP SOP TSSOP ORDER CODES PACKAG E DIP SOP TSSOP TUBE T&R DESCRIPTION The M74HC40103 is an high speed CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER fabricated with silicon gate C2MOS technology. The HC40103 consists of an 8 stage synchronous down counter with a single output which is active when the internal count is zero. The HC40103 contains a single 8-bit binary counter. This device has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT / ZERO DETECT output are active low logic. In normal operation the counter is decremented by one count on each positive transition of the CLOCK. Counting is PIN CONNECTION AND IEC LOGIC SYMBOLS M74HC40103B1R M74HC40103M1R M74HC40103RM13TR M74HC40103TTR inhibited when the CARRY-IN / COUNTER ENABLE (CI/CE) input is high. The CARRY-OUT / ZERO-DETECT (CO/ZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE) input is low, data at the J input is clocked into the counter on the next positive clock transition regardless of the state of the CI/CE input. When the ASYNCHRONOUS PRESET-ENABLE (APE) input is low, data at the J inputs is asynchronously forced into the counter regardless of the state of the SPE CI/CE or CLOCK inputs. J input J0-J7 represent a singular 8-bit binary word. When the CLEAR, CLR input is low, the counter is asynchronously cleared to its maximum count September 2001 1/16 M74HC40103 (25510) regardless of the state of any other input. The precedence relationship between control input is indicated in the truth table. If all control inputs are high at the time of zero count, the counters will jump to the maximum count giving a INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2 3 4, 5, 6, 7, 10, 11, 12, 13 9 14 15 8 16 SYMBOL CLOCK CLEAR CI/CE J0 to J9 APE CO/ZD SPE GND Vcc NAME AND FUNCTION Clock Input (LOW to HIGH edge triggered) Asynchronous Master Reset Input (Active Low) Terminal Enable Input Jam Inputs Asynchronous Preset Enable Inputs(Active Low) Terminal Count Output (Active Low) Synchronous Preset Enable Input (Active Low) Ground (0V) Positive Supply Voltage counting sequence of 256 clock pulses long. The HC40103 may be cascaded using the CI/CE input and the CO/ZD output, in either a synchronous or ripple mode. All inputs are equipped with protection circuits against static discharge and transient excess voltage. TRUTH TABLE CONTROL INPUTS MODE CLEAR H H H H L APE H H H L X SPE H H L X X CI/CE H L X X X COUNT INHIBIT REGULAR COUNT SYNCHRONOUS PRESET ASYNCHRONOUS PRESET CLEAR EVEN IF CLOCK IS GIVEN, NO COUNT IS MADE DOWN COUNT AT RISING EDGE OF CLOCK DATA OF PI TERMINAL IS PRESET AT RISING EDGE OF CLOCK DATA OF PI TERMINAL IS ASYNCHRONOUSLY PRESET TO CLOCK COUNTER IS SET TO MAXIMUM COUNT FUNCTIONAL DESCRIPTION X : Don’t Care Maximum Count is "255" 2/16 M74HC40103 LOGIC DIAGRAM TIMING CHART 3/16 M74HC40103 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 25 ± 50 500(*) -65 to +150 300 Unit V V V mA mA mA mA mW °C °C ICC or IGND DC VCC or Ground Current Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2.0V VCC = 4.5V VCC = 6.0V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 0 to 1000 0 to 500 0 to 400 Unit V V V °C ns ns ns 4/16 M74HC40103 DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage 2.0 4.5 6.0 4.5 6.0 II ICC Input Leakage Current Quiescent Supply Current 6.0 6.0 IO=-20 µA IO=-20 µA IO=-20 µA IO=-4.0 mA IO=-5.2 mA IO=20 µA IO=20 µA IO=20 µA IO=4.0 mA IO=5.2 mA VI = VCC or GND VI = VCC or GND TA = 25°C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 ± 0.1 4 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 ±1 40 Typ. Max. Value -40 to 85°C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 ±1 80 µA µA V V Max. -55 to 125°C Min. 1.5 3.15 4.2 0.5 1.35 1.8 Max. V Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL V VOH AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 TA = 25°C Min. Typ. 30 8 7 96 24 20 116 29 25 104 26 22 48 12 10 Max. 75 15 13 185 37 31 225 45 38 200 40 34 95 19 16 Value -40 to 85°C Min. Max. 95 19 16 230 46 39 280 56 48 250 50 43 120 24 20 -55 to 125°C Min. Max. 110 22 19 280 56 47 340 68 57 300 60 51 145 29 24 ns Unit tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CK - CO/ZD) tPLH tPHL Propagation Delay Time (APE - CO/ZD) tPLH tPHL Propagation Delay Time (CL - CO/ZD) tPLH tPHL Propagation Delay Time (CI/CE - CO/ZD) ns ns ns ns 5/16 M74HC40103 Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 TA = 25°C Min. 4 20 24 150 30 25 115 20 19 115 20 19 47 9 8 70 13 11 140 27 23 72 14 12 -14 -5 -4 -30 -11 -9 -17 -6 -5 Typ. 8 32 38 20 7 5 35 12 10 31 11 9 12 4 3 20 7 5 40 14 12 20 8 6 0 0 0 0 0 0 0 0 0 Max. Value -40 to 85°C Min. 3 16 19 195 36 32 140 28 24 140 28 24 62 12 10 90 16 15 175 36 31 92 18 15 0 0 0 0 0 0 0 0 0 Max. -55 to 125°C Min. 2.6 13 15 235 45 40 175 35 30 175 35 30 70 13 11 110 20 16 205 42 36 105 20 18 0 0 0 0 0 0 0 0 0 Max. MHz Unit fMAX Maximum Clock Frequency Clock Pulse Width HIGH or LOW CLEAR Pulse Width LOW Preset Enable Pulse Width APE, LOW Removal time CLEAR to CLOCK or APE to CLOCK Set Up Time SPE to CLOCK Set Up Time CI/CE to CLOCK Set Up Time Jn to CLOCK Hold Time SPE to CLOCK Hold Time CI/CE to CLOCK Hold Time Jn to CLOCK tW ns tW ns tW ns tREM ns tSETUP ns tSETUP ns tSETUP ns thold ns thold ns thold ns CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) 5.0 5.0 TA = 25°C Min. Typ. 5 60 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF Unit CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC 6/16 M74HC40103 FUNCTIONAL DESCRIPTION This device is an 8-stage presettable synchronous down counter. Carry Out/Zero Detect (CO/ZD) is output at the "L" level for the period of 1 bit when the readout becomes "0". This device adopts 8-bit-binary counter decimal notation, making setting up to 255 counts possible. COUNT OPERATION At the "H" level of control input of CLEAR, SPE and APE, the counter carriers out down count operation one by one at the rise of pulse given to CLOCK input. Count operation can be inhibited by setting Carry Input/Clock Enable CI/CE to the "H" level. CO/ZD is output at the "L" level when the readout becomes "0" but is not output even if the readout becomes "0" when CI/CE is at the "H" level, thus maintaining the "H" level. Synchronous cascade operation can be carried out by using CI/CE input and CO/ZD output. The contents of count jump to maximum count (255) if clock is given when the readout is "0". Therefore, operation of 256-frequency division is carried out when clock input alone is given without various kinds of preset operation. PRESET AND RESET OPERATION When Clear (CLEAR ) input is set to the "L" level, the readout is set to the maximum count independently of other inputs. When Asynchronous Preset Enable (APE) input is set to the "L" level, readouts given on J0 to J7 can be preset asynchronously to the counter independently of inputs other than CLEAR input. When Synchronous Preset Enable (SPE) is set to the "L" level the readouts given on J0 to J7 can be preset to counter synchronously with the rise of clock. As to these operation mode, refer to the truth table. INPUTS CLEAR L H H H H H H H APE X L L H H H H H SPE X X X L L L H H J X L H L H X X X TE X X X X X X L H X CLOCK X X X OUTPUT Qn + 1 L L H L H Qn Qn Qn 7/16 M74HC40103 TYPICAL APPLICATIONS PROGRAMMABLE DIVIDE-BY-N COUNTER fOUT = fIN / (N+1) Timing Chart when N = "3" (J0, J1 = VCC , J2-J7 = GND HC40103 ... 1/2 to 1/256 are dividable PARALLEL CARRY CASCADING * At synchronous cascade connection, huzzerd occurs at C0 output after its second stage when digit place changes, due to delay arrival. Therefore, take gate from HC32 or the like, not from C0 output at the rear stage directly PROGRAMMABLE TIMER The above formula does not take into account the phase of clock input. Therefore, the real pulse width is the distance between the above formula-1/f IN ~ The above formula 8/16 M74HC40103 TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 9/16 M74HC40103 WAVEFORM 2 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) W AVEFORM 3 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) 10/16 M74HC40103 WAVEFORM 4 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) W AVEFORM 5 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle) 11/16 M74HC40103 WAVEFORM 6 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle) 12/16 M74HC40103 Plastic DIP-16 (0.25) MECHANICAL DATA mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch P001C 13/16 M74HC40103 SO-16 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8° (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45° (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 PO13H 14/16 M74HC40103 TSSOP16 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0° 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8° 0.75 0° 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8° 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 15/16 M74HC40103 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 16/16