M74HC533RM13TR

M74HC533 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT INVERTING ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 12ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 533 DESCRIPTION The M74HC533 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with silicon gate C2MOS technology. This 8-BIT D-Type latches is controlled by a latch enable input (LE) and output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input. When the LE is taken, the Q outputs will be latched at the logic level of D input data. ) (s t c u d o r P e DIP PACKAGE TUBE t e l o s b O TSSOP u d o r P e ORDER CODES DIP SOP TSSOP ) s ( ct SOP M74HC533B1R M74HC533M1R T&R M74HC533RM13TR M74HC533TTR While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. The 3-State output configuration and the wide choice of outline make bus organized system simple. All inputs are equipped with protection circuits against static discharge and transient excess voltage. t e l o s b O PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/11 M74HC533 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 OE 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 Q0 to Q7 3 State Output Enable Input (Active LOW) 3 State Outputs D0 to D7 Data Inputs LE GND VCC NAME AND FUNCTION TRUTH TABLE Latch Enable Input Ground (0V) Positive Supply Voltage u d o INPUTS OUTPUTS OE LE D H L L L X L H H X X L H ) (s t c u d o r P e t e l o s b O 2/11 e t e ol s b O X: Don’t Care Z: High Impedance (*): Q Outputs are latched at the time when the LE input is taken low logic level. LOGIC DIAGRAM ) s ( ct Pr Q Z NO CHANGE (*) H L M74HC533 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Supply Voltage Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 35 mA ± 70 mA 500(*) mW VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) V ) s ( t -65 to +150 300 c u d °C °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C RECOMMENDED OPERATING CONDITIONS Symbol VCC e t e l Parameter Supply Voltage VI Input Voltage VO Output Voltage Top Operating Temperature Input Rise and Fall Time o s b tr, tf s ( t c O ) u d o o r P Value Unit 2 to 6 V 0 to VCC V 0 to VCC V -55 to 125 °C VCC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns r P e t e l o s b O 3/11 M74HC533 DC SPECIFICATIONS Test Condition Symbol VIH Parameter High Level Input Voltage Low Level Input Voltage VIL VOH VOL II High Level Output Voltage Low Level Output Voltage IOZ Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ICC t e l o s b O 4/11 TA = 25°C VCC (V) Min. 2.0 4.5 6.0 2.0 4.5 6.0 Typ. Max. 1.5 3.15 4.2 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 0.5 1.35 1.8 1.9 2.0 1.9 1.9 IO=-20 µA 4.4 4.5 4.4 4.4 du IO=-20 µA 5.9 6.0 5.9 IO=-6.0 mA 4.18 4.31 4.13 5.68 5.9 6.0 IO=-7.8 mA 2.0 IO=20 µA 0.0 0.1 4.5 IO=20 µA 0.0 0.1 o r P 6.0 IO=20 µA 0.0 0.1 4.5 IO=6.0 mA 0.17 6.0 IO=7.8 mA 0.18 6.0 5.8 V 5.63 V ) s ( ct IO=-20 µA 4.5 Max. 0.5 1.35 1.8 4.5 6.0 Unit 1.5 3.15 4.2 2.0 V 4.10 5.60 0.1 0.1 0.1 0.1 0.1 0.1 0.26 0.33 0.40 0.26 0.33 0.40 VI = VCC or GND ± 0.1 ±1 ±1 µA 6.0 VI = VIH or VIL VO = VCC or GND ± 0.5 ±5 ± 10 µA 6.0 VI = VCC or GND 4 40 80 µA ) (s t c u d o r P e Value e t e l b O so V M74HC533 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (LE, D - Q) tPZL tPZH High Impedance Output Enable Time tPLZ tPHZ High Impedance Output Disable Time tW(H) Minimum Pulse Width (LE) Minimum Set-up Time ts e t e ol Min. 50 50 150 50 RL = 1 KΩ 150 RL = 1 KΩ 50 RL = 1 KΩ 50 Typ. Max. 25 7 6 42 14 12 57 19 16 39 13 11 54 18 15 30 14 13 15 6 6 16 4 3 60 12 10 125 25 21 175 35 30 125 25 21 175 35 30 125 25 21 75 15 13 50 10 9 5 5 5 O ) 50 -40 to 85°C -55 to 125°C Min. Min. Max. let 50 75 15 13 155 31 26 220 44 37 155 31 26 220 44 37 155 31 26 95 19 16 65 13 11 5 5 5 Unit Max. 90 18 15 190 38 32 265 53 45 190 38 32 265 53 45 190 38 32 110 22 19 75 15 13 5 5 5 ns ns ) s ( ct u d o r P e o s b s ( t c du o r P Minimum Hold Time th 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 TA = 25°C CL (pF) VCC (V) Value ns ns ns ns ns ns ns CAPACITIVE CHARACTERISTICS s b O Symbol Parameter CIN Input Capacitance COUT Output Capacitance Power Dissipation Capacitance (note 1) CPD Test Condition VCC (V) Value TA = 25°C Min. Typ. Max. 5 10 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF 10 pF 38 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip Flop) and the CPD when n pcs of Flip Flop operate, can be gained by the following equation: CPD(TOTAL) = 22 + 16 x n (pF) 5/11 M74HC533 TEST CIRCUIT ) s ( ct u d o TEST tPLH, tPHL tPZL, tPLZ e t e ol tPZH, tPHZ CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) s b O Pr SWITCH Open VCC GND WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) ) (s t c u d o r P e t e l o s b O 6/11 M74HC533 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) ) s ( ct u d o r P e t e l o ) (s s b O WAVEFORM 3: PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) t c u d o r P e t e l o s b O 7/11 M74HC533 Plastic DIP-20 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.254 B 1.39 TYP MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D ) s ( ct 25.4 E 8.5 e 2.54 e3 22.86 u d o 0.335 7.1 I 3.93 s ( t c 1.34 e t e ol bs O ) 3.3 Z Pr 0.100 F L 1.000 0.900 0.280 0.155 0.130 0.053 u d o r P e t e l o s b O P001J 8/11 M74HC533 SO-20 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. a1 2.65 MAX. 0.1 0.104 0.2 a2 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 b1 0.23 0.32 0.009 C 0.5 0.019 ) s ( ct 0.012 0.020 c1 u d o 45° (typ.) D 12.60 13.00 0.496 E 10.00 10.65 0.393 e 1.27 e3 11.43 F 7.40 7.60 L 0.50 1.27 M ) (s S e t e ol s b O 0.75 Pr 0.512 0.419 0.050 0.450 0.291 0.300 0.020 0.050 0.029 8° (max.) t c u d o r P e t e l o s b O PO13L 9/11 M74HC533 TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 c 0.09 0.20 0.004 D 6.4 6.5 6.6 0.252 E 6.2 6.4 6.6 0.244 E1 4.3 4.4 4.48 1 e bs 0.65 BSC K 0° L 0.45 let o s b 0.60 s ( t c 0.75 du ro P e A2 A1 b 0.260 0.252 0.260 0.173 0.176 0.0256 BSC 0° 8° 0.018 0.024 O K e 0.030 L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 10/11 0.0089 0.256 u d o r P e A O ) 8° 0.012 t e l o 0.169 ) s ( ct M74HC533 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. 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