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M74HC564RM13TR

M74HC564RM13TR

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

  • 描述:

    M74HC564RM13TR - OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT INVERTING - STMicroelectronics

  • 数据手册
  • 价格&库存
M74HC564RM13TR 数据手册
M74HC564 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT INVERTING s s s s s s s HIGH SPEED: fMAX = 90MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 564 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC564B1R M74HC564M1R T&R M74HC564RM13TR M74HC564TTR DESCRIPTION The M74HC564 is an high speed CMOS OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS INVERTING fabricated with silicon gate C2MOS technology. This 8 bit D-TYPE FLIP FLOP is controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. The output control does not affect the internal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/11 M74HC564 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 3, 4, 5, 6, 7, 8, 9, 10 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 SYMBOL OE D0 to D7 Q0 to Q7 NAME AND FUNCTION 3 State Output Enable Input (Active LOW) Data Inputs 3 State Outputs CLOCK GND VCC Clock Input (LOW to HIGH, edge triggered) Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OE H L L L X: Don’t Care Z: High Impedance OUTPUT D X X L H Q Z NO CHANGE H L CK X LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 M74HC564 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 35 ± 70 500(*) -65 to +150 300 Unit V V V mA mA mA mA mW °C °C ICC or IGND DC VCC or Ground Current Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2.0V VCC = 4.5V VCC = 6.0V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 0 to 1000 0 to 500 0 to 400 Unit V V V °C ns ns ns 3/11 M74HC564 DC SPECIFICATION Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage 2.0 4.5 6.0 4.5 6.0 II IOZ Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current 6.0 6.0 6.0 IO=-20 µA IO=-20 µA IO=-20 µA IO=-6.0 mA IO=-7.8 mA IO=20 µA IO=20 µA IO=20 µA IO=6.0 mA IO=7.8 mA VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND TA = 25°C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 ± 0.1 ± 0.5 4 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 ±1 ±5 40 Typ. Max. Value -40 to 85°C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 ±1 ± 10 80 µA µA µA V V Max. -55 to 125°C Min. 1.5 3.15 4.2 0.5 1.35 1.8 Max. V Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL V VOH ICC 4/11 M74HC564 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 CL (pF) TA = 25°C Min. Typ. 25 7 6 70 20 15 88 25 19 48 15 12 60 20 16 34 17 15 18 75 90 15 6 6 25 6 4 Max. 60 12 10 150 30 26 190 38 32 125 25 21 165 33 28 125 25 21 5 25 30 75 15 13 75 15 13 0 0 0 95 19 16 95 19 16 0 0 0 Value -40 to 85°C Min. Max. 75 15 13 190 38 32 240 48 41 155 31 26 205 41 35 155 31 26 4.2 21 25 110 22 19 110 22 19 0 0 0 -55 to 125°C Min. Max. 90 18 15 225 45 38 285 57 48 190 38 32 250 50 43 190 38 32 ns Unit tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CK - Q) 50 50 ns 150 ns tPZL tPZH High Impedance Output Enable Time 50 RL = 1 KΩ ns 150 RL = 1 KΩ ns tPLZ tPHZ High Impedance Output Disable Time fMAX Maximum Clock Frequency Minimum Pulse Width (CK) Minimum Set-up Time Minimum Hold Time 50 RL = 1 KΩ 6.2 31 37 ns 50 MHz tW(L) tW(H) ts 50 ns 50 ns th 50 ns CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) TA = 25°C Min. Typ. 5 10 54 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF pF Unit CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8(per flip-fllop) 5/11 M74HC564 TEST CIRCUIT TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) SWITCH Open VCC GND WAVEFORM 1: CK TO Qn PROPAGATION DELAYS, Dn TO CK SETUP AND HOLD TIMES, CK MAXIMUM FREQUENCY (f=1MHz; 50% duty cycle) 6/11 M74HC564 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) W AVEFORM 3: CK MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle) 7/11 M74HC564 Plastic DIP-20 (0.25) MECHANICAL DATA mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.34 8.5 2.54 22.86 7.1 3.93 0.130 0.053 0.254 1.39 0.45 0.25 25.4 0.335 0.100 0.900 0.280 0.155 1.65 TYP MAX. MIN. 0.010 0.055 0.018 0.010 1.000 0.065 TYP. MAX. inch P001J 8/11 M74HC564 SO-20 MECHANICAL DATA mm. DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8° (max.) 0.291 0.020 13.00 10.65 0.35 0.23 0.5 45° (typ.) 0.496 0.393 0.050 0.450 0.300 0.050 0.029 0.512 0.419 0.1 TYP MAX. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. TYP. MAX. 0.104 0.008 0.096 0.019 0.012 inch PO13L 9/11 M74HC564 TSSOP20 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0° 0.45 0.60 0.05 0.8 0.19 0.09 6.4 6.2 4.3 6.5 6.4 4.4 0.65 BSC 8° 0.75 0° 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 6.6 6.6 4.48 0.002 0.031 0.007 0.004 0.252 0.244 0.169 0.256 0.252 0.173 0.0256 BSC 8° 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.260 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0087225C 10/11 M74HC564 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 11/11
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