M74HC648M1R

M 74HC646 M74HC648 HC646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE) HC648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.) . . . . . . . . HIGH SPEED fMAX = 73 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH= IOL = 6 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS646/648 B1R (Plastic Package) M1R (Micro Package) ORDER CODES : M74HCXXXM1R M74HCXXXB1R DESCRIPTION The M74HC646/648 are high speed CMOS OCTAL BUS TRANSCEIVERS AND REGISTERS, (32 STATE) fabricated in silicon gate C MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These devices consist of bus transceiver circuits with 3-state output, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers on the low-to-high transition of the appropriate clock pin (Clock AB - or Clock BA). Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select controls (Select AB select BA) can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when enable G is active (low). In the isolation mode (enable G high), ”A” data may be stored in one register and/or ”B” data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. All inputs are equipped with protection circuits PIN CONNECTIONS (top view) INPUT AND OUTPUT EQUIVALENT CIRCUIT GAB, GAB, CAB, SAB, SBA, CBA A, B October 1993 1/12 M74HC646/648 LOGIC DIAGRAM (HC648) Note : In case of M54/74HC646 output inverter marked * at A bus and B bus are eliminated. TIMING CHART 2/12 M74HC646/648 T RUTH TABLE HC646 (The truth table for HC648 is the same as this, but with the outputs inverted) G DIR CAB CBA SAB SBA X H X X X X X X A INPUTS Z INPUTS B INPUTS Z INPUTS FUNCTION Both the A bus and the B bus are inputs The output functions of the A and B bus are disabled Both the A and B bus are used for inputs to the internal flip-flops. Data at the bus will be stored on low to high transition of the clock inputs The A bus are inputs and the B bus are outputs The data at the A bus are displayed at the B bus The data at the A bus are displayed at the B bus. The data of the A bus are stored to the internal flip-flop on low to high transition of th clock pulse. The data stored to the internal flip-flop are dispayed at the B bus The data at the A bus are stored to the internal flipflop on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the B bus The B bus are inputs and the A bus are outputs The data at the B bus are displayed at the A bus The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flipflop on low to high transition of the clock pulse The data stored to the internal flip-flops are displayed at the A bus the data at the B bus are stored to the internal flipflop on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the A bus X X* X* L L X X INPUTS L H L H X L H OUTPUTS L H L H Qn L H L H X X* X* H H X X OUTPUTS X* X* L L X* x* X X X H H X X X L L L H L H Qn L H INPUTS L H L H X L H X : DON’T CARE Z : HIGH IMPEDANCE Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS * : THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO HIGH TRANSITION OF THE CLOCK INPUTS 3/12 M74HC646/648 P IN DESCRIPTION PIN No 1 2 3 4, 5, 6, 7, 8, 9, 10, 11 20, 19, 18, 17, 16, 15, 14, 13 21 22 23 12 24 SYMBOL CLOCK AB SELECT AB GAB A1 to A8 B1 to B8 G SELECT BA CLOCK BA GND VCC NAME AND FUNCTION A to B Clock Input (LOW to HIGH, Edge-Trigged) Select A to B Source Input Direction Control Input A data Inputs/Outputs B Data Inputs/Outputs Output Enable Input (Active LOW) Select B to A Source Input B to A Clock Input (LOW to HIGH, Edge-Triggered) Ground (0V) Positive Supply Voltage IEC LOGIC SYMBOLS HC646 HC648 4/12 M74HC646/648 A BSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO ICC or IGND PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source Sink Current Per Output Pin DC VCC or Ground Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 35 ± 70 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mW o o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied. (*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top tr, tf Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2 V VCC = 4.5 V VCC = 6 V Value 2 to 6 0 to VCC 0 to VCC -40 to +85 0 to 1000 0 to 500 0 to 400 Unit V V o V C ns 5/12 M74HC646/648 D C SPECIFICATIONS Test Conditions Symbol VIH Parameter High Level Input Voltage VCC (V) 2.0 4.5 6.0 V IL Low Level Input Voltage High Level Output Voltage 2.0 4.5 6.0 V OH 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage 2.0 4.5 6.0 4.5 II IOZ ICC Input Leakage Current 3 State Output Off State Current Quiescent Supply Current 6.0 6.0 6.0 6.0 VI = IO=-20 µA VIH or V IL IO=-6.0 mA IO=-7.8 mA VI = IO= 20 µA VIH or V IL IO= 6.0 mA IO= 7.8 mA VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 ±0.1 ±0.5 4 Value TA = 25 oC Min. Typ. Max. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.37 0.37 ±1 ±5.0 40 µA µA µA V V -40 to 85 oC Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 V V Unit AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns) Test Conditions Symbol tTLH tTHL tPLH tPHL Parameter Output Transition Time VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 tPLH tPHL Propagation Delay Time (CLOCK - BUS) 2.0 4.5 6.0 2.0 4.5 6.0 CL (pF) 50 Value TA = 25 oC Min. Typ. Max. 25 60 7 12 6 74 21 18 91 26 22 98 28 24 116 33 28 10 150 30 26 190 38 32 210 42 36 250 50 43 -40 to 85 oC Min. Max. 75 15 13 190 38 32 240 48 41 265 53 45 315 63 54 Unit ns Propagation Delay Time (BUS - BUS) 50 ns 150 ns 50 ns 150 ns 6/12 M74HC646/648 A C ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns) Symbol tPLH tPHL Parameter Propagation Delay Time (SELECT - BUS) Test Conditions VCC CL (V) (pF) 2.0 4.5 6.0 2.0 4.5 6.0 tPZL tPZH 3-State Output Enable Time (G, DIR) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 50 RL = 1 KΩ 6 30 35 50 Value TA = 25 C -40 to 85 oC Min. Typ. Max. Min. Max. 81 170 215 23 34 43 o Unit ns 150 20 98 28 24 RL = 1 KΩ 84 24 20 102 29 25 60 23 20 19 67 79 30 7 6 16 4 3 29 210 42 36 175 35 30 215 43 37 175 35 30 4.8 24 28 75 15 13 50 10 9 5 5 5 10 37 265 53 45 220 44 37 270 54 46 220 44 37 ns 50 ns 150 RL = 1 KΩ ns tPLZ tPHZ fMAX Output Disable Time (G, DIR) Maximum Clock Frequency ns 50 MHz 95 19 16 65 13 11 5 5 5 10 tW(H) tW(L) ts Minimum Clock Pulse Width 50 ns Minimum Set-up Time 50 ns th Minimum Hold Time 50 5 10 39 38 ns pF pF pF CIN CI/O CPD (*) Input Capacitance Bus Terminal Capacitance Power Dissipation Capacitance for HC646 for HC648 (*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/8 (per bit) 7/12 M74HC646/648 SWITCHING CHARACTERISTICS TEST CIRCUIT AND WAVEFORM WAVEFORM 1 WAVEFORM 2 WAVEFORM 3 WAVEFORM 5 WAVEFORM 4 8/12 M74HC646/648 TEST WAVEFORM ICC (Opr.) * INPUT TRANSITION TIME IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICSTEST. 9/12 M74HC646/648 Plastic DIP24 (0.25) MECHANICAL DATA mm MIN. a1 b b1 b2 D E e e3 F I L 4.445 3.3 15.2 2.54 27.94 14.1 0.175 0.130 0.23 1.27 32.2 16.68 0.598 0.100 1.100 0.555 TYP. 0.63 0.45 0.31 0.009 0.050 1.268 0.657 MAX. MIN. inch TYP. 0.025 0.018 0.012 MAX. DIM. P043A 10/12 M74HC646/648 SO24 MECHANICAL DATA mm MIN. A a1 a2 b b1 C c1 D E e e3 F L S 7.40 0.50 15.20 10.00 1.27 13.97 7.60 1.27 8° (max.) L C c1 DIM. inch MAX. 2.65 MIN. TYP. MAX. 0.104 0.004 0.007 0.096 0.013 0.009 0.020 45° (typ.) 15.60 10.65 0.598 0.393 0.05 0.55 0.291 0.19 0.299 0.050 0.614 0.420 0.019 0.012 TYP. 0.10 0.20 2.45 0.35 0.23 0.50 0.49 0.32 a2 A e3 E D 24 13 1 12 F a1 b e s b1 11/12 M74HC646/648 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A 12/12