M74HCT7259B1R

® M74HCT7259 8BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER (OPEN DRAIN,INVERTING OUTPUT) PRELIMINARY DATA LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C s COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN) VIL = 0.8V (MAX) AT 5V s OUTPUT DRIVE CAPABILITY 90 LSTTL LOADS s HIGH CURRENT OPEN DRAIN OUTPUT UP TO 80 mA The M74HCT7259 is a high speed CMOS 8 BIT ADDRESSABLE LATCH/DECODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The M74HCT7259 has single data input (D) 8 LATCH inverted OUTPUTS (Q0-Q7), 3 address inputs (A, B and C), common enable input (ENABLE) and a common CLEAR input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to be entered is held on the A, B and C inputs. When ENABLE is taken low the data flows through to the address output. The data is stored on the positive-going edge of the ENABLE pulse. All unadressed latches will remain unaffected. With ENABLE in the high state the device is deselected and all latches remain in their previous state, unaffected by changes on the s DIP ORDER CODES PACKAGE DIP SOP T UBE M74HCT7259B1R SOP T&R M74HCT7259M1R M74HCT7259M1RTR data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the ENABLE should be held high (inactive) while the address lines are changing. If ENABLE is held high and CLEAR is taken low all eight latches are cleared to the HIGH (OFF) state. If ENABLE is low all latches except the addressed latch will be cleared. The address latch will instead be the complement of the D input,effectively implementing a 3 to 8 line decoder. Internal clamp diodes protect the open drain outputs against over voltages due to inductive loads. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS February 2000 1/11 M74HCT7259 LOGIC DIAGRAM 2/11 M74HCT7259 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 2, 3 4, 5, 6, 7, 9, 10, 11, 12 13 14 15 8 16 SYMBOL A, B, C Q0 to Q7 DATA IN ENABLE CLEAR GND VCC NAME AND FUNCT ION Latch Select latch Outputs Data Inputs Latch Enable Input Conditional Reset Input Ground (0V) Positive Supply Voltage TRUTH TABLE INPUT S CLEAR H H L ENABL E L H L OUTPUTS OF ADDRESSED LATCH D Qi0 D SELECT INPUT S C L L L L H H H H B L L H H L L H H A L H L H L H L H Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 EACH O THER OUTPUT QI0 Qi0 H F UNCTION ADDRESSABLE LATCH MEMORY 8-LINE DEMULTIPLEXER L AT CH ADDRESSED D:The level at the data input Qi0: The level before the indicated steady state input conditions were established, (i = 0,1,....,7). ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO IGND ICC PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Per Pin Ground Current DC VCC Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 100 - 800 50 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mA mW o o C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. o o o o (*) 500 mW: ≅ 65 C derate to 300 mW by 10mW/ C: 65 C to85 C 3/11 M74HCT7259 RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time Parameter Valu e 3.3 to 5.5 0 to VCC 0 to VCC -40 to +85 0 to 500 Unit V V V o C ns DC SPECIFICATIONS Symb ol Parameter Test Co nditions V CC (V) VIH High Level Input Voltage 3.3(*) 4.5 to 5.5 VIL Low Level Input Voltage 3.3(*) 4.5 to 5.5 VOL Low Level Output Voltage 3.3(*) 4.5 IOZ IIN ICC Output Leackage Current Input Leakage Current Quiescent Supply Current 5.5 I O = 70 mA IO= 20 µA IO= 36 mA IO= 80 mA 5.5 5.5 VI = VIH or VIL VOUT = VCC or GND VI = VCC or GND VI = VCC or GND Each Input in Turn: VIN = 0.5 V or 2.4 V All Other Inputs: VCC or GND 0.4 0.0 0.17 0.32 Min. 2.0 2.0 T yp. Valu e T A = 25 oC Max. -40 to 85 o C Min. 2.0 2.0 V Max. Un it 0.5 0.8 0.5 0.8 V 0.5 0.1 0.26 0.40 ±5 ±0.1 4 3.0 0.6 0.1 0.33 0.50 ± 50 ±1 40 3.9 µA µA µA mA V (*) Voltage Range is 3.3V ±5% 4/11 M74HCT7259 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symb ol Parameter T est Cond ition s V CC C L (V) (pF) tTLH tPLZ tPZL Output Transition Time Propagation Delay Time (DATA - Q) 3.3(*) 4.5 3.3(*) 3.3 (*) Valu e T A = 25 oC Min. T yp. 3 Max. 6 -40 to 85 o C Min. Max. 18 9 80 92 20 24 31 37 39 46 98 112 25 29 39 45 49 56 82 98 21 25 33 39 41 49 76 90 19 23 7 7 4 30 36 15 15 10 5 5 96 10 38 45 38 19 38 19 26 13 10 5 10 Un it RL (K Ω ) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 50 50 50 150 50 150 50 50 150 50 50 150 50 50 150 50 50 50 50 50 50 50 50 ns ns 4.5 4.5 tPLZ tPZL Propagation Delay Time (A, B, C - Q) 3.3 (*) 3.3(*) 150 4.5 4.5 ns tPLZ tPZL Propagation Delay Time (ENABLE - Q) 3.3 (*) 3.3(*) 150 4.5 4.5 ns tPLZ tPZL Propagation Delay Time (CLEAR - Q) 3.3 (*) 3.3(*) 150 4.5 4.5 ns tW(L) tW(L) ts th C IN Minimum Pulse Width (CLEAR) Minimum Pulse Width (ENABLE) Minimum Set-Up Time Minimum Hold Time Input Capacitance 3.3(*) 4.5 3.3(*) 4.5 3.3(*) 4.5 3.3(*) 4.5 ns ns ns ns pF pF C PD (**) Power Dissipation Capacitance (*) Voltage Range is 3.3V ±5% (**) CPD is defined as the value of theIC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer toTest Circuit). Average operting current can be obtained by the following equation. I CC(opr) = CPD • VCC • fIN + ICC 5/11 M74HCT7259 SWITCHING CHARACTERISTICS TEST WAVEFORMS WAVEFORM 1: (ENABLE = L, CLR = H, A-C= STABLE) WAVEFORM 2: (ENABLE = L) 6/11 M74HCT7259 WAVEFORM 3: (CLR = H, A-C = STABLE) WAVEFORM 4: (D = H, A-C = STABLE) 7/11 M74HCT7259 WAVEFORM 5: (CLR = H) TEST CIRCUIT ICC (Opr.) 8/11 M74HCT7259 Plastic DIP-16 (0.25) MECHANICAL DATA mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX. DIM. P001C 9/11 M74HCT7259 SO16L MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.4 0.5 10.1 10.0 1.27 8.89 7.6 1.27 0.75 8 (max.) 0.291 0.020 10.5 10.65 0.35 0.23 0.5 45 (typ.) 0.397 0.3.93 0.050 0.350 0.300 0.050 0.029 0.413 0.419 0.1 mm TYP. MAX. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.008 0.096 0.019 0.012 P013I 10/11 M74HCT7259 Information furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. 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