M74HCT74TTR

M74HCT74 DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR s s s s s s HIGH SPEED : fMAX = 48MHz (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HCT74B1R M74HCT74M1R T&R M74HCT74RM13TR M74HCT74TTR DESCRIPTION The M74HCT74 is an high speed CMOS DUAL D TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. A signal on the D INPUT (nD) is transferred on the Q OUTPUT during the positive going transition of the clock pulse. CLEAR (CLR ) and PRESET (PR) are independent of the clock and accomplished by a low on the appropriate input. The M74HCT74 is designed to directly interface HSC2MOS systems with TTL and NMOS components. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/10 M74HCT74 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1,13 2, 12 3, 11 4, 10 5, 9 6, 8 7 14 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK 1PR, 2PR 1Q, 2Q 1Q, 2Q GND Vcc NAME AND FUNCTION Asynchronous Reset Direct Input Data Inputs Clock Input (LOW-to-HIGH, Edge-Triggered) Asynchronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS CLR L H L H H H X : Don’t Care OUTPUTS FUNCTION D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn CLEAR PRESET ---------NO CHANGE PR H L L H H H LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/10 M74HCT74 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 25 ± 50 500(*) -65 to +150 300 Unit V V V mA mA mA mA mW °C °C ICC or IGND DC VCC or Ground Current Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (VCC = 4.5 to 5.5V) Parameter Value 4.5 to 5.5 0 to VCC 0 to VCC -55 to 125 0 to 500 Unit V V V °C ns DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 5.5 5.5 5.5 IO=-20 µA IO=-4.0 mA IO=20 µA IO=4.0 mA VI = VCC or GND VI = VCC or GND Per Input pin VI = 0.5V or VI = 2.4V Other Inputs at VCC or GND IO = 0 TA = 25°C Min. 2.0 Typ. Max. Value -40 to 85°C Min. 2.0 Max. -55 to 125°C Min. 2.0 Max. V Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Additional Worst Case Supply Current VIL 0.8 4.4 4.18 4.5 4.31 0.0 0.17 0.1 0.26 ± 0.1 2 2.0 4.4 4.13 0.8 4.4 4.10 0.1 0.33 ±1 20 2.9 0.8 V VOH VOL II ICC ∆ ICC V 0.1 0.40 ±1 40 3.0 V µA µA mA 3/10 M74HCT74 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter VCC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 1 27 TA = 25°C Min. Typ. 8 21 18 48 6 8 7 15 15 15 0 5 5 Max. 15 33 30 22 19 19 19 0 6 5 Value -40 to 85°C Min. Max. 19 41 38 18 23 23 23 0 8 -55 to 125°C Min. Max. 22 50 45 ns ns ns MHz ns ns ns ns ns Unit tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CLOCK-Q) tPLH tPHL Propagation Delay Time (CL,PR - Q,Q) fMAX Maximum Clock Frequency Minimum Pulse tW(H) Width (CLOCK) tW(L) tW(L) ts th tREM Minimum Pulse Width (CLR, PR) Minimum Set-Up Time Minimum Hold Time Minimum Removal Time (CLR, PR to CLOCK) CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) TA = 25°C Min. Typ. 5 32 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF Unit CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + I CC/2 (per FLIP/ FLOP) 4/10 M74HCT74 TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : PROPAGATION DELAY, MINIMUM SETUP AND HOLD TIME, CK MINIMUM PULSE WIDTH AND MAXIMUM FREQUENCY (f=1MHz; 50% duty cycle) 5/10 M74HCT74 WAVEFORM 2 : MINIMUM PULSE WIDTH, PROPAGATION DELAY (f=1MHz; 50% duty cycle) W AVEFORM 3 : MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) 6/10 M74HCT74 Plastic DIP-14 MECHANICAL DATA mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 1.27 3.3 2.54 0.050 8.5 2.54 15.24 7.1 5.1 0.130 0.100 0.51 1.39 0.5 0.25 20 0.335 0.100 0.600 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.055 0.020 0.010 0.787 0.065 TYP. MAX. inch P001A 7/10 M74HCT74 SO-14 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 8.55 5.8 1.27 7.62 4.0 5.3 1.27 0.68 8° (max.) 0.149 0.181 0.019 8.75 6.2 0.35 0.19 0.5 45° (typ.) 0.336 0.228 0.050 0.300 0.157 0.208 0.050 0.026 0.344 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 PO13G 8/10 M74HCT74 TSSOP14 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0° 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8° 0.75 0° 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8° 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080337D 9/10 M74HCT74 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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