M74HCT75RM13TR

M74HCT75 4 BIT D TYPE LATCH s s s s s s HIGH SPEED : tPD = 21ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 75 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HCT75B1R M74HCT75M1R T&R M74HCT75RM13TR M74HCT75TTR DESCRIPTION The M74HCT75 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. It contains two groups of 2 bit latches controlled by an enable input (G1•2 or G3•4). These two latch groups can be used in different circuits. Each latch has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The data applied to the data input is transferred to the Q and Q outputs when the enable input is taken high and the outputs will follow the data input as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data input is retained at the outputs. The M74HCT75 is designed to directly interface HSC2MOS systems with TTL and NMOS components. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS September 2001 1/9 M74HCT75 IINPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 4, 11, 8 2, 3, 6, 7 4 13 16, 15, 10, 9 12 5 SYMBOL 1Q to 4Q 1D to 4D G3 • 4 G1 • 2 1Q to 4Q GND VCC NAME AND FUNCTION Complementary Latch Outputs Data Inputs Latch Enable Input, latches 3 and 4 Latch Enable Input, latches 1 and 2 Latch Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS D L H X G H H L OUTPUTS FUNCTION Q L H Qn Q H L Qn LATCH LOGIC DIAGRAM 2/9 M74HCT75 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 25 ± 50 500(*) -65 to +150 300 Unit V V V mA mA mA mA mW °C °C ICC or IGND DC VCC or Ground Current Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (VCC = 4.5 to 5.5V) Parameter Value 4.5 to 5.5 0 to VCC 0 to VCC -55 to 125 0 to 500 Unit V V V °C ns 3/9 M74HCT75 DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 5.5 5.5 5.5 IO=-20 µA IO=-4.0 mA IO=20 µA IO=4.0 mA VI = VCC or GND VI = VCC or GND Per Input pin VI = 0.5V or VI = 2.4V Other Inputs at VCC or GND IO = 0 TA = 25°C Min. 2.0 Typ. Max. Value -40 to 85°C Min. 2.0 Max. -55 to 125°C Min. 2.0 Max. V Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Additional Worst Case Supply Current VIL 0.8 4.4 4.18 4.5 4.31 0.0 0.17 0.1 0.26 ± 0.1 2 2.0 4.4 4.13 0.8 4.4 4.10 0.1 0.33 ±1 20 2.9 0.8 V VOH VOL II ICC ∆ ICC V 0.1 0.40 ±1 40 3.0 V µA µA mA AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter VCC (V) 4.5 4.5 4.5 4.5 4.5 4.5 TA = 25°C Min. Typ. 8 18 21 8 4 Max. 15 28 33 15 10 5 Value -40 to 85°C Min. Max. 19 35 41 19 13 5 -55 to 125°C Min. Max. 22 42 50 22 15 8 ns ns ns ns ns ns Unit tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (DATA - Q) tPLH tPHL Propagation Delay Time (G - Q) Minimum Pulse tW(H) Width (G) Minimum Set-Up ts Time Minimum Hold th Time 4/9 M74HCT75 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) TA = 25°C Min. Typ. 5 61 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF Unit CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM : PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 5/9 M74HCT75 Plastic DIP-16 (0.25) MECHANICAL DATA mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch P001C 6/9 M74HCT75 SO-16 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8° (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45° (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 PO13H 7/9 M74HCT75 TSSOP16 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0° 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8° 0.75 0° 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8° 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 8/9 M74HCT75 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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