M93C46-RDS6TG

M93C86, M93C76, M93C66 M93C56, M93C46, M93C06 16Kbit, 8Kbit, 4Kbit, 2Kbit, 1Kbit and 256bit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROM FEATURES SUMMARY ■ Industry Standard MICROWIRE Bus ■ Figure 1. Packages Single Supply Voltage: – 4.5V to 5.5V for M93Cx6 – 2.5V to 5.5V for M93Cx6-W – 1.8V to 5.5V for M93Cx6-R ■ Dual Organization: by Word (x16) or Byte (x8) ■ Programming Instructions that work on: Byte, Word or Entire Memory ■ Self-timed Programming Cycle with Auto-Erase ■ Ready/Busy Signal During Programming ■ Speed: – 1MHz Clock Rate, 10ms Write Time (Current product, identified by process identification letter F or M) – 2MHz Clock Rate, 5ms Write Time (New Product, identified by process identification letter W) ■ Sequential Read Operation ■ Enhanced ESD/Latch-Up Behaviour ■ More than 1 Million Erase/Write Cycles ■ More than 40 Year Data Retention 8 1 PDIP8 (BN) 8 1 SO8 (MN) 150 mil width TSSOP8 (DS) 3x3mm body size TSSOP8 (DW) 169 mil width M93C06 IS “NOT FOR NEW DESIGN” The M93C06 is still in production, but is not recommended for new designs. Please refer to AN1571 November 2003 on how to replace the M93C06 by the M93C46 in your application. 1/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 M93C06 IS “NOT FOR NEW DESIGN” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Memory Size versus Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 3. Instruction Set for the M93Cx6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. 90° Turned-SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 POWER-ON DATA PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Instruction Set for the M93C46 and M93C06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 5. Instruction Set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 6. Instruction Set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. READ, WRITE, EWEN, EWDS Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Erase/Write Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. ERASE, ERAL Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. WRAL Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 READY/BUSY STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 8. Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Table 8. Operating Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 9. Operating Conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 10. Operating Conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 11. AC Measurement Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 12. AC Measurement Conditions (M93Cx6-W and M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9. AC Testing Input Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 14. DC Characteristics (M93Cx6, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 15. DC Characteristics (M93Cx6, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 16. DC Characteristics (M93Cx6-W, temperature range 6). . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 17. DC Characteristics (M93Cx6-W, temperature range 3). . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 18. DC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 19. AC Characteristics (M93Cx6, temperature range 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 20. AC Characteristics (M93Cx6-W, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 21. AC Characteristics (M93Cx6-W, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 22. AC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10. Synchronous Timing (Start and Op-Code Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11. Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 12. Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 23 Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 23 Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline. . . . 24 Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data 24 Figure 15. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline 25 Table 25. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 16. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 26 Table 26. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 26 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 28. How to Identify Current and New Products by the Process Identification Letter . . . . . . . 28 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 SUMMARY DESCRIPTION These electrically erasable programmable memory (EEPROM) devices are accessed through a Serial Data Input (D) and Serial Data Output (Q) using the MICROWIRE bus protocol. Figure 2. Logic Diagram VCC D Q C Table 2. Memory Size versus Organization Device Number of Bits Number of 8-bit Bytes Number of 16-bit Words M93C86 16384 2048 1024 M93C76 8192 1024 512 M93C66 4096 512 256 M93C56 2048 256 128 M93C46 1024 128 64 M93C061 256 32 16 Note: 1. Not for New Design M93Cx6 The M93Cx6 is accessed by a set of instructions, as summarized in Table 3, and in more detail in Table 4 to Table 6). S ORG Table 3. Instruction Set for the M93Cx6 Instruction VSS AI01928 Table 1. Signal Names S Chip Select Input D Serial Data Input Q Serial Data Output C Serial Clock ORG Organisation Select VCC Supply Voltage VSS Ground The memory array organization may be divided into either bytes (x8) or words (x16) which may be selected by a signal applied on Organization Select (ORG). The bit, byte and word sizes of the memories are as shown in Table 2. 4/30 Description Data READ Read Data from Memory Byte or Word WRITE Write Data to Memory Byte or Word EWEN Erase/Write Enable EWDS Erase/Write Disable ERASE Erase Byte or Word ERAL Erase All Memory WRAL Write All Memory with same Data Byte or Word A Read Data from Memory (READ) instruction loads the address of the first byte or word to be read in an internal address register. The data at this address is then clocked out serially. The address register is automatically incremented after the data is output and, if Chip Select Input (S) is held High, the M93Cx6 can output a sequential stream of data bytes or words. In this way, the memory can be read as a data stream from eight to 16384 bits long (in the case of the M93C86), or continuously (the address counter automatically rolls over to 00h when the highest address is reached). Programming is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle) and does not require an Erase cycle prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the byte or word locations of the M93Cx6. After the start of the programming cy- M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 cle, a Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is driven High. An internal Power-on Data Protection mechanism in the M93Cx6 inhibits the device when the supply is too low. The DU (Don’t Use) pin does not contribute to the normal operation of the device. It is reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be connected to VCC or V SS. Direct connection of DU to VSS is recommended for the lowest stand-by power consumption. Figure 3. DIP, SO and TSSOP Connections M93Cx6 S C D Q 1 2 3 4 8 7 6 5 VCC DU ORG VSS AI01929B Note: 1. See page 23 (onwards) for package dimensions, and how to identify pin-1. 2. DU = Don’t Use. Figure 4. 90° Turned-SO Connections M93Cx6 DU VCC S C 1 2 3 4 8 7 6 5 ORG VSS Q D AI00900B Note: 1. See page 26 for package dimensions, and how to identify pin-1. 2. DU = Don’t Use. MEMORY ORGANIZATION The M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization Select (ORG) is left unconnected (or connected to VCC) the x16 organization is selected; when Organization Select (ORG) is connected to Ground (VSS) the x8 organization is selected. When the M93Cx6 is in stand-by mode, Organization Select (ORG) should be set either to VSS or VCC for minimum power consumption. Any voltage between VSS and V CC applied to Organization Select (ORG) may increase the stand-by current. POWER-ON DATA PROTECTION To prevent data corruption and inadvertent write operations during power-up, a Power-On Reset (POR) circuit resets all internal programming circuitry, and sets the device in the Write Disable mode. – At Power-up and Power-down, the device must not be selected (that is, Chip Select Input (S) must be driven Low) until the supply voltage reaches the operating value VCC specified in Table 8 to Table 10. – When VCC reaches its valid level, the device is properly reset (in the Write Disable mode) and is ready to decode and execute incoming instructions. For the M93Cx6 devices (5V range) the POR threshold voltage is around 3V. For the M93Cx6W (3V range) and M93Cx6-R (2V range) the POR threshold voltage is around 1.5V. 5/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 INSTRUCTIONS The instruction set of the M93Cx6 devices contains seven instructions, as summarized in Table 4 to Table 6. Each instruction consists of the following parts, as shown in Figure 5: ■ Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock (C) being held Low. ■ A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of Serial Clock (C). ■ Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code). ■ The address bits of the byte or word that is to be accessed. For the M93C46, the address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization (see Table 4). For the M93C56 and M93C66, the address is made up of 8 bits for the x16 organization or 9 bits for the x8 organization (see Table 5). For the M93C76 and M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8 organization (see Table 6). The M93Cx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in Table 19 to Table 22. Table 4. Instruction Set for the M93C46 and M93C06 x8 Origination (ORG = 0) Instruc tion Description Start bit OpCode Address1,2 Data READ Read Data from Memory 1 10 A6-A0 Q7-Q0 WRITE Write Data to Memory 1 01 A6-A0 D7-D0 EWEN Erase/Write Enable 1 00 EWDS Erase/Write Disable 1 ERASE Erase Byte or Word ERAL WRAL Required Clock Address1,3 Cycles Data Required Clock Cycles A5-A0 Q15-Q0 18 A5-A0 D15-D0 11X XXXX 10 11 XXXX 9 00 00X XXXX 10 00 XXXX 9 1 11 A6-A0 10 A5-A0 9 Erase All Memory 1 00 10X XXXX 10 10 XXXX 9 Write All Memory with same Data 1 00 01X XXXX 18 01 XXXX Note: 1. X = Don’t Care bit. 2. Address bits A6 and A5 are not decoded by the M93C06. 3. Address bits A5 and A4 are not decoded by the M93C06. 6/30 x16 Origination (ORG = 1) D7-D0 D15-D0 25 25 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Table 5. Instruction Set for the M93C56 and M93C66 x8 Origination (ORG = 0) Instruc tion Description Start bit OpCode Address1,2 Data READ Read Data from Memory 1 10 A8-A0 Q7-Q0 WRITE Write Data to Memory 1 01 A8-A0 D7-D0 EWEN Erase/Write Enable 1 00 EWDS Erase/Write Disable 1 ERASE Erase Byte or Word ERAL WRAL x16 Origination (ORG = 1) Required Clock Address1,3 Cycles Data Required Clock Cycles A7-A0 Q15-Q0 20 A7-A0 D15-D0 1 1XXX XXXX 12 11XX XXXX 11 00 0 0XXX XXXX 12 00XX XXXX 11 1 11 A8-A0 12 A7-A0 11 Erase All Memory 1 00 1 0XXX XXXX 12 10XX XXXX 11 Write All Memory with same Data 1 00 0 1XXX XXXX 20 01XX XXXX D7-D0 D15-D0 27 27 Note: 1. X = Don’t Care bit. 2. Address bit A8 is not decoded by the M93C56. 3. Address bit A7 is not decoded by the M93C56. Table 6. Instruction Set for the M93C76 and M93C86 x8 Origination (ORG = 0) Instruc tion Description Start bit OpCode Address1,2 Data READ Read Data from Memory 1 10 A10-A0 Q7-Q0 WRITE Write Data to Memory 1 01 A10-A0 D7-D0 EWEN Erase/Write Enable 1 00 EWDS Erase/Write Disable 1 ERASE Erase Byte or Word ERAL WRAL x16 Origination (ORG = 1) Required Clock Address1,3 Cycles Data Required Clock Cycles A9-A0 Q15-Q0 22 A9-A0 D15-D0 11X XXXX XXXX 14 11 XXXX XXXX 13 00 00X XXXX XXXX 14 00 XXXX XXXX 13 1 11 A10-A0 14 A9-A0 13 Erase All Memory 1 00 10X XXXX XXXX 14 10 XXXX XXXX 13 Write All Memory with same Data 1 00 01X XXXX XXXX 22 01 XXXX XXXX D7-D0 D15-D0 29 29 Note: 1. X = Don’t Care bit. 2. Address bit A10 is not decoded by the M93C76. 3. Address bit A9 is not decoded by the M93C76. 7/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Figure 5. READ, WRITE, EWEN, EWDS Sequences READ S D 1 1 0 An A0 Q Qn ADDR Q0 DATA OUT OP CODE WRITE S CHECK STATUS D 1 0 1 An A0 Dn D0 Q ADDR DATA IN BUSY READY OP CODE ERASE WRITE ENABLE S D ERASE WRITE DISABLE 1 0 0 1 1 Xn X0 S D OP CODE 1 0 0 0 0 Xn X0 OP CODE AI00878C Note: For the meanings of An, Xn, Qn and Dn, see Table 4, Table 5 and Table 6. Read The Read Data from Memory (READ) instruction outputs serial data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 8-bit byte or the 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically increments the internal address register and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read. 8/30 Erase/Write Enable and Disable The Erase/Write Enable (EWEN) instruction enables the future execution of erase or write instructions, and the Erase/Write Disable (EWDS) instruction disables it. When power is first applied, the M93Cx6 initializes itself so that erase and write instructions are disabled. After an Erase/Write Enable (EWEN) instruction has been executed, erasing and writing remains enabled until an Erase/ Write Disable (EWDS) instruction is executed, or until V CC falls below the power-on reset threshold voltage. To protect the memory contents from accidental corruption, it is advisable to issue the Erase/Write Disable (EWDS) instruction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Erase/ Write Enable (EWEN) or Erase/Write Disable (EWDS) instructions. M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Figure 6. ERASE, ERAL Sequences ERASE S CHECK STATUS D 1 1 1 An A0 Q ADDR BUSY READY OP CODE ERASE ALL S CHECK STATUS D 1 0 0 1 0 Xn X0 Q ADDR BUSY READY OP CODE AI00879B Note: For the meanings of An and Xn, please see Table 4, Table 5 and Table 6. Erase The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or word) to 1. Once the address has been correctly decoded, the falling edge of the Chip Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be detected by monitoring the Ready/ Busy line, as described on page 9. Write For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and address bits. These form the byte or word that is to be written. As with the other bits, Serial Data Input (D) is sampled on the rising edge of Serial Clock (C). After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. The completion of the cycle can be detected by monitoring the Ready/Busy line, as described later in this document. Once the Write cycle has been started, it is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle). The cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an explicit erase instruction before a Write Data to Memory (WRITE) instruction. Erase All The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set to 1). The format of the instruction requires that a dummy address be provided. The Erase cycle is conducted in the same way as the Erase instruction (ERASE). The completion of the cycle can be detected by monitoring the Ready/Busy line, as described on page 9. 9/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Figure 7. WRAL Sequence WRITE ALL S CHECK STATUS D 1 0 0 0 1 Xn X0 Dn D0 Q ADDR DATA IN BUSY READY OP CODE AI00880C Note: For the meanings of Xn and Dn, please see Table 4, Table 5 and Table 6. Write All As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with same Data (WRAL) instruction requires that a dummy address be provided. As with the Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided. This value is written to all the addresses of the memory device. The completion of the cycle can be detected by monitoring the Ready/Busy line, as described next. READY/BUSY STATUS While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL instruction, the Busy signal (Q=0) is returned whenever Chip Select Input (S) is driven High. (Please note, though, that there is an initial delay, of tSLSH, before this 10/30 status information becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write cycle is completed, and Chip Select Input (S) is driven High, the Ready signal (Q=1) indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q) remains set to 1 until the Chip Select Input (S) is brought Low or until a new start bit is decoded. COMMON I/O OPERATION Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a current limiting resistor, to form a common, single-wire data bus. Some precautions must be taken when operating the memory in this way, mostly to prevent a short circuit current from flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output (Q). Please see the application note AN394 for details. M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Figure 8. Write Sequence with One Clock Glitch S C D An START "0" "1" WRITE An-1 An-2 Glitch D0 ADDRESS AND DATA ARE SHIFTED BY ONE BIT AI01395 CLOCK PULSE COUNTER In a noisy environment, the number of pulses received on Serial Clock (C) may be greater than the number delivered by the master (the microcontroller). This can lead to a misalignment of the instruction of one or more bits (as shown in Figure 8) and may lead to the writing of erroneous data at an erroneous address. To combat this problem, the M93Cx6 has an onchip counter that counts the clock pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL instruction is aborted, and the contents of the memory are not modified. The number of clock cycles expected for each instruction, and for each member of the M93Cx6 family, are summarized in Table 4 to Table 6. For example, a Write Data to Memory (WRITE) instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization) from the start bit to the falling edge of Chip Select Input (S). That is: 1 Start bit + 2 Op-code bits + 9 Address bits + 8 Data bits 11/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7. Absolute Maximum Ratings Symbol TSTG Parameter Storage Temperature 1 Min. Max. Unit –65 150 °C 260 2 260 3 260 3 °C PDIP SO TSSOP TLEAD Lead Temperature during Soldering VOUT Output range (Q = VOH or Hi-Z) –0.45 VCC+0.5 V VIN Input range –0.45 VCC+1 V VCC Supply Voltage –0.3 6.5 V VESD Electrostatic Discharge Voltage (Human Body model) 4 –4000 4000 V Note: 1. 2. 3. 4. 12/30 ® Compliant with the ECOPACK 7191395 specifiication for lead-free soldering processes No longer than 10 seconds Not exceeding 250°C for more than 30 seconds, and peaking at 260°C JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure- ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8. Operating Conditions (M93Cx6) Symbol VCC Parameter Min. Max. Unit Supply Voltage 4.5 5.5 V Ambient Operating Temperature (range 6) –40 85 °C Ambient Operating Temperature (range 7) –40 105 °C Ambient Operating Temperature (range 3) –40 125 °C Min. Max. Unit Supply Voltage 2.5 5.5 V Ambient Operating Temperature (range 6) –40 85 °C Ambient Operating Temperature (range 7) –40 105 °C Ambient Operating Temperature (range 3) –40 125 °C Min. Max. Unit Supply Voltage 1.8 5.5 V Ambient Operating Temperature (range 6) –40 85 °C TA Table 9. Operating Conditions (M93Cx6-W) Symbol VCC Parameter TA Table 10. Operating Conditions (M93Cx6-R) Symbol VCC TA Parameter 13/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Table 11. AC Measurement Conditions (M93Cx6) Symbol CL Parameter Min. Max. Load Capacitance Unit 100 Input Rise and Fall Times pF 50 Input Pulse Voltages ns 0.4 V to 2.4 V V Input Timing Reference Voltages 1.0 V and 2.0 V V Output Timing Reference Voltages 0.8 V and 2.0 V V Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Table 12. AC Measurement Conditions (M93Cx6-W and M93Cx6-R) Symbol CL Parameter Min. Max. Load Capacitance Unit 100 Input Rise and Fall Times pF 50 ns Input Pulse Voltages 0.2VCC to 0.8VCC V Input Timing Reference Voltages 0.3VCC to 0.7VCC V Output Timing Reference Voltages 0.3VCC to 0.7VCC V Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 9. AC Testing Input Output Waveforms M93CXX 2.4V 2V 2.0V 1V 0.8V 0.4V INPUT OUTPUT M93CXX-W & M93CXX-R 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI02553 Table 13. Capacitance Symbol Parameter Test Condition COUT Output Capacitance VOUT = 0V CIN Input Capacitance VIN = 0V Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 1 MHz. 14/30 Min Max Unit 5 pF 5 pF M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Table 14. DC Characteristics (M93Cx6, temperature range 6) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICC Test Condition Min. Max. Unit 0V ≤ VIN ≤ VCC ±2.5 µA 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA VCC = 5V, S = VIH, f = 1 MHz, Current Product 1 1.5 mA VCC = 5V, S = VIH, f = 2 MHz, New Product 2 2 mA 50 µA 15 µA Supply Current VCC = 5V, S = VSS, C = VSS, ORG = VSS or VCC, Current Product 1 ICC1 Supply Current (Stand-by) VCC = 5V, S = VSS, C = VSS, ORG = VSS or VCC, New Product 2 VIL Input Low Voltage VCC = 5V ± 10% –0.45 0.8 V VIH Input High Voltage VCC = 5V ± 10% 2 VCC + 1 V VOL Output Low Voltage VCC = 5V, IOL = 2.1mA 0.4 V VOH Output High Voltage VCC = 5V, IOH = –400µA 2.4 V Note: 1. Current product: identified by Process Identification letter F or M. 2. New product: identified by Process Identification letter W. Table 15. DC Characteristics (M93Cx6, temperature range 7 or 3) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current Test Condition Min. Max. Unit 0V ≤ VIN ≤ VCC ±2.5 µA 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA 1.5 mA 2 mA 50 µA 15 µA VCC = 5V, S = VIH, f = 1 MHz, Current Product 1 ICC Supply Current VCC = 5V, S = VIH, f = 2 MHz, New Product 2 VCC = 5V, S = VSS, C = VSS, ORG = VSS or VCC, Current Product 1 ICC1 Supply Current (Stand-by) VCC = 5V, S = VSS, C = VSS, ORG = VSS or VCC, New Product 2 VIL Input Low Voltage VCC = 5V ± 10% –0.45 0.8 V VIH Input High Voltage VCC = 5V ± 10% 2 VCC + 1 V VOL Output Low Voltage VCC = 5V, IOL = 2.1mA 0.4 V VOH Output High Voltage VCC = 5V, IOH = –400µA 2.4 V Note: 1. Current product: identified by Process Identification letter F or M. 2. New product: identified by Process Identification letter W. 15/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Table 16. DC Characteristics (M93Cx6-W, temperature range 6) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICC Supply Current (CMOS Inputs) Test Condition Min. Max. Unit 0V ≤ VIN ≤ VCC ±2.5 µA 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA VCC = 5V, S = VIH, f = 1 MHz, Current Product 1 1.5 mA VCC = 2.5V, S = VIH, f = 1 MHz, Current Product 1 1 mA 2 mA 1 mA VCC = 2.5V, S = VSS, C = VSS, ORG = VSS or VCC, Current Product 1 10 µA VCC = 2.5V, S = VSS, C = VSS, ORG = VSS or VCC, New Product 2 5 µA VCC = 5V, S = VIH, f = 2 MHz, New Product 2 VCC = 2.5V, S = VIH, f = 2 MHz, New Product 2 ICC1 Supply Current (Stand-by) VIL Input Low Voltage (D, C, S) –0.45 0.2 VCC V VIH Input High Voltage (D, C, S) 0.7 VCC VCC + 1 V VCC = 5V, IOL = 2.1mA 0.4 V VOL Output Low Voltage (Q) VCC = 2.5V, IOL = 100µA 0.2 V VOH VCC = 5V, IOH = –400µA 2.4 V VCC = 2.5V, IOH = –100µA VCC–0.2 V Output High Voltage (Q) Note: 1. Current product: identified by Process Identification letter F or M. 2. New product: identified by Process Identification letter W. 16/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Table 17. DC Characteristics (M93Cx6-W, temperature range 7 or 3) Symbol ILI Input Leakage Current ILO Output Leakage Current ICC ICC1 Max. 1 Unit 0V ≤ VIN ≤ VCC ±2.5 µA 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA VCC = 5V, S = VIH, f = 2 MHz 2 mA VCC = 2.5V, S = VIH, f = 2 MHz 1 mA VCC = 2.5V, S = VSS, C = VSS, ORG = VSS or VCC 5 µA Parameter Supply Current (CMOS Inputs) Supply Current (Stand-by) Test Condition Min. 1 VIL Input Low Voltage (D, C, S) –0.45 0.2 VCC V VIH Input High Voltage (D, C, S) 0.7 VCC VCC + 1 V VCC = 5V, IOL = 2.1mA 0.4 V VOL Output Low Voltage (Q) VCC = 2.5V, IOL = 100µA 0.2 V VOH VCC = 5V, IOH = –400µA 2.4 V VCC = 2.5V, IOH = –100µA VCC–0.2 V Output High Voltage (Q) Note: 1. New product: identified by Process Identification letter W. Table 18. DC Characteristics (M93Cx6-R) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICC ICC1 Supply Current (CMOS Inputs) Supply Current (Stand-by) Max. 1 Unit 0V ≤ VIN ≤ VCC ±2.5 µA 0V ≤ VOUT ≤ VCC, Q in Hi-Z ±2.5 µA VCC = 5V, S = VIH, f = 2 MHz 2 mA VCC = 1.8V, S = VIH, f = 1 MHz 1 mA VCC = 1.8V, S = VSS, C = VSS, ORG = VSS or VCC 2 µA Test Condition Min. 1 VIL Input Low Voltage (D, C, S) –0.45 0.2 VCC V VIH Input High Voltage (D, C, S) 0.8 VCC VCC + 1 V VOL Output Low Voltage (Q) VCC = 1.8V, IOL = 100µA 0.2 V VOH Output High Voltage (Q) VCC = 1.8V, IOH = –100µA VCC–0.2 V Note: 1. This product is under development. For more infomation, please contact your nearest ST sales office. 17/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Table 19. AC Characteristics (M93Cx6, temperature range 6, 7 or 3) Test conditions specified in Table 11 and Table 8 Symbol Alt. fC fSK tSLCH tSHCH tCSS Min.3 Max.3 Min.4 Max.4 Unit Clock Frequency D.C. 1 D.C. 2 MHz Chip Select Low to Clock High 250 50 ns Chip Select Set-up Time M93C46, M93C56, M93C66 50 50 ns Chip Select Set-up time M93C76, M93C86 100 50 ns Parameter tSLSH2 tCS Chip Select Low to Chip Select High 250 200 ns tCHCL1 tSKH Clock High Time 250 200 ns tCLCH1 tSKL Clock Low Time 250 200 ns tDVCH tDIS Data In Set-up Time 100 50 ns tCHDX tDIH Data In Hold Time 100 50 ns tCLSH tSKS Clock Set-up Time (relative to S) 100 50 ns tCLSL tCSH Chip Select Hold Time 0 0 ns tSHQV tSV Chip Select to Ready/Busy Status 400 200 ns tSLQZ tDF Chip Select Low to Output Hi-Z 200 100 ns tCHQL tPD0 Delay to Output Low 400 200 ns tCHQV tPD1 Delay to Output Valid 400 200 ns tW tWP Erase/Write Cycle time 10 5 ms Note: 1. 2. 3. 4. 18/30 tCHCL + tCLCH ≥ 1 / fC. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. Current product: identified by Process Identification letter F or M. New product: identified by Process Identification letter W. M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Table 20. AC Characteristics (M93Cx6-W, temperature range 6) Test conditions specified in Table 12 and Table 9 Symbol Alt. fC fSK tSLCH Min.3 Max.3 Min.4 Max.4 Unit Clock Frequency D.C. 1 D.C. 2 MHz Chip Select Low to Clock High 250 50 ns 100 50 ns 1000 200 ns Parameter tSHCH tCSS Chip Select Set-up Time tSLSH2 tCS Chip Select Low to Chip Select High tCHCL1 tSKH Clock High Time 350 200 ns tCLCH1 tSKL Clock Low Time 250 200 ns tDVCH tDIS Data In Set-up Time 100 50 ns tCHDX tDIH Data In Hold Time 100 50 ns tCLSH tSKS Clock Set-up Time (relative to S) 100 50 ns tCLSL tCSH Chip Select Hold Time 0 0 ns tSHQV tSV Chip Select to Ready/Busy Status 400 200 ns tSLQZ tDF Chip Select Low to Output Hi-Z 200 100 ns tCHQL tPD0 Delay to Output Low 400 200 ns tCHQV tPD1 Delay to Output Valid 400 200 ns tW tWP Erase/Write Cycle time 10 5 ms Note: 1. 2. 3. 4. tCHCL + tCLCH ≥ 1 / fC. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. Current product: identified by Process Identification letter F or M. New product: identified by Process Identification letter W. 19/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Table 21. AC Characteristics (M93Cx6-W, temperature range 7 or 3) Test conditions specified in Table 12 and Table 9 Symbol Alt. fC fSK tSLCH Parameter Clock Frequency Min.3 Max.3 Unit D.C. 2 MHz Chip Select Low to Clock High 50 ns tSHCH tCSS Chip Select Set-up Time 50 ns tSLSH2 tCS Chip Select Low to Chip Select High 200 ns tCHCL1 tSKH Clock High Time 200 ns tCLCH1 tSKL Clock Low Time 200 ns tDVCH tDIS Data In Set-up Time 50 ns tCHDX tDIH Data In Hold Time 50 ns tCLSH tSKS Clock Set-up Time (relative to S) 50 ns tCLSL tCSH Chip Select Hold Time 0 ns tSHQV tSV Chip Select to Ready/Busy Status 200 ns tSLQZ tDF Chip Select Low to Output Hi-Z 100 ns tCHQL tPD0 Delay to Output Low 200 ns tCHQV tPD1 Delay to Output Valid 200 ns tW tWP Erase/Write Cycle time 5 ms Note: 1. tCHCL + tCLCH ≥ 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. 3. New product: identified by Process Identification letter W. 20/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Table 22. AC Characteristics (M93Cx6-R) Test conditions specified in Table 12 and Table 10 Symbol Alt. fC fSK tSLCH Min.3 Max.3 Unit Clock Frequency D.C. 1 MHz Chip Select Low to Clock High 250 ns Parameter tSHCH tCSS Chip Select Set-up Time 50 ns tSLSH2 tCS Chip Select Low to Chip Select High 250 ns tCHCL1 tSKH Clock High Time 250 ns tCLCH1 tSKL Clock Low Time 250 ns tDVCH tDIS Data In Set-up Time 100 ns tCHDX tDIH Data In Hold Time 100 ns tCLSH tSKS Clock Set-up Time (relative to S) 100 ns tCLSL tCSH Chip Select Hold Time 0 ns tSHQV tSV Chip Select to Ready/Busy Status 400 ns tSLQZ tDF Chip Select Low to Output Hi-Z 200 ns tCHQL tPD0 Delay to Output Low 400 ns tCHQV tPD1 Delay to Output Valid 400 ns tW tWP Erase/Write Cycle time 10 ms Note: 1. tCHCL + tCLCH ≥ 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. 3. This product is under development. For more infomation, please contact your nearest ST sales office. 21/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Figure 10. Synchronous Timing (Start and Op-Code Input) tCLSH tCHCL C tSHCH tCLCH S tDVCH D tCHDX OP CODE START START OP CODE OP CODE INPUT AI01428 Figure 11. Synchronous Timing (Read or Write) C tCLSL S tDVCH tCHDX tSLSH A0 An D tCHQV tSLQZ tCHQL Hi-Z Q15/Q7 Q ADDRESS INPUT Q0 DATA OUTPUT AI00820C Figure 12. Synchronous Timing (Read or Write) tSLCH C tCLSL S tDVCH An D tCHDX tSLSH A0/D0 tSHQV tSLQZ Hi-Z BUSY Q READY tW ADDRESS/DATA INPUT WRITE CYCLE AI01429 22/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 PACKAGE MECHANICAL Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline E b2 A2 A1 b A L c e eA eB D 8 E1 1 PDIP-B Notes: 1. Drawing is not to scale. Table 23. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data mm inches Symb. Typ. Min. A Max. Typ. Min. 5.33 A1 Max. 0.210 0.38 0.015 A2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 D 9.27 9.02 10.16 0.365 0.355 0.400 E 7.87 7.62 8.26 0.310 0.300 0.325 E1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 – – 0.100 – – eA 7.62 – – 0.300 – – eB L 10.92 3.30 2.92 3.81 0.430 0.130 0.115 0.150 23/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline h x 45˚ A C B CP e D N E H 1 A1 α L SO-a Note: Drawing is not to scale. Table 24. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data mm inches Symb. Typ. Min. Max. A 1.35 A1 Min. Max. 1.75 0.053 0.069 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 – – – – H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 0.90 0.016 0.035 α 0° 8° 0° 8° N 8 e CP 24/30 1.27 Typ. 0.050 8 0.10 0.004 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Figure 15. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline D 8 5 c E1 1 E 4 α A1 A L A2 L1 CP b e TSSOP8BM Notes: 1. Drawing is not to scale. Table 25. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Mechanical Data mm inches Symbol Typ. Min. A Max. Min. 1.100 A1 0.050 0.150 0.750 0.950 b 0.250 c A2 Typ. 0.850 Max. 0.0433 0.0020 0.0059 0.0295 0.0374 0.400 0.0098 0.0157 0.130 0.230 0.0051 0.0091 0.0335 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 E 4.900 4.650 5.150 0.1929 0.1831 0.2028 E1 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 – – 0.0256 – – CP 0.100 L 0.550 L1 0.950 α 0.400 0.700 0.0039 0.0217 0.0157 0.0276 0° 6° 0.0374 0° 6° 25/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Figure 16. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline D 8 5 c E1 1 E 4 α L A1 A A2 L1 CP b e TSSOP8AM Notes: 1. Drawing is not to scale. Table 26. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data mm inches Symbol Typ. Min. A 0.050 0.150 0.800 1.050 b 0.190 c 0.090 A2 Typ. Min. 1.200 A1 1.000 CP Max. 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.100 0.0039 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 – – 0.0256 – – E 6.400 6.200 6.600 0.2520 0.2441 0.2598 E1 4.400 4.300 4.500 0.1732 0.1693 0.1772 L 0.600 0.450 0.750 0.0236 0.0177 0.0295 L1 1.000 0° 8° α 26/30 Max. 0.0394 0° 8° M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 PART NUMBERING Table 27. Ordering Information Scheme Example: M93C86 – T W MN 6 T P Device Type M93 = MICROWIRE serial access EEPROM Device Function 86 = 16 Kbit (2048 x 8) 76 = 8 Kbit (1024 x 8) 66 = 4 Kbit (512 x 8) 56 = 2 Kbit (256 x 8) 46 = 1 Kbit (128 x 8) 062 = 256 bit (32 x 8) Turned Die blank = Normal (unturned) Die T4 = 90° Turned Die Operating Voltage blank = VCC = 4.5 to 5.5V W = VCC = 2.5 to 5.5V R = VCC = 1.8 to 5.5V Package BN = PDIP8 MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) DS3 = TSSOP8 (3x3mm body size) Temperature Range 6 = –40 to 85 °C 71 = –40 to 105 °C 31 = –40 to 125 °C Option blank = Standard Packing T = Tape & Reel Packing Plating Technology blank = Standard SnPb plating P = Pb-Free, RoHS compliant G = Green package Note: 1. 2. 3. 4. Produced with High Reliability Certified Flow (HRCF). M93C06 is “Not for New Design”. Available only on new products: identified by the Process Identification letter W. Turned die option is not available for all devices. Please contact your nearest STMicroelectronics Sales Office. Devices are shipped from the factory with the memory content set at all 1s (FFFFh for x16, FFh for x8). For a list of available options (speed, package, etc.) or for further information on any aspect of this 27/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 device, please contact your nearest ST Sales Office. Table 28. How to Identify Current and New Products by the Process Identification Letter Markings on Current Products1 Markings on New Products1 M93C46W6 AYWWF (or AYWWM) M93C46W6 AYWWW Note: 1. This example comes from the S08 package. Other packages have similar information. For further information, please ask your ST Sales Office for Process Change Notice PCN MPG/EE/0059 (PCEE0059). 28/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 REVISION HISTORY Table 29. Document Revision History Date Rev. Description of Revision 04-Feb-2003 2.0 Document reformatted, and reworded, using the new template. Temperature range 1 removed. TSSOP8 (3x3mm) package added. New products, identified by the process letter W, added, with fc(max) increased to 1MHz for -R voltage range, and to 2MHz for all other ranges (and corresponding parameters adjusted) 26-Mar-2003 2.1 Value of standby current (max) corrected in DC characteristics tables for -W and -R ranges VOUT and VIN separated from VIO in the Absolute Maximum Ratings table 04-Apr-2003 2.2 Values corrected in AC characteristics tables for -W range (tSLSH, tDVCH, tCLSL) for devices with Process Identification Letter W 23-May-2003 2.3 Standby current corrected for -R range 27-May-2003 2.4 Turned die option re-instated in Ordering Information Scheme 25-Nov-2003 3.0 Table of contents, and Pb-free options added. Temperature range 7 added. VIL(min) improved to -0.45V. 29/30 M93C86, M93C76, M93C66, M93C56, M93C46, M93C06 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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