M93Cx6-A125
Automotive 16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit
(8-bit or 16-bit wide) MICROWIRE™ serial EEPROM
Datasheet - production data
Features
• Industry standard MICROWIRE™ bus
• Memory array: 1 Kb, 2 Kb, 4 Kb, 8 Kb or 16 Kb
• Dual organization: by word (x16) or byte (x8)
SO8 (MN)
150 mil width
• Write
– Byte within 4 ms
– Word within 4 ms
• READY/BUSY signal during programming
• 2 MHz clock rate
• Sequential read operation
TSSOP8 (DW)
169 mil width
• Single supply voltage: 1.8 V to 5.5 V
• Operating temperature range: -40 °C up to
125 °C
• Enhanced ESD protection
WFDFPN8 (MF)
2 x 3 mm
• Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 600 k Write cycles at 125 °C
• Data retention
– 50 years at 125 °C
– more than 100 years at 25 °C
• Packages
– RoHS-compliant and Halogen-free
(ECOPACK2®)
Table 1. Device summary
Reference
M93Cx6-A125
January 2015
This is information on a product in full production.
DocID024752 Rev 5
Part number
M93C46-A125
M93C56-A125
M93C66-A125
M93C76-A125
M93C86-A125
1/31
www.st.com
Contents
M93Cx6-A125
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1
Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.2
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.3
Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.4
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1
Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2
Erase and Write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1
Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.2
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.3
Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2.4
ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 15
5.2.5
Erase Byte or Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.6
Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8
Common I/O operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9
Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Contents
12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
13
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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3
List of tables
M93Cx6-A125
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
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Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Instruction set for the M93Cx6-A125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Instruction set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Instruction set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Instruction set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operating conditions (M93Cx6-A125) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Input and output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Cycling performance by byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 26
WFDFPN8 (MLP8) – 8-lead very thin fine pitch dual flat package no lead
2 x 3 mm, 0.5 mm pitch, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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M93Cx6-A125
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
M93Cx6-A125 ORG input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
READ, WRITE, WEN, WDS sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WRAL sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ERASE, ERAL sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Synchronous timing (Start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Synchronous timing (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Synchronous timing (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 26
WFDFPN8 (MLP8) – 8-lead very thin fine pitch dual flat package no lead
2 x 3 mm, 0.5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Description
1
M93Cx6-A125
Description
The M93C46 (1 Kbit), M93C56 (2 Kbit), M93C66 (4 Kbit), M93C76 (8 Kbit) and M93C86
(16 Kbit) are Electrically Erasable PROgrammable Memory (EEPROM) devices accessed
through the MICROWIRE™ bus protocol. The memory array can be configured either in
bytes (x8b) or in words (x16b).
The M93Cx6-A125 devices operate within a voltage supply range from 1.8 V to 5.5 V
The M93Cx6-A125 devices are guaranteed over the -40 °C/+125 °C temperature range and
are compliant with the Automotive standard AEC-Q100 Grade 1.
Table 2. Memory size versus organization
Device
Number of bits
Number of 8-bit bytes
Number of 16-bit words
M93C86
16384
2048
1024
M93C76
8192
1024
512
M93C66
4096
512
256
M93C56
2048
256
128
M93C46
1024
128
64
Figure 1. Logic diagram
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Table 3. Signal names
Signal name
6/31
Function
Direction
S
Chip Select
Input
D
Serial Data input
Input
Q
Serial Data output
Output
C
Serial Clock
Input
ORG
Organization Select
Input
VCC
Supply voltage
-
VSS
Ground
-
DocID024752 Rev 5
M93Cx6-A125
Description
The M93Cx6-A125 is accessed by a set of instructions, as summarized in Table 4, and in
more detail in Table 5: Instruction set for the M93C46 to Table 7: Instruction set for the
M93C76 and M93C86).
Table 4. Instruction set for the M93Cx6-A125
Instruction
Description
Data
READ
Read Data from Memory
Byte or Word
WRITE
Write Data to Memory
Byte or Word
WEN
Write Enable
-
WDS
Write Disable
-
ERASE
Erase Byte or Word
Byte or Word
ERAL
Erase All Memory
-
WRAL
Write All Memory with same Data
-
A Read Data from Memory (READ) instruction loads the address of the first byte or word to
be read in an internal address register. The data at this address is then clocked out serially.
The address register is automatically incremented after the data is output and, if Chip Select
Input (S) is held High, the M93Cx6-A125 can output a sequential stream of data bytes or
words. In this way, the memory can be read as a data stream from eight to 16384 bits long
(in the case of the M93C86), or continuously (the address counter automatically rolls over to
00h when the highest address is reached).
Programming is internally self-timed (the external clock signal on Serial Clock (C) may be
stopped or left running after the start of a Write cycle) and does not require an Erase cycle
prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the
byte or word locations of the M93Cx6-A125. After the start of the programming cycle, a
Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is
driven High. An internal Power-on Data Protection mechanism in the M93Cx6-A125 inhibits
the device when the supply is too low.
Figure 2. 8-pin package connections (top view)
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1. See Section 12: Package mechanical data for package dimensions, and how to identify pin-1.
2. DU = Don’t Use. The DU (do not use) pin does not contribute to the normal operation of the device. It is
reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be
connected to VCC or VSS.
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Connecting to the serial bus
2
M93Cx6-A125
Connecting to the serial bus
Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus.
Only one device is selected at a time, so only one device drives the Serial Data output (Q)
line at a time, the other devices are high impedance.
The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master may be in a state where all inputs/outputs are high
impedance at the same time (for example, if the bus master is reset during the transmission
of an instruction), the clock line (C) must be connected to an external pull-down resistor so
that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is
pulled low): this ensures that C does not become high at the same time as S goes low, and
so, that the tSLCH requirement is met. The typical value of R is 100 kΩ.
Figure 3. Bus master and memory devices on the serial bus
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M93Cx6-A125
Operating features
3
Operating features
3.1
Supply voltage (VCC)
3.1.1
Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied. In order to secure a stable
DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor
(usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
3.1.2
Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip
Select (S) line is not allowed to float and should be driven to VSS, it is therefore
recommended to connect the S line to VSS via a suitable pull-down resistor.
3.1.3
Power-up and device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of VCC), the device does not respond to any
instruction until VCC has reached the power on reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Operating conditions, in
Section 11: DC and AC parameters).
When VCC passes the POR threshold, the device is reset and is in the following state:
3.1.4
•
Standby Power mode
•
deselected (assuming that there is a pull-down resistor on the S line)
Power-down
At power-down (continuous decrease in VCC), as soon as VCC drops from the normal
operating voltage to below the power on reset threshold voltage, the device stops
responding to any instruction sent to it.
During power-down, the device must be deselected and in the Standby Power mode (that is,
there should be no internal Write cycle in progress).
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Memory organization
4
M93Cx6-A125
Memory organization
The M93Cx6-A125 memory is organized either as bytes (x8) or as words (x16). If
Organization Select (ORG) is left unconnected (or connected to VCC) the x16 organization is
selected; when Organization Select (ORG) is connected to Ground (VSS) the x8
organization is selected. When the M93Cx6-A125 is in Standby mode, Organization Select
(ORG) should be set either to VSS or VCC to reach the device minimum power consumption
(as any voltage between VSS and VCC applied to ORG input may increase the device
Standby current).
Figure 4. M93Cx6-A125 ORG input connection
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M93Cx6-A125
5
Instructions
Instructions
The instruction set of the M93Cx6-A125 devices contains seven instructions, as
summarized in Table 5 to Table 7. Each instruction consists of the following parts, as shown
in Figure 5: READ, WRITE, WEN, WDS sequences:
•
Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock
(C) being held low.
•
A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of
Serial Clock (C).
•
Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock
(C). (Some instructions also use the first two bits of the address to define the op-code).
•
The address bits of the byte or word that is to be accessed. For the M93C46, the
address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization
(see Table 5). For the M93C56 and M93C66, the address is made up of 8 bits for the
x16 organization or 9 bits for the x8 organization (see Table 6). For the M93C76 and
M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8
organization (see Table 7).
The M93Cx6-A125 devices are fabricated in CMOS technology and are therefore able to
run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in “AC
characteristics” tables, in Section 11: DC and AC parameters.
Table 5. Instruction set for the M93C46
x8 origination (ORG = 0)
Instruction
Description
Start
bit
Opcode
Address
(1)
Data
x16 origination (ORG = 1)
Required
Address
clock
(1)
cycles
Data
Required
clock
cycles
READ
Read Data from
Memory
1
10
A6-A0
Q7-Q0
-
A5-A0
Q15-Q0
-
WRITE
Write Data to
Memory
1
01
A6-A0
D7-D0
18
A5-A0
D15-D0
25
WEN
Write Enable
1
00
11X XXXX
-
10
11 XXXX
-
9
WDS
Write Disable
1
00
00X
XXXX
-
10
00 XXXX
-
9
ERASE
Erase Byte or
Word
1
11
A6-A0
-
10
A5-A0
-
9
ERAL
Erase All Memory
1
00
10X
XXXX
-
10
10 XXXX
-
9
WRAL
Write All Memory
with same Data
1
00
01X
XXXX
D7-D0
18
01 XXXX D15-D0
25
1. X = Don't Care bit.
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Instructions
M93Cx6-A125
Table 6. Instruction set for the M93C56 and M93C66
Instruction
x8 origination (ORG = 0)
x16 origination (ORG = 1)
OpStart
Required
Required
cod
Address
Address
bit
Data
clock
Data
clock
e
(1) (2)
(1) (3)
cycles
cycles
Description
READ
Read Data from Memory
1
10
A8-A0
Q7Q0
-
A7-A0
Q15Q0
-
WRITE
Write Data to Memory
1
01
A8-A0
D7D0
20
A7-A0
D15-D0
27
WEN
Write Enable
1
00
1 1XXX
XXXX
-
12
11XX
XXXX
-
11
WDS
Write Disable
1
00
0 0XXX
XXXX
-
12
00XX
XXXX
-
11
ERASE
Erase Byte or Word
1
11
A8-A0
-
12
A7-A0
-
11
ERAL
Erase All Memory
1
00
1 0XXX
XXXX
-
12
10XX
XXXX
-
11
WRAL
Write All Memory with
same Data
1
00
0 1XXX
XXXX
D7D0
20
01XX
XXXX
D15-D0
27
1. X = Don't Care bit.
2. Address bit A8 is not decoded by the M93C56.
3. Address bit A7 is not decoded by the M93C56.
Table 7. Instruction set for the M93C76 and M93C86
x8 Origination (ORG = 0)
Instruction
Description
Start Opbit code
Address
(1)(2)
Data
x16 Origination (ORG = 1)
Required
Address
clock
(1) (3)
cycles
Data
Required
clock
cycles
READ
Read Data from
Memory
1
10
A10-A0
Q7-Q0
-
A9-A0
Q15-Q0
-
WRITE
Write Data to
Memory
1
01
A10-A0
D7-D0
22
A9-A0
D15-D0
29
WEN
Write Enable
1
00
11X XXXX
XXXX
-
14
11 XXXX
XXXX
-
13
WDS
Write Disable
1
00
00X XXXX
XXXX
-
14
00 XXXX
XXXX
-
13
ERASE
Erase Byte or Word
1
11
A10-A0
-
14
A9-A0
-
13
ERAL
Erase All Memory
1
00
10X XXXX
XXXX
-
14
10 XXXX
XXXX
-
13
WRAL
Write All Memory
with same Data
1
00
01X XXXX
XXXX
D7-D0
22
01 XXXX
D15-D0
XXXX
1. X = Don't Care bit.
2. Address bit A10 is not decoded by the M93C76.
3. Address bit A9 is not decoded by the M93C76.
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M93Cx6-A125
5.1
Instructions
Read Data from Memory
The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q).
When the instruction is received, the op-code and address are decoded, and the data from
the memory is transferred to an output shift register. A dummy 0 bit is output first, followed
by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are
triggered by the rising edge of Serial Clock (C). The M93Cx6-A125 automatically increments
the internal address register and clocks out the next byte (or word) as long as the Chip
Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or
words) and a continuous stream of data can be read (the address counter automatically rolls
over to 00h when the highest address is reached).
5.2
Erase and Write data
5.2.1
Write Enable and Write Disable
The Write Enable (WEN) instruction enables the future execution of erase or write
instructions, and the Write Disable (WDS) instruction disables it. When power is first
applied, the M93Cx6-A125 initializes itself so that erase and write instructions are disabled.
After a Write Enable (WEN) instruction has been executed, erasing and writing remains
enabled until a Write Disable (WDS) instruction is executed, or until VCC falls below the
power-on reset threshold voltage. To protect the memory contents from accidental
corruption, it is advisable to issue the Write Disable (WDS) instruction after every write
cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable
(WEN) or Write Disable (WDS) instructions.
5.2.2
Write
For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and
address bits. These form the byte or word that is to be written. As with the other bits, Serial
Data Input (D) is sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after
this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed. The completion of the cycle can be detected by
monitoring the READY/BUSY line, as described later in this document.
Once the Write cycle has been started, it is internally self-timed (the external clock signal on
Serial Clock (C) may be stopped or left running after the start of a Write cycle). The Write
cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an
explicit erase instruction before a Write Data to Memory (WRITE) instruction.
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Instructions
M93Cx6-A125
Figure 5. READ, WRITE, WEN, WDS sequences
2EAD
3
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1. For the meanings of An, Xn, Qn and Dn, see Table 5, Table 6 and Table 7.
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M93Cx6-A125
5.2.3
Instructions
Write All
As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with
same Data (WRAL) instruction requires that a dummy address be provided. As with the
Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same
Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided.
This value is written to all the addresses of the memory device. The completion of the cycle
can be detected by monitoring the READY/BUSY line, as described next.
Figure 6. WRAL sequence
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3
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1
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1. For the meanings of Xn and Dn, please see Table 5, Table 6 and Table 7.
5.2.4
ECC (Error Correction Code) and Write cycling
The devices identified with the Process letter “K” embed an Error Correction Code (ECC)
internal logic function which is transparent for the Microwire communication protocol.
The ECC logic is implemented on each byte.
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Instructions
5.2.5
M93Cx6-A125
Erase Byte or Word
The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be
detected by monitoring the READY/BUSY line, as described in Section 6: READY/BUSY
status.
Figure 7. ERASE, ERAL sequences
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3
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3
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1. For the meanings of An and Xn, please see Table 5, Table 6 and Table 7.
5.2.6
Erase All
The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/BUSY line, as described in Section 6:
READY/BUSY status.
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M93Cx6-A125
6
READY/BUSY status
READY/BUSY status
While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL
instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.
(Please note, though, that there is an initial delay, of tSLSH, before this status information
becomes available). In this state, the M93Cx6-A125 ignores any data on the bus. When the
Write cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)
indicates that the M93Cx6-A125 is ready to receive the next instruction. Serial Data Output
(Q) remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is
decoded.
7
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
8
Common I/O operation
Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a
current limiting resistor, to form a common, single-wire data bus. Some precautions must be
taken when operating the memory in this way, mostly to prevent a short circuit current from
flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output
(Q). Please see the application note AN394 for details.
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Clock pulse counter
9
M93Cx6-A125
Clock pulse counter
In a noisy environment, the number of pulses received on Serial Clock (C) may be greater
than the number delivered by the master (the microcontroller). This can lead to a
misalignment of the instruction of one or more bits (as shown in Figure 8) and may lead to
the writing of erroneous data at an erroneous address.
To avoid this problem, the M93Cx6-A125 has an on-chip counter that counts the clock
pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of
clock pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL
instruction is aborted, and the contents of the memory are not modified.
The number of clock cycles expected for each instruction, and for each member of the
M93Cx6-A125 family, are summarized in Table 5: Instruction set for the M93C46 to Table 7:
Instruction set for the M93C76 and M93C86. For example, a Write Data to Memory (WRITE)
instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization)
from the start bit to the falling edge of Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 9 Address bits
+ 8 Data bits
Figure 8. Write sequence with one clock glitch
3
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!N
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DocID024752 Rev 5
M93Cx6-A125
10
Maximum ratings
Maximum ratings
Stressing the device outside the ratings listed in the Absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these, or any other conditions outside those indicated in the operating sections of
this specification, is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 8. Absolute maximum ratings
Symbol
TSTG
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
(1)
TLEAD
Lead temperature during soldering
VOUT
Output range (Q = VOH or Hi-Z)
–0.50
VCC+0.5
V
VIN
Input range
–0.50
VCC+1
V
VCC
Supply voltage
–0.50
6.5
V
-
4000
V
VESD
Electrostatic discharge voltage (human body
See note
model)(2)
°C
1. Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS
directive 2011/65/EU of July 2011).
2. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with
ANSI/ESDA/JEDEC JS-001-2012), C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
DocID024752 Rev 5
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DC and AC parameters
11
M93Cx6-A125
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 9. Operating conditions (M93Cx6-A125)
Symbol
VCC
TA
Parameter
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
125
°C
Table 10. AC measurement conditions
Symbol
Parameter
Min.
Max.
Load capacitance
CL
Unit
100
-
pF
-
Input rise and fall times
50
ns
-
Input voltage levels
0.2 VCC to 0.8 VCC
V
-
Input timing reference voltages
0.3 VCC to 0.7 VCC
V
-
Output timing reference voltages
0.3 VCC to 0.7 VCC
V
Figure 9. AC testing input output waveforms
-#88
9&&
9&&
)NPUTVOLTAGELEVELS
9&&
9&&
)NPUTANDOUTPUT
TIMINGREFERENCELEVELS
-36
Table 11. Input and output capacitance
Symbol
COUT
CIN
Test condition(1)
Min
Max
Unit
VOUT = 0V
-
8
pF
VIN = 0V
-
6
pF
Min.
Max.
Unit
TA ≤ 25 °C, 1.8 V < VCC < 5.5 V
-
4,000,000
TA = 85 °C, 1.8 V < VCC < 5.5 V
-
1,200,000
TA = 125 °C, 1.8 V < VCC < 5.5 V
-
600,000
Parameter
Output capacitance
Input capacitance
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 1 MHz.
Table 12. Cycling performance by byte
Symbol
Parameter
Ncycle
Write cycle
endurance
Test condition
Write
cycle(1)
1. A Write cycle is executed when either a Write, a Write All, an Erase or an Erase All instruction is decoded.
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M93Cx6-A125
DC and AC parameters
Table 13. DC characteristics
Symbol
Parameter
Test conditions
(in addition to conditions specified
in Table 9)
Min.
Max.
ILI
Input leakage current
VIN = VSS or VCC
-
2
ILO
Output leakage current
S = VCC, VOUT = VSS or VCC
-
2
VCC = 1.8 V, C = 0.1 VCC/0.9 VCC,
Q = open, fC = 2 MHz
-
1
VCC = 2.5 V, C = 0.1 VCC/0.9 VCC,
Q = open, fC = 2 MHz
-
1
VCC = 5.5 V, fC = 2 MHz
C = 0.1 VCC/0.9 VCC, Q = open
-
1.5
1.8 V ≤ VCC < 5.5 V during tW,
S = VCC
-
1.5
t° = 85 °C, VCC = 1.8 V,
S = VCC, VIN = VSS or VCC
-
1
t° = 85 °C, VCC = 2.5 V,
S = VCC, VIN = VSS or VCC
-
2
t° = 85 °C, VCC = 5.5 V,
S = VCC, VIN = VSS or VCC
-
3
t° = 125 °C, VCC = 1.8 V,
S = VCC, VIN = VSS or VCC
-
15
t° = 125 °C, VCC = 2.5 V,
S = VCC, VIN = VSS or VCC
-
15
t° = 125 °C, VCC = 5.5 V,
S = VCC, VIN = VSS or VCC
-
15
1.8 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
2.5 V ≤ VCC < 5.5 V
–0.45
0.3 VCC
1.8 V ≤ VCC < 2.5 V
0.75 VCC
VCC+1
2.5 V ≤ VCC < 5.5 V
0.7 VCC
VCC+1
VCC = 1.8 V, IOL = 1 mA
-
0.3
VCC ≥ 2.5 V, IOL = 2.1 mA
-
0.4
VCC = 1.8 V, IOH = 1 mA
0.8 VCC
-
VCC ≥ 2.5 V, IOH = -2.1 mA
0.8 VCC
-
0.5
1.5
ICC
ICC0(1)
ICC1
Supply current (Read)
Supply current (Write)
Supply current (Standby mode)
VIL
Input low voltage (D, C, S)
VIH
Input high voltage (D, C, S)
VOL
Output low voltage
VOH
Output high voltage
VRES
Internal reset threshold voltage
-
Unit
µA
mA
mA
µA
V
V
V
V
V
1. Average value during the Write cycle (tW)
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DC and AC parameters
M93Cx6-A125
Table 14. AC characteristics
Test conditions specified in Table 9 and Table 10
Symbol
Alt.
fC
fSK
tSLCH
Parameter
Min.
Max.
Unit
D.C.
2
MHz
Chip Select low to Clock high
50
-
ns
Clock frequency
tSHCH
tCSS
Chip Select set-up time
50
-
ns
tSLSH(1)
tCS
Chip Select low to Chip Select high
200
-
ns
tCHCL
(2)
tSKH
Clock high time
200
-
ns
tCLCH
(2)
tSKL
Clock low time
200
-
ns
tDVCH
tDIS
Data in set-up time
50
-
ns
tCHDX
tDIH
Data in hold time
50
-
ns
tCLSH
tSKS
Clock set-up time (relative to S)
50
-
ns
tCLSL
tCSH
Chip Select hold time
0
-
ns
tSHQV
tSV
Chip Select to READY/BUSY status
-
200
ns
tSLQZ(3)
tDF
Chip Select low to output Hi-Z (VCC>2.5 V)
-
100
ns
Chip Select low to output Hi-Z (VCC
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