M93C86-MN6T

M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Datasheet 16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit (8-bit or 16-bit wide) MICROWIRE™ serial access EEPROM Features • • SO8N (150 mil width) TSSOP8 (169 mil width) • • • • • • • • • Industry standard MICROWIRE™ bus Single supply voltage: – 2.5 V to 5.5 V for M93Cx6-W – 1.8 V to 5.5 V for M93Cx6-R Dual organization: by word (x16) or byte (x8) Programming instructions that work on: byte, word or entire memory Self-timed programming cycle with auto-erase: 5 ms READY/BUSY signal during programming 2 MHz clock rate Sequential read operation Enhanced ESD/latch-up behavior More than 4 million write cycles More than 200-year data retention Package UFDFPN8 (DFN8) (2 x 3 mm) • ECOPACK2 (RoHS compliant) and halogen-free packages: – DFN8 – SO8N – TSSOP8 Product status link M93C46-W M93C56-W M93C56-R M93C66-W M93C66-R M93C76-W M93C76-R M93C86-W M93C86-R DS1077 - Rev 19 - July 2022 For further information contact your local STMicroelectronics sales office. www.st.com M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Description 1 Description The M93C46 (1 Kbit), M93C56 (2 Kbit), M93C66 (4 Kbit), M93C76 (8 Kbit) and M93C86 (16 Kbit) are electrically erasable programmable memory (EEPROM) devices accessed through the MICROWIRE™ bus protocol. The memory array can be configured either in bytes (x8b) or in words (x16b). The M93Cx6-W devices operate within a voltage supply range from 2.5 V to 5.5 V and the M93Cx6-R devices operate within a voltage supply range from 1.8 V to 5.5 V. All these devices operate with a clock frequency of 2 MHz (or less), over an ambient temperature range of - 40 ° C / + 85 ° C. Table 1. Memory size versus organization Device Number of bits Number of 8-bit bytes Number of 16-bit words M93C86 16384 2048 1024 M93C76 8192 1024 512 M93C66 4096 512 256 M93C56 2048 256 128 M93C46 1024 128 64 Figure 1. Logic diagram VCC D Q C M93Cx6 S ORG VSS MS69281V1 Table 2. Signal names Signal name DS1077 - Rev 19 Function Direction S Chip Select Input D Serial Data input Input Q Serial Data output Output C Serial Clock Input ORG Organization Select Input VCC Supply voltage - VSS Ground - page 2/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Description Figure 2. 8-pin package connections (top view) M93Cx6 S 1 8 VCC C 2 7 DU D 3 6 ORG Q 4 5 VSS MS69284V1 1. 2. DS1077 - Rev 19 See Section 11 Package information for package dimensions, and how to identify pin-1. DU = Don't use. The DU (do not use) pin does not contribute to the normal operation of the device. It is reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be connected to VCC or VSS. page 3/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Connecting to the serial bus 2 Connecting to the serial bus Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus. Only one device is selected at a time, so only one device drives the Serial data output (Q) line at a time, the other devices are high impedance. The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the bus master leaves the S line in the high impedance state. In applications where the bus master can enter a state where all input/outputs are high-impedance at a given time (for example, if the bus master is reset during the transmission of an instruction), it is advised to connect the clock line (C) to an external pull-down resistor so that, if all inputs/outputs become high-impedance, the C line is pulled low (while the S line is pulled low). This ensures that S and C do not become high at the same time, and the tSLCH requirement is met. The typical value of R is 100 kΩ. Figure 3. Bus master and memory devices on the serial bus VCC VSS R SDO SDI SCK C Q D VCC C Q D C VCC Q D VCC Bus master VSS R M93xxx memory device R VSS M93xxx memory device R VSS M93xxx memory device CS3 CS2 CS1 S ORG S ORG S ORG AI14377b DS1077 - Rev 19 page 4/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Operating features 3 Operating features 3.1 Supply voltage (VCC) 3.1.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied. In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). 3.1.2 Power-up conditions When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float and should be driven to VSS, it is therefore recommended to connect the S line to VSS via a suitable pull-down resistor. 3.1.3 Power-up and device reset In order to prevent inadvertent Write operations during power-up, a power on reset (POR) circuit is included. At power-up (continuous rise of VCC), the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Operating conditions, in Section 10 DC and AC parameters). When VCC passes the POR threshold, the device is reset and is in the following state: • • 3.1.4 Standby power mode Deselected (assuming that there is a pull-down resistor on the S line) Power-down At power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it. During power-down, the device must be deselected and in the Standby Power mode (that is, there should be no internal Write cycle in progress). DS1077 - Rev 19 page 5/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Memory organization 4 Memory organization The M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization Select (ORG) is left unconnected (or connected to VCC) the x16 organization is selected; when Organization Select (ORG) is connected to Ground (VSS) the x8 organization is selected. When the M93Cx6 is in Standby mode, Organization Select (ORG) should be set either to VSS or VCC to reach the device minimum power consumption (as any voltage between VSS and VCC applied to ORG input may increase the device Standby current). Figure 4. M93Cx6 ORG input connection Vcc Vcc ORG ORG Vss x16 organization Vcc Vss x16 organization Not connected ORG Vss x8 organization MSv31690V2 DS1077 - Rev 19 page 6/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Instructions 5 Instructions The instruction set of the M93Cx6 devices contains seven instructions, as summarized in Table 3 to Table 5. Each instruction consists of the following parts, as shown in Figure 5. READ, WRITE, WEN, WDS sequences: • Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock (C) being held low. • A start bit, which is the first '1' read on Serial Data Input (D) during the rising edge of Serial Clock (C). • Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code). • The address bits of the byte or word that is to be accessed. For the M93C46, the address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization (see Table 3). For the M93C56 and M93C66, the address is made up of 8 bits for the x16 organization or 9 bits for the x8 organization (see Table 4). For the M93C76 and M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8 organization (see Table 5). The M93Cx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in "AC characteristics" tables, in Section 10 DC and AC parameters. Table 3. Instruction set for the M93C46 x8 origination (ORG = 0) Instruction Description Start bit Op-code x16 origination (ORG = 1) Address(1) Data Required clock cycles Address(1) Data Required clock cycles READ Read Data from Memory 1 10 A6-A0 Q7-Q0 - A5-A0 Q15-Q0 - WRITE Write Data to Memory 1 01 A6-A0 D7-D0 18 A5-A0 D15-D0 25 WEN Write Enable 1 00 11X XXXX - 10 11 XXXX - 9 WDS Write Disable 1 00 00X XXXX - 10 00 XXXX - 9 ERASE Erase Byte or Word 1 11 A6-A0 - 10 A5-A0 - 9 ERAL Erase All Memory 1 00 10X XXXX - 10 10 XXXX - 9 1 00 01X XXXX D7-D0 18 01 XXXX D15-D0 25 WRAL Write All Memory with same Data 1. X = Don't care bit. DS1077 - Rev 19 page 7/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Read Data from Memory Table 4. Instruction set for the M93C56 and M93C66 x8 origination (ORG = 0) Instruction Description x16 origination (ORG = 1) Start bit Opcode Address(1)(2) Data Required clock cycles Address(2)(3) Data Required clock cycles READ Read Data from Memory 1 10 A8-A0 Q7-Q0 - A7‑A0 Q15‑Q0 - WRITE Write Data to Memory 1 01 A8-A0 D7-D0 20 A7-A0 D15-D0 27 WEN Write Enable 1 00 1 1XXX XXXX - 12 11XX XXXX - 11 WDS Write Disable 1 00 0 0XXX XXXX - 12 00XX XXXX - 11 ERASE Erase Byte or Word 1 11 A8-A0 - 12 A7-A0 - 11 ERAL Erase All Memory 1 00 1 0XXX XXXX - 12 10XX XXXX - 11 WRAL Write All Memory with same Data 1 00 0 1XXX XXXX D7-D0 20 01XX XXXX D15-D0 27 1. Address bit A8 is not decoded by the M93C56. 2. X = Don't care bit. 3. Address bit A7 is not decoded by the M93C56. Table 5. Instruction set for the M93C76 and M93C86 x8 Origination (ORG = 0) Instruction Description x16 Origination (ORG = 1) Start bit Opcode Address(1)(2) Data Required clock cycles Address(2) (3) Data Required clock cycles READ Read Data from Memory 1 10 A10-A0 Q7-Q0 - A9‑A0 Q15‑Q0 - WRITE Write Data to Memory 1 01 A10-A0 D7-D0 22 A9-A0 D15-D0 29 WEN Write Enable 1 00 11X XXXX XXXX - 14 11 XXXX XXXX - 13 WDS Write Disable 1 00 00X XXXX XXXX - 14 00 XXXX XXXX - 13 ERASE Erase Byte or Word 1 11 A10-A0 - 14 A9-A0 - 13 ERAL Erase All Memory 1 00 10X XXXX XXXX - 14 10 XXXX XXXX - 13 1 00 01X XXXX XXXX D7-D0 22 01 XXXX XXXX D15-D0 29 WRAL Write All Memory with same Data 1. Address bit A10 is not decoded by the M93C76. 2. X = Don't care bit. 3. Address bit A9 is not decoded by the M93C76. 5.1 Read Data from Memory The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically increments the internal address register and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read (the address counter automatically rolls over to 00h when the highest address is reached). DS1077 - Rev 19 page 8/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Erase and Write data 5.2 Erase and Write data 5.2.1 Write Enable and Write Disable The Write Enable (WEN) instruction enables the future execution of erase or write instructions, and the Write Disable (WDS) instruction disables it. When power is first applied, the M93Cx6 initializes itself so that erase and write instructions are disabled. After a Write Enable (WEN) instruction has been executed, erasing and writing remains enabled until a Write Disable (WDS) instruction is executed, or until VCC falls below the power-on reset threshold voltage. To protect the memory contents from accidental corruption, it is advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write Disable (WDS) instructions. 5.2.2 Write For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and address bits. These form the byte or word that is to be written. As with the other bits, Serial Data Input (D) is sampled on the rising edge of Serial Clock (C). After the last data bit has been sampled, the Chip Select Input (S) must be taken low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. The completion of the cycle can be detected by monitoring the READY/BUSY line, as described later in this document. Once the Write cycle has been started, it is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle). The Write cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an explicit erase instruction before a Write Data to Memory (WRITE) instruction. DS1077 - Rev 19 page 9/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Erase and Write data Figure 5. READ, WRITE, WEN, WDS sequences Read S D 1 1 0 An A0 Q Qn ADDR Q0 DATA OUT OP CODE Write S CHECK STATUS D 1 0 1 An A0 Dn D0 Q ADDR DATA IN BUSY READY OP CODE Write Enable S D Write Disable 1 0 0 1 1 Xn X0 OP CODE 1. DS1077 - Rev 19 S D 1 0 0 0 0 Xn X0 OP CODE AI00878d For the meanings of An, Xn, Qn and Dn, see Table 3. Instruction set for the M93C46, Table 4. Instruction set for the M93C56 and M93C66 and Table 5. Instruction set for the M93C76 and M93C86. page 10/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Erase and Write data 5.2.3 Write All As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with same Data (WRAL) instruction requires that a dummy address be provided. As with the Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided. This value is written to all the addresses of the memory device. The completion of the cycle can be detected by monitoring the READY/BUSY line, as described next. Figure 6. WRAL sequence WRITE ALL S CHECK STATUS D 1 0 0 0 1 Xn X0 Dn D0 Q ADDR DATA IN BUSY READY OP CODE AI00880C 1. DS1077 - Rev 19 For the meanings of Xn and Dn, please see Table 3. Instruction set for the M93C46, Table 4. Instruction set for the M93C56 and M93C66 and Table 5. Instruction set for the M93C76 and M93C86. page 11/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Erase and Write data 5.2.4 Erase Byte or Word The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or word) to 1. Once the address has been correctly decoded, the falling edge of the Chip Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be detected by monitoring the READY/BUSY line, as described in Section 6 READY/BUSY status. Figure 7. ERASE, ERAL sequences ERASE S CHECK STATUS D 1 1 1 An A0 Q ADDR BUSY READY OP CODE ERASE ALL S CHECK STATUS D 1 0 0 1 0 Xn X0 Q ADDR BUSY READY OP CODE AI00879b 1. 5.2.5 For the meanings of An and Xn, please see Table 3. Instruction set for the M93C46, Table 4. Instruction set for the M93C56 and M93C66 and Table 5. Instruction set for the M93C76 and M93C86. Erase All The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set to 1). The format of the instruction requires that a dummy address be provided. The Erase cycle is conducted in the same way as the Erase instruction (ERASE). The completion of the cycle can be detected by monitoring the READY/BUSY line, as described in Section 6 READY/BUSY status. DS1077 - Rev 19 page 12/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x READY/BUSY status 6 READY/BUSY status While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high. (Please note, though, that there is an initial delay, of tSLSH, before this status information becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1) indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q) remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is decoded. DS1077 - Rev 19 page 13/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Clock pulse counter 7 Clock pulse counter In a noisy environment, the number of pulses received on Serial Clock (C) may be greater than the number delivered by the master (the microcontroller). This can lead to a misalignment of the instruction of one or more bits (as shown in Figure 8) and may lead to the writing of erroneous data at an erroneous address. To avoid this problem, the M93Cx6 has an on-chip counter that counts the clock pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL instruction is aborted, and the contents of the memory are not modified. The number of clock cycles expected for each instruction, and for each member of the M93Cx6 family, are summarized in Table 3. Instruction set for the M93C46 to Table 5. Instruction set for the M93C76 and M93C86. For example, a Write Data to Memory (WRITE) instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization) from the start bit to the falling edge of Chip Select Input (S). That is: • 1 Start bit • + 2 Op-code bits • + 9 Address bits • + 8 Data bits Figure 8. Write sequence with one clock glitch S C D An START "0" "1" WRITE DS1077 - Rev 19 An-1 An-2 Glitch D0 ADDRESS AND DATA ARE SHIFTED BY ONE BIT AI01395 page 14/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Initial delivery state 8 Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). DS1077 - Rev 19 page 15/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Maximum ratings 9 Maximum ratings Stressing the device outside the ratings listed in the Table 6. Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Absolute maximum ratings Symbol TA TSTG Parameter Min. Max. Unit Ambient operating temperature –40 130 °C Storage temperature –65 150 °C (1) °C TLEAD Lead temperature during soldering VOUT Output range (Q = VOH or Hi-Z) –0.50 VCC+0.5 V VIN Input range –0.50 VCC+1 V VCC Supply voltage –0.50 6.5 V - 4000 V VESD Electrostatic discharge voltage (human body See note model)(2) 1. Compliant with JEDEC standard J-STD-020 (for small-body, Sn-Pb or Pb free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS directive 2011/65/EU of July 2011). 2. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with ANSI/ESDA/JEDEC JS-001), C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω). DS1077 - Rev 19 page 16/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x DC and AC parameters 10 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 7. Operating conditions M93Cx6-W Symbol VCC TA Parameter Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature -40 85 °C Min. Max. Unit Supply voltage 1.8 5.5 V Ambient operating temperature -40 85 °C Table 8. Operating conditions M93Cx6-R Symbol VCC TA Parameter Table 9. Cycling performance Symbol Parameter Test conditions Min. Max. - 4,000,000 TA ≤ 25 °C, Ncycle VCC(min) < VCC < VCC(max) Write cycle endurance Unit Write cycle(1) TA = 85 °C, - VCC(min) < VCC < VCC(max) 1,200,000 1. The Write cycle endurance is evaluated by characterization and qualification. Table 10. Memory cell data retention Parameter Data retention Test conditions(1). Min. Unit TA = 55 °C 200 Year 1. The data retention behavior is checked in production, while the 200-year limit is evaluated by characterization and qualification results. Table 11. AC measurement conditions Symbol Min. Max. Unit Load capacitance - 100 pF - Input rise and fall times - 50 ns - Input voltage levels 0.2 VCC to 0.8 VCC V - Input timing reference voltages 0.3 VCC to 0.7 VCC V - Output timing reference voltages 0.3 VCC to 0.7 VCC V CL DS1077 - Rev 19 Parameter page 17/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x DC and AC parameters Figure 9. AC testing input output waveforms M93Cxx 0.8 VCC 0.7 VCC Input voltage levels 0.3 VCC 0.2 VCC Input and output timing reference levels MS19788V4 Table 12. Capacitance Symbol COUT CIN Parameter Test condition(1) Min Max Unit VOUT = 0V - 8 pF VIN = 0V - 6 pF Min. Max. Unit Output capacitance Input capacitance 1. Specified by design - Not tested in production. Table 13. DC characteristics (M93Cx6-W) Test condition Symbol Parameter (in addition to the conditions defined in Table 7 and Table 11) ILI Input leakage current VIN = VSS or VCC - ± 2.5 µA ILO Output leakage current VOUT = VSS or VCC, Q in high-Z - ± 2.5 µA ICC Operating supply current (Read) VCC = 5 V, S = VIH, f = 2 MHz, Q = open - 2 mA VCC = 2.5 V, S = VIH, f = 2 MHz, Q = open - 1 mA - 2 µA - 3 µA VCC = 2.5 V, S = VSS, C = VSS, ORG = VSS or VCC, ICC1 Standby supply current pin7 = VCC, VSS, or high-Z VCC = 5.5 V, S = VSS, C = VSS, ORG = VSS or VCC, pin7 = VCC, VSS, or high-Z DS1077 - Rev 19 VIL Input low voltage (D, C, S) - –0.45 0.2 VCC V VIH Input high voltage (D, C, S) - 0.7 VCC VCC + 1 V VOL Output low voltage (Q) VCC = 5 V, IOL = 2.1 mA - 0.4 V VCC = 2.5 V, IOL = 100 µA - 0.2 V VOH Output high voltage (Q) VCC = 5 V, IOH = –400 µA 0.8 VCC - V VCC - 0.2 - V VCC = 2.5 V, IOH = –100 µA page 18/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x DC and AC parameters Table 14. DC characteristics (M93Cx6-R) Test condition Symbol Parameter (in addition to the conditions defined in Min. Max. Unit Table 8 and Table 11) ILI Input leakage current VIN = VSS or VCC - ± 2.5 µA ILO Output leakage current VOUT = VSS or VCC, Q in high-Z - ± 2.5 µA ICC Operating supply current (Read) VCC = 5 V, S = VIH, f = 2 MHz, Q = open - 2 mA VCC = 1.8 V, S = VIH, f = 1 MHz, Q = open - 1 mA - 1 µA VCC = 1.8 V, S = VSS, C = VSS, ICC1 ORG = VSS or VCC, Supply current (Standby) pin7 = VCC, VSS or high-Z VIL Input low voltage (D, C, S) - –0.45 0.2 VCC V VIH Input high voltage (D, C, S) - 0.8 VCC VCC + 1 V VOL Output low voltage (Q) VCC = 1.8 V, IOL = 100 µA - 0.2 V VOH Output high voltage (Q) VCC = 1.8 V, IOH = –100 µA VCC - 0.2 - V Min. Max. Unit D.C. 2 MHz Chip Select low to Clock high 50 - ns Table 15. AC characteristics (M93Cx6-W, M93Cx6-R) Test conditions specified in Table 7, Table 8 and Table 11 Symbol Alt. fC fSK tSLCH - tSHCH tCSS Chip Select setup time 50 - ns tSLSH(1) tCS Chip Select low to Chip Select high 200 - ns (2) tSKH Clock high time 200 - ns tCLCH(2) tSKL Clock low time 200 - ns tDVCH tDIS Data in setup time 50 - ns tCHDX tDIH Data in hold time 50 - ns tCLSH tSKS Clock setup time (relative to S) 50 - ns tCLSL tCSH Chip Select hold time 0 - ns tSHQV tSV Chip Select to READY/BUSY status - 200 ns tSLQZ tDF Chip Select low to output high-Z - 100 ns tCHQL tPD0 Delay to output low - 200 ns tCHQV tPD1 Delay to output valid - 200 ns tW tWP Erase or Write cycle time - 5 ms tCHCL Parameter Clock frequency 1. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive instruction cycles. 2. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max). DS1077 - Rev 19 page 19/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x DC and AC parameters Figure 10. Synchronous timing (Start and op-code input) tCLSH tCHCL C tSHCH tCLCH S tDVCH tCHDX OP CODE START D START OP CODE OP CODE INPUT ai01428 Figure 11. Synchronous timing (Read) C tCLSL S tDVCH D Q tCHDX tCHQV tSLSH A0 An tSLQZ tCHQL Hi-Z Q15/Q7 ADDRESS INPUT Q0 DATA OUTPUT AI00820C Figure 12. Synchronous timing (Write) tSLCH C tCLSL S tDVCH D tSLSH tCHDX A0/D0 An tSHQV Q Hi-Z tSLQZ BUSY READY tW ADDRESS/DATA INPUT WRITE CYCLE ai01429 DS1077 - Rev 19 page 20/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Package information 11 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 11.1 SO8N package information This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package. Figure 13. SO8N – Outline Package SO8N (package code O7) A2 h x 45˚ A c b ccc e D 0.25 mm GAUGE PLANE SEATING PLANE C k 8 E1 1 E A1 L L1 1. DS1077 - Rev 19 Drawing is not to scale. page 21/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x SO8N package information Table 16. SO8N – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.100 - 0.230 0.0039 - 0.0091 D(2) 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1(3) 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. Note: The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side. Figure 14. SO8N - Recommended footprint 3.9 6.7 0.6 (x8) 1.27 1. DS1077 - Rev 19 Dimensions are expressed in millimeters. page 22/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x UFDFPN8 (DFN8) package information 11.2 UFDFPN8 (DFN8) package information This UFDFPN is a 8-lead, 2 x 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package. Figure 15. UFDFPN8 - Outline D N A B Package UFDFN8 (package code ZW) A ccc C Pin #1 ID marking E A1 C eee C Seating plane Side view 2x aaa C 1 aaa C 2x 2 Top view D2 e 1 2 L3 Datum A b L1 L L3 Pin #1 ID marking E2 K e/2 L1 e Terminal tip L Detail “A” Even terminal ND-1 x e See Detail “A” Bottom view 1. 2. 3. 4. DS1077 - Rev 19 Maximum package warpage is 0.05 mm. Exposed copper is not systematic and can appear partially or totally according to the cross section. Drawing is not to scale. The central pad (the area E2 by D2 in the above illustration) must be either connected to VSS or left floating (not connected) in the end application. page 23/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x UFDFPN8 (DFN8) package information Table 17. UFDFPN8 - Mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.450 0.550 0.600 0.0177 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 b(2) 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 1.900 2.000 2.100 0.0748 0.0787 0.0827 D2 1.200 - 1.600 0.0472 - 0.0630 E 2.900 3.000 3.100 0.1142 0.1181 0.1220 E2 1.200 - 1.600 0.0472 - 0.0630 e - 0.500 - - 0.0197 - K 0.300 - - 0.0118 - - L 0.300 - 0.500 0.0118 - 0.0197 L1 - - 0.150 - - 0.0059 L3 0.300 - - 0.0118 - - aaa - - 0.150 - - 0.0059 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee(3) - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 3. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. Figure 16. UFDFPN8 - Recommended footprint 1.600 0.500 0.300 0.600 1.600 1.400 1. DS1077 - Rev 19 Dimensions are expressed in millimeters. page 24/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x TSSOP8 package information 11.3 TSSOP8 package information This TSSOP is an 8-lead, 3 x 6.4 mm, 0.65 mm pitch, thin shrink small outline package. Figure 17. TSSOP8 – Outline D 8 Package TSSOP8 (package code 6P) 5 k E1 E A1 1 L L1 4 A2 A c 1. 6P_TSSOP8_ME_V3 e b Drawing is not to scale. Table 18. TSSOP8 – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.200 - - 0.0472 A1 0.050 - 0.150 0.0020 - 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 D 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1 4.300 4.400 4.500 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° - 8° 0° - 8° aaa - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. Note: DS1077 - Rev 19 The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side. page 25/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x TSSOP8 package information Figure 18. TSSOP8 – Recommended footprint 1.55 0.65 0.40 2.35 5.80 7.35 1. DS1077 - Rev 19 6P_TSSOP8_FP_V2 Dimensions are expressed in millimeters. page 26/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Ordering information 12 Ordering information Table 19. Ordering information scheme Example: M93C86- W MN 6 T P Device type M93 = MICROWIRE™ serial EEPROM Device function 86 = 16-Kbit (2048 x 8) 76 = 8-Kbit (1024 x 8) 66 = 4-Kbit (512 x 8) 56 = 2-Kbit (256 x 8) 46 = 1-Kbit (128 x 8) Operating voltage W = VCC= 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V Package(1) MN = SO8N (150 mil width) DW = TSSOP8 (169 mil width ) MC = UFDFPN8 (DFN8 ) Device grade 6 = Industrial temperature range, –40 to 85 °C. Device tested with standard test flow Packing Blank = tube packing T = tape and reel packing Plating technology G or P = RoHS compliant and halogen-free (ECOPACK2) 1. All packages are ECOPACK2 (RoHS-compliant and free of brominated, chlorinated and antimony-oxide flame retardants). Engineering samples Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. DS1077 - Rev 19 page 27/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Revision history Table 20. Document revision history Date Revision Changes Modified footnote in Table 14 and Table 15 on page 23 01-Apr-2010 9 29-Apr-2010 10 Updated Figure 14: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline and Table 22: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data Updated Figure 31: Available M93C66-x products (package, voltage range, temperature grade) UFDFPN option. Updated Table 7: Absolute maximum ratings, MLP8 package data in Section 12: Package mechanical data and process data in Section 9: Clock pulse counter. 12-Apr-2011 11 05-Oct-2011 12 Deleted Table 29: Available M93C46-x products (package, voltage range, temperature grade), Table 30: Available M93C56-x products (package, voltage range, temperature grade), Table 31: Available M93C66-x products (package, voltage range, temperature grade), Table 32: Available M93C76-x products (package, voltage range, temperature grade) and Table 33: Available M93C86-x products (package, voltage range, temperature grade). Updated Table 1: Device summary and Table 8: Operating conditions (M93Cx6). Modified footnote 2 in Table 7. Document reformatted. Updated: 23‑Apr‑2013 13 • Part number names • Table 1: Device summary and package figure on cover page • Section 1: Description • Introductory paragraph in Section 9: Maximum ratings • Note (2) under Table 7: Absolute maximum ratings • Table 8: Operating conditions (M93Cx6) and Table 8: Operating conditions (M93Cx6-W) • Introductory paragraph in Section 11: Package information • Figure 15: UFDFPN8 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2 x 3 mm, outline and Table 20: UFDFPN8 8-lead Ultra thin Fine pitch Dual Flat Package No lead x 3 mm, data • Table 20: Ordering information scheme Renamed: • Figure 2: 8-pin package connections (top view) • Table 16: AC characteristics (M93Cx6, device grade 6) Deleted: • Section: Common I/O operation • Table: DC characteristics (M93Cx6, device grade 3), Table: DC characteristics (M93Cx6-W, device grade 3), and Table: AC characteristics (M93Cx6-W, device grade 3) Updated: 26‑Oct‑2013 14 • Table 1: Device summary: added “M93C46-R” and “M93C86-R”, deleted M93Cxx part numbers. • Features : Single supply voltage, write cycles and data retention • Section 1: Description • Note (2) under Table 7: Absolute maximum ratings. • Section 10: DC and AC parameters: updated the introduction and deleted tables related to M93Cxx part numbers. • Figure 9: AC testing input output waveforms • Table 14: DC characteristics (M93Cx6-W), Table 15: DC characteristics (M93Cx6-R), Table 16: AC characteristics (M93Cx6-W, M93Cx6-R) and Table 17: AC characteristics (M93Cx6-R). • Table 20: Ordering information scheme. Added: • DS1077 - Rev 19 Figure 4: M93Cx6 ORG input connection page 28/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Date Revision Changes • 15-Nov-2013 15 Table 10: Cycling performance and Table 11: Memory cell data retention. Removed Table 14 Cycling performance by byte Updated: 06‑Nov‑2015 16 • Features • Table 1: Device summary • Notes of Table 7: Absolute maximum ratings; • Table 20: Ordering information scheme • Table 11: Package information Updated: 21‑Dec‑2015 17 • Figure 15: UFDFN8 - Outline • Table 18: UFDFN8 - Mechanical data Updated: 10‑Jan‑2022 18 • Features • Section Device summary • Section 2 Connecting to the serial bus • Table 6. Absolute maximum ratings • Table 8. Operating conditions M93Cx6-R • Table 10. Memory cell data retention • Table 11. AC measurement conditions • Table 12. Capacitance • Table 13. DC characteristics (M93Cx6-W) • Table 14. DC characteristics (M93Cx6-R) • Section 11.1 SO8N package information • Section 11.2 UFDFPN8 (DFN8) package information • TSSOP8 package information • Section 12 Ordering information Added: • Figure 16. UFDFPN8 - Recommended footprint • Figure 2 Deleted: • PDIP8 (BN) • Table 17: AC characteristics (M93Cx6-R) • Section 11.1: PDIP8 package information Updated: • 25-Jul-2022 DS1077 - Rev 19 19 Table 15. AC characteristics (M93Cx6-W, M93Cx6-R) • Table 16. SO8N – Mechanical data • Section 11.2 UFDFPN8 (DFN8) package information • Section 11.3 TSSOP8 package information page 29/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Operating features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1.3 Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 5.1 Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Erase and Write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2.1 Write Enable and Write Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2.2 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2.3 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2.4 Erase Byte or Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2.5 Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 7 Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 11 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 12 11.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.2 UFDFPN8 (DFN8) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.3 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 DS1077 - Rev 19 page 30/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Contents List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 DS1077 - Rev 19 page 31/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Memory size versus organization . . . . . . . . Signal names . . . . . . . . . . . . . . . . . . . . . Instruction set for the M93C46 . . . . . . . . . . Instruction set for the M93C56 and M93C66 Instruction set for the M93C76 and M93C86 Absolute maximum ratings . . . . . . . . . . . . Operating conditions M93Cx6-W . . . . . . . . Operating conditions M93Cx6-R . . . . . . . . Cycling performance . . . . . . . . . . . . . . . . Memory cell data retention . . . . . . . . . . . . AC measurement conditions . . . . . . . . . . . Capacitance . . . . . . . . . . . . . . . . . . . . . . DC characteristics (M93Cx6-W) . . . . . . . . . DC characteristics (M93Cx6-R) . . . . . . . . . AC characteristics (M93Cx6-W, M93Cx6-R) SO8N – Mechanical data . . . . . . . . . . . . . UFDFPN8 - Mechanical data . . . . . . . . . . . TSSOP8 – Mechanical data . . . . . . . . . . . Ordering information scheme. . . . . . . . . . . Document revision history . . . . . . . . . . . . . DS1077 - Rev 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 2 . 7 . 8 . 8 16 17 17 17 17 17 18 18 19 19 22 24 25 27 28 page 32/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. DS1077 - Rev 19 Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 8-pin package connections (top view) . . . . . . . . . Bus master and memory devices on the serial bus M93Cx6 ORG input connection. . . . . . . . . . . . . . READ, WRITE, WEN, WDS sequences . . . . . . . . WRAL sequence. . . . . . . . . . . . . . . . . . . . . . . . ERASE, ERAL sequences . . . . . . . . . . . . . . . . . Write sequence with one clock glitch . . . . . . . . . . AC testing input output waveforms . . . . . . . . . . . Synchronous timing (Start and op-code input). . . . Synchronous timing (Read) . . . . . . . . . . . . . . . . Synchronous timing (Write) . . . . . . . . . . . . . . . . SO8N – Outline . . . . . . . . . . . . . . . . . . . . . . . . SO8N - Recommended footprint . . . . . . . . . . . . . UFDFPN8 - Outline . . . . . . . . . . . . . . . . . . . . . . UFDFPN8 - Recommended footprint . . . . . . . . . . TSSOP8 – Outline . . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 4 . 6 10 11 12 14 18 20 20 20 21 22 23 24 25 26 page 33/34 M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS1077 - Rev 19 page 34/34