M95040-DFDW6TP

M950x0-W M950x0-R M950x0-DF Datasheet 4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM with high-speed clock Features SO8N (150 mil width) • • • TSSOP8 (169 mil width) • UFDFPN8 (MC) DFN8 (2 x 3 mm) Product status link M95040-DF M95010-R M95020-R M95040-R • • • • • • • Compatible with the serial peripheral interface (SPI) bus Memory array – 1/2/4-Kbit (128/256/512 bytes) of EEPROM – Page size: 16 bytes – Additional write lockable page (Identification page) for M95040-DF order code Write – Byte Write within 5 ms – Page Write within 5 ms Write protect – quarter array – half array – whole memory array Max clock frequency: 20 MHz Single supply voltage: – 2.5 V to 5.5 V for M950x0-W – 1.8 V to 5.5 V for M950x0-R – 1.7 V to 5.5 V for M95040-DF Operating temperature range: from -40 °C up to +85 °C Enhanced ESD protection More than 4 million write cycles More than 200-year data retention Packages RoHS-compliant and Halongen-free – SO8N (ECOPACK2) – TSSOP8 (ECOPACK2) – UFDFPN8 (ECOPACK2) M95010-W M95020-W M95040-W DS1639 - Rev 14 - April 2022 For further information contact your local STMicroelectronics sales office. www.st.com M950x0-W M950x0-R M950x0-DF Description 1 Description The M95010/M95020/M95040 devices (M950x0) are electrically erasable programmable memories (EEPROMs) organized as 128/256/512 x 8 bits respectively, accessed through the SPI bus. The M950x0-W can operate with a supply voltage from 2.5 V to 5.5 V, the M950x0-R can operate with a supply voltage from 1.8 V to 5.5 V and the M950x0-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C The M950x0-DF offers an additional page, named the identification page (16 bytes). The identification page can be used to store sensitive application parameters that can be (later) permanently locked in read-only mode. Figure 1. Logic diagram VCC D C S M95xxx Q W HOLD VSS The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is selected when chip select (S) is driven low. Communications with the device can be interrupted when the HOLD is driven low. Table 1. Signal names Signal name DS1639 - Rev 14 Function Direction C Serial clock Input D Serial data input Input Q Serial data output Output S Chip select Input W Write protect Input HOLD Hold Input VCC Supply voltage - VSS Ground - page 2/46 M950x0-W M950x0-R M950x0-DF Description Figure 2. 8-pin package connections (top view) M95xxx 1. DS1639 - Rev 14 S 1 8 VCC Q 2 7 HOLD W 3 6 C VSS 4 5 D See Package information for package dimensions, and how to identify pin 1. page 3/46 M950x0-W M950x0-R M950x0-DF Block diagram 2 Block diagram The memory is organized as shown in the following figure. Figure 3. Block diagram DATA REGISTER + ECC /S SENSE AMPLIFIERS X DECODER PAGE LATCHES Q I/O D C HOLD 1. = Identification page DS1639 - Rev 14 STATUS REGISTER CONTROL LOGIC Y DECODER ARRAY W CUSTOM AREA(1) HV GENERATOR + SEQUENCER ADDRESS REGISTER MS67262 page 4/46 M950x0-W M950x0-R M950x0-DF Signal description 3 Signal description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 15 and Table 16). These signals are described next. 3.1 Serial data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial clock (C). 3.2 Serial data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of serial clock (C). 3.3 Serial clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial data input (D) are latched on the rising edge of serial clock (C). Data on serial data output (Q) change from the falling edge of serial clock (C). 3.4 Chip select (S) When this input signal is high, the device is deselected and serial data output (Q) is at high impedance. The device is in the standby power mode, unless an internal write cycle is in progress. Driving chip select (S) low selects the device, placing it in the active power mode. After power-up, a falling edge on chip select (S) is required prior to the start of any instruction. 3.5 Hold (HOLD) The hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock (C) are Don’t care. To start the hold condition, the device must be selected, with chip select (S) driven low. 3.6 Write protect (W) This input signal controls whether the memory is write protected. When write protect (W) is held low, writes to the memory are disabled, but other operations remain enabled. Write protect (W) must either be driven high or low, but must not be left floating. 3.7 VCC supply voltage VCC is the supply voltage. 3.8 VSS ground VSS is the reference for all signals, including the VCC supply voltage. DS1639 - Rev 14 page 5/46 M950x0-W M950x0-R M950x0-DF Connecting to the SPI bus 4 Connecting to the SPI bus The device is fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The serial data input (D) is sampled on the first rising edge of the serial clock (C) after chip select (S) goes low. All output data bytes are shifted out of the device, most significant bit first. The serial data output (Q) is latched on the first falling edge of the serial clock (C) after the instruction (such as the read from memory array and read status register instructions) have been clocked into the device. Figure 4 shows an example of three memory devices connected to an MCU, on an SPI bus. Only one memory device is selected at a time, so only one memory device drives the serial data output (Q) line at a time, the other memory devices are high impedance. The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the bus master leaves the S line in the high impedance state. In applications where the bus master may leave all SPI bus lines in high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), it is recommended to connect the clock line (C) to an external pull-down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled high): this ensures that S and C do not become high at the same time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ. Figure 4. Bus master and memory devices on the SPI bus VCC SPI interface with (CPOL, CPHA) = (0, 0) or 1, 1) SDO SDI SCK C Q D SPI bus master R CS3 CS2 CS1 SPI memory device S W HOLD (1) C Q D VCC (1) R C Q D VCC SPI memory device R SPI memory device S W HOLD (1) VCC (1) S W HOLD (1) (1) VSS 1. The Write protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate. MS19755V3 DS1639 - Rev 14 page 6/46 M950x0-W M950x0-R M950x0-DF SPI modes 4.1 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two modes: • • CPOL = 0, CPHA = 0 CPOL = 1, CPHA = 1 For these two modes, input data is latched in on the rising edge of serial clock (C), and output data is available from the falling edge of serial clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Stand-by mode and not transferring data: • • C remains at 0 for (CPOL = 0, CPHA = 0) C remains at 1 for (CPOL = 1, CPHA = 1) Figure 5. SPI modes supported CPOL CPHA 0 0 C 1 1 C D Q DS1639 - Rev 14 MSB MSB page 7/46 M950x0-W M950x0-R M950x0-DF Operating features 5 Operating features 5.1 Supply voltage (VCC) 5.1.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8, Table 9 and Table 10 in Section 9 DC and AC parameters). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually in the range between 10 and 100 nF) close to the VCC / VSS device pins. 5.1.2 Device reset In order to prevent erroneous instruction decoding and inadvertent write operations during power‑up, a power‑on‑reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the internal reset threshold voltage(this threshold is defined in Table 15 and Table 16 as VRES). At power-up, when VCC passes over the POR threshold, the device is reset and is in the following state: • • • Standby power mode Deselected (note that, to be executed, an instruction must be preceded by a falling edge on chip select (S)) Status register values: – – – the write enable latch (WEL) bit is reset to 0 the write in progress (WIP) bit is reset to 0 the BP1 and BP0 bits remain unchanged (non-volatile bits). It is important to note that the device must not be accessed until VCC reaches a valid and stable level within the specified [VCC(min), VCC(max)] range, as defined in Table 8, Table 9 and Table 10. 5.1.3 Power-up conditions When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the chip select (S) line is not allowed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 4). In addition, the chip select (S) input offers a built-in safety feature, as the S input is edge-sensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected on chip select (S). This ensures that chip select (S) must have been high, prior to going low to start the first operation. The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 8, Table 9 and Table 10. 5.1.4 Power-down During power-down (continuous decrease of the VCC supply voltage below the minimum VCC operating voltage defined in Table 8, Table 9 and Table 10), the device must be: 5.1.5 • deselected (chip select S must be allowed to follow the voltage applied on VCC) • in standby power mode (there must not be any internal write cycle in progress) Active power and Standby power modes When chip select (S) is low, the device is selected, and in the active power mode. The device consumes ICC. When chip select (S) is high, the device is deselected. If a write cycle is not currently in progress, the device then goes into the standby power mode, and the device consumption drops to ICC1, as specified in DC characteristics (see Section 9 DC and AC parameters). DS1639 - Rev 14 page 8/46 M950x0-W M950x0-R M950x0-DF Hold condition 5.2 Hold condition The hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. To enter the hold condition, the device must be selected, with chip select (S) low. During the hold condition, the serial data output (Q) is high impedance, and the serial data input (D) and the serial clock (C) are Don’t care. Normally, the device is kept selected for the whole duration of the hold condition. Deselecting the device while it is in the hold condition has the effect of resetting the state of the device: this mechanism can be used, if required, to reset the ongoing processes. The hold condition starts when the hold (HOLD) signal is driven low at the same time as serial clock (C) already being low (as shown in Figure 6). The hold condition ends when the hold (HOLD) signal is driven high at the same time as serial clock (C) already being low. Figure 6 also shows what happens if the rising and falling edges are not timed to coincide with serial clock (C) being low. Figure 6. Hold condition activation C HOLD Hold condition 5.3 Hold condition Status register Figure 3 shows the position of the status register in the control logic of the device. This register contains a number of status and control bits, as shown in Table 5 and as detailed in Section 6.3 Read Status register (RDSR). DS1639 - Rev 14 page 9/46 M950x0-W M950x0-R M950x0-DF Data protection and protocol control 5.4 Data protection and protocol control To help protect the device from data corruption in noisy or poorly controlled environments, a number of safety features have been built in to the device. The main security measures can be summarized as follows: • • • • WEL bit is reset at power-up Chip select (S) must rise after the eighth clock count (or multiple thereof) in order to start a non-volatile write cycle (in the memory array or in the status register) Accesses to the memory array are ignored during the non-volatile programming cycle, and the programming cycle continues unaffected. Invalid chip select (S) and hold (HOLD) transitions are ignored. For any instruction to be accepted and executed, chip select (S) must be driven high after the rising edge of serial clock (C) that latches the last bit of the instruction, and before the next rising edge of serial clock (C). For this, “the last bit of the instruction” can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except in the case of RDSR and READ instructions). Moreover, the “next rising edge of CLOCK” might (or might not) be the next bus transaction for some other device on the bus. When a write cycle is in progress, the device protects it against external interruption by ignoring any subsequent READ, WRITE or WRSR instruction as defined in Table 3 until the present cycle is complete. Table 2. Write-protected block size Status register bits DS1639 - Rev 14 BP1 BP0 0 0 0 Protected block Protected array addresses M95040 M95020 M95010 None None None None 1 Upper quarter 180h - 1FFh C0h - FFh 60h - 7Fh 1 0 Upper half 100h - 1FFh 80h - FFh 40h - 7Fh 1 1 Whole memory 000h - 1FFh 00h - FFh 00h - 7Fh page 10/46 M950x0-W M950x0-R M950x0-DF Error correction code (ECC x 1) 5.5 Error correction code (ECC x 1) The error correction code (ECC x 1) is an internal logic function, which is transparent for the SPI communication protocol. The ECC x 1 logic is implemented on each bytes of memmory array. If a single bit out of byte happens to be erroneous during a read operation, the ECC x 1 detects this bit and replaces it with the correct value. The read reliability is therefore much improved. DS1639 - Rev 14 page 11/46 M950x0-W M950x0-R M950x0-DF Instructions 6 Instructions Each command is composed of bytes (MSB transmitted first), initiated with the instruction byte, as summarized in Table 3 If an invalid instruction is sent (one not contained in Table 3), the device automatically enters in a Wait state until deselected. Table 3. Instruction set Instruction Description Instruction format WREN Write enable 0000 X110(1) WRDI Write disable 0000 X100(1) RDSR Read Status register 0000 X101(1) WRSR Write Status register 0000 X001(1) READ Read from memory array 0000 A8011(2) WRITE Write to memory array 0000 A8010(2) RDID (3) Read identification page 1000 0011 WRID(3) Write identification page 1000 0010 RDLS(3) Reads the identification page lock status 1000 0011 Locks the identification page in read-only mode 1000 0010 LID(3) 1. X = Don’t Care. 2. For M95040, A8 = 1 for the upper half of the memory array and 0 for the lower half, while for M95010 and M95020, A8 is "Don’t Care". 3. Available only for the M95040-DF device. Table 4. Significant bits within the address bytes Instruction Bit b3 of the instruction byte LSB address byte(1)(2) b7 b6 b5 b4 b3 b2 b1 b0 READ or WRITE A8/X(3) A7 A6 A5 A4 A3 A2 A1 A0 RDID or WRID 0 0 0 0 0 A3 A2 A1 A0 RDLS or LID 0 1 0 0 0 0 0 0 0 1. A: Significant address bit. 2. X: bit is Don’t Care. 3. For M95040, A8 = 1 for the upper half of the memory array and 0 for the lower half, while for M95010 and M95020, A8 is Don’t Care. DS1639 - Rev 14 page 12/46 M950x0-W M950x0-R M950x0-DF Write enable (WREN) 6.1 Write enable (WREN) The write enable latch (WEL) bit must be set prior to a write instruction (WRITE, WRSR, WRID or LID). The only way to do this is to send a write enable instruction to the device. As shown in Figure 7, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction byte are shifted in, on serial data input (D). The device then enters a wait state. It waits for a the device to be deselected, by chip select (S) being driven high. Figure 7. Write enable (WREN) sequence S 0 1 2 3 4 5 6 7 C Instruction D Q DS1639 - Rev 14 High impedance MS41478V1dita page 13/46 M950x0-W M950x0-R M950x0-DF Write disable (WRDI) 6.2 Write disable (WRDI) One way of resetting the write enable latch (WEL) bit is to send a write disable instruction to the device. As shown in Figure 8, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction byte are shifted in, on serial data input (D). The device then enters a wait state. It waits for a the device to be deselected, by chip select (S) being driven high. The write enable latch (WEL) bit, in fact, becomes reset by any of the following events: • • • • • Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion. Write protect (W) line being held low Figure 8. Write disable (WRDI) sequence S 0 1 2 3 4 5 6 7 C Instruction D Q DS1639 - Rev 14 High Impedance page 14/46 M950x0-W M950x0-R M950x0-DF Read Status register (RDSR) 6.3 Read Status register (RDSR) The read status register instruction is used to read the status Register. As shown in Figure 9, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte are then shifted in, on serial data input (D). The current state of the bits in the Status register is shifted out, on serial data out (Q). The read cycle is terminated by driving chip select (S) high. The status register is always readable, even if an internal write cycle (tW) is in progress. During a write status register cycle, the values of the non-volatile bits (BP0, BP1) become available when a new RDSR instruction is executed, after completion of the write cycle. On the other hand, the two read-only bits (write enable latch (WEL), write In progress (WIP)) are dynamically updated during the ongoing write cycle. It is possible to read the status register contents continuously, as described in Figure 9. Bits b7, b6, b5 and b4 are always read as 1. The status and control bits of the status register are as follows: Table 5. Status register format b7 1 b0 1 1 1 BP1 BP0 WEL WIP Block protect bits Write enable latch bit Write in progress bit 6.3.1 WIP bit The write in progress (WIP) bit indicates whether the memory is busy with a write (WRITE, WRID/LID) or write status register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such cycle is in progress. 6.3.2 WEL bit The write enable latch (WEL) bit indicates the status of the internal write enable latch. When set to 1, the internal write enable latch is set. When set to 0, the internal write enable latch is reset, and no write or write status register instruction is accepted. DS1639 - Rev 14 page 15/46 M950x0-W M950x0-R M950x0-DF Read Status register (RDSR) 6.3.3 BP1, BP0 bits The block protect (BP1, BP0) bits are non volatile. They define the size of the area to be software-protected against write instructions. These bits are written with the write status register (WRSR) instruction. When one or both of the block protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes protected against write instructions as defined in Table 3. The block protect (BP1, BP0) bits can be written provided that the hardware protected mode has not been set. Figure 9. Read Status Register (RDSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction D Q High impedance Status Register Out 7 MSB DS1639 - Rev 14 6 5 4 3 2 1 Status Register Out 0 7 MSB 6 5 4 3 2 1 0 7 MS57015V1 page 16/46 M950x0-W M950x0-R M950x0-DF Write status register (WRSR) 6.4 Write status register (WRSR) The write status register (WRSR) instruction is used to write new values to the status register. Before it can be accepted, a write enable (WREN) instruction must have been previously executed. The write status register (WRSR) instruction is entered by driving chip select (S) low, followed by the instruction code, the data byte on serial data input (D) and chip select (S) driven high. Chip select (S) must be driven high after the rising edge of serial clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (C). Otherwise, the write status register (WRSR) instruction is not executed. Driving the chip select (S) signal high at a byte boundary of the input data triggers the self-timed write cycle that takes tW to complete (as specified in Table 17). The instruction sequence is shown in Figure 10. While the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (WIP) bit: the WIP bit is 1 during the self-timed write cycle tW, and, 0 when the write cycle is complete. The WEL bit (write enable latch) is also reset at the end of the write cycle tW. The WRSR instruction allows the user to change the values of the BP1, BP0 bits, which define the size of the area that is to be treated as read only, as defined in Table 2. The contents of the BP1, BP0 bits are updated after the completion of the WRSR instruction, including the tW write cycle. The WRSR instruction has no effect on the b7, b6, b5, b4, b1 and b0 bits in the status register. B7, b6, b5 and b4 are always read as 1. Figure 10. Write status register (WRSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction Status Register In 7 D 6 5 4 3 2 1 0 MSB Q High impedance MS47556V1dita The WRSR instruction is not accepted, and is not executed, under the following conditions: • • • • DS1639 - Rev 14 if the write enable latch (WEL) bit has not been set to 1 (by executing a write enable instruction just before) if a write cycle is already in progress if the device has not been deselected, by chip select (S) being driven high, after the eighth bit, b0, of the data byte has been latched in if write protect (W) is low during the WRSR command (instruction, address and data) page 17/46 M950x0-W M950x0-R M950x0-DF Read from memory array (READ) 6.5 Read from memory array (READ) As shown in Figure 11, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte and address byte are then shifted in, on serial data input (D). For the M95040, the most significant address bit, A8, is incorporated as bit b3 of the instruction byte, as shown in Table 3. The address is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data Output (Q). If chip select (S) continues to be driven low, an internal bit-pointer is automatically incremented at each clock cycle, and the corresponding data bit is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single read instruction. The read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a write cycle is currently in progress. Table 6. Address range bits Device M95040 M95020 M95010 Address bits A8-A0 A7-A0 A6-A0 Figure 11. Read from memory array (READ) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 C Instruction D A8 Byte Address A7 A6 A5 A4 A3 A2 A1 A0 Data Out High Impedance Q 7 6 5 4 3 2 1 0 MS57016V1 1. DS1639 - Rev 14 Depending on the memory size, as shown in Table 6, the most significant address bits are "Don’t care". page 18/46 M950x0-W M950x0-R M950x0-DF Write to Memory array (WRITE) 6.6 Write to Memory array (WRITE) As shown in Figure 12, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (D). The instruction is terminated by driving chip select (S) high at a byte boundary of the input data. The self‑timed write cycle, triggered by the chip select (S) rising edge, continues for a period tW (as specified in Table 17), at the end of which the write in progress (WIP) bit is reset to 0. In the case of Figure 12, chip select (S) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. However, if chip select (S) continues to be driven low (as shown in Figure 13), the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. If chip select (S) still continues to be driven low, the next byte of input data is shifted in, and used to overwrite the byte at the start of the current page. The instruction is not accepted, and is not executed, under the following conditions: • • • • Note: if the write enable latch (WEL) bit has not been set to 1 (by executing a write enable instruction just before) if a write cycle is already in progress if the device has not been deselected, by driving high chip select (S), at a byte boundary (after the rising edge of Serial Clock (C) that latches the last data bit, and before the next rising edge of serial clock (C) occurs anywhere on the bus) if write protect (W) is low or if the addressed page is in the area protected by the block brotect (BP1 and BP0) bits The self-timed write cycle tW is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as “1”. Figure 12. Byte write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 C Instruction D A8 Byte Address A7 A6 A5 A4 A3 A2 A1 A0 7 Data Byte 6 5 4 3 2 1 0 High Impedance Q MS57017V1 1. DS1639 - Rev 14 Depending on the memory size, as shown in Table 6, the most significant address bits are "Don’t care". page 19/46 M950x0-W M950x0-R M950x0-DF Write to Memory array (WRITE) Figure 13. Page write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 C Instruction Byte Address A8 D Data Byte 1 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0 7 142 143 141 140 139 138 137 136 15+8N 14+8N 13+8N 12+8N 11+8N 10+8N 9+8N 24 25 26 27 28 29 30 31 8+8N S 1 0 C Data Byte 2 D 7 6 5 4 3 Data Byte N 2 1 0 7 6 5 4 3 2 Data Byte 16 1 0 7 6 5 4 3 2 AI01443D_dita 1. DS1639 - Rev 14 Depending on the memory size, as shown in Table 6, the most significant address bits are "Don’t care". page 20/46 M950x0-W M950x0-R M950x0-DF Read identification page (available only in M95040-D device) 6.7 Read identification page (available only in M95040-D device) The read identification page (RDID) instruction is used to read the identification page (additional page of 16 bytes, which can be written and later permanently locked in read-only mode). The chip select (S) signal is first driven low, the bits of the instruction byte and address bytes are then shifted in (MSB first) on serial data input (D). Address bit A7 must be 0 and the other address bits are Don't Care except the lower address bits [A3:A0] (it might be easier to define these bits as 0, as shown in Table 3). Data is then shifted/clocked out (MSB first) on serial data output (Q). The first byte addressed can be any byte within the identification page. If chip select (S) continues to be driven low, the internal address register is automatically incremented and the byte of data at the new address is shifted out. Note that there is no roll over feature in the identification page. The address of bytes to read must not exceed the page boundary. The read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at any time during when the data bits are shifted out. The instruction is not accepted, and is not executed, if a write cycle is currently in progress. Figure 14. Read identification page sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 C Instruction A7 A6 A5 A4 A3 A2 A1 A0 D High Impedance Q Byte Address Data Out 7 6 5 4 3 2 1 0 MS57018V1 DS1639 - Rev 14 page 21/46 M950x0-W M950x0-R M950x0-DF Write identification page (available only in M95040-D device) 6.8 Write identification page (available only in M95040-D device) The write identification page (WRID) instruction is used to write the identification page (additional page of 16 bytes which can also be permanently locked in read-only mode). The chip select signal (S) is first driven low, and then the bits of the instruction byte, address bytes, and at least one data byte are shifted in (MSB first) on serial data input (D). Address bit A7 must be 0 and the other address bits are Don't Care except the lower address bits [A3:A0] (it might be easier to define these bits as 0, as shown in Table 3). The self-timed write cycle starts from the rising edge of chip select (S), and continues for a period tW (as specified in Section 9 DC and AC parameters). Figure 15. Write identification page sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 C Instruction Byte Address A7 A6 A5 A4 A3 A2 A1 A0 7 D Data Byte 6 5 4 3 2 1 0 High Impedance Q MS57019V1 The instruction is discarded, and is not executed if the block protect bits (BP1,BP0) = (1,1) or one of the conditions defined in Section 5.4 Data protection and protocol control is not satisfied. DS1639 - Rev 14 page 22/46 M950x0-W M950x0-R M950x0-DF Read lock status (available only in M95040-D device) 6.9 Read lock status (available only in M95040-D device) The read lock status (RDLS) instruction is used to read the lock status. To send this instruction to the device, chip select (S) first has to be driven low. The bits of the instruction byte and address bytes are then shifted (MSB first) in on serial data input (D). Address bit A7 must be 1, all other address bits are Don't Care (it might be easier to define these bits as 0, as shown in Table 3). The lock bit is the LSB (least significant bit) of the byte read on serial data output (Q). It is at “1” when the lock is active and at “0” when the lock is not active. If chip select (S) continues to be driven low, the same data byte is shifted out. The read cycle is terminated by driving chip select (S) high. The instruction sequence is shown in Figure 16. The read lock status instruction is not accepted and not executed if a write cycle is currently in progress. Figure 16. Read lock status sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 C Instruction A7 A6 A5 A4 A3 A2 A1 A0 D High Impedance Q Byte Address Data Out 7 6 5 4 3 2 1 0 MS57018V1 DS1639 - Rev 14 page 23/46 M950x0-W M950x0-R M950x0-DF Lock identification page (available only in M95040-D device) 6.10 Lock identification page (available only in M95040-D device) The lock identification page (LID) instruction permanently locks the identification page in read-only mode. The LID instruction is issued by driving chip select (S) low, sending (MSB first) the instruction code, the address and a data byte on serial data input (D), and driving chip select (S) high. In the address sent, A7 must be equal to 1, all other address bits are Don't Care (it might be easier to define these bits as 0, as shown in Table 3). The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care. The LID instruction is terminated by driving Chip Select (S) high at a data byte boundary, otherwise, the instruction is not executed. Figure 17. Lock ID sequence S 0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 23 24 25 C Instruction D 8-bit address 7 6 5 3 2 Data byte 1 0 7 6 5 4 3 2 1 0 High impedance Q MS57020V1 Driving chip select (S) high at a byte boundary of the input data triggers the self-timed write cycle whose duration is tW (as specified in AC characteristics in Section 9 DC and AC parameters). The instruction sequence is shown in Figure 17. The instruction is discarded, and is not executed if the block protect bits (BP1,BP0) = (1,1) or one of the conditions defined in Section 5.4 Data protection and protocol control is not satisfied. DS1639 - Rev 14 page 24/46 M950x0-W M950x0-R M950x0-DF Power-up and delivery state 7 Power-up and delivery state 7.1 Power-up state After power-up, the device is in the following state: • • • • • Standby power mode Deselected (after power-up, a falling edge is required on chip select (S) before any instructions can be started) Not in the hold condition The write enable latch (WEL) is reset to 0 Write in progress (WIP) is reset to 0 The BP1 and BP0 bits of the status register are unchanged from the previous power-down (they are non-volatile bits). 7.2 Initial delivery state The device is delivered with: • • • DS1639 - Rev 14 The memory array set to all 1s (each byte = FFh) The block protect (BP1 and BP0) bits are initialized to 0 The identification page bits, for M95040-D only, set to all 1s (each byte = FFh) page 25/46 M950x0-W M950x0-R M950x0-DF Maximum ratings 8 Maximum ratings Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Absolute maximum ratings Symbol Parameter Min. Max. TAMB Ambient operating temperature –40 130 TSTG Storage temperature –65 150 TLEAD Lead temperature during soldering See note Unit °C (1) VO Output voltage –0.50 VCC + 0.6 VI Input voltage –0.50 VCC + 1.0 IOL DC output current (Q = 0) - 5 IIH DC output current (Q = 1) - 5 -0.50 6.5 V - 4000 V VCC Supply voltage VESD Electrostatic discharge voltage (human body model) (2) V mA 1. Compliant with JEDEC standard J-STD-020 (for small-body, Sn-Pb or Pb free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS directive 2011/65/EU of July 2011). 2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-Q100-002 (compliant with ANSI/ESDA/JEDEC JS-001, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω). DS1639 - Rev 14 page 26/46 M950x0-W M950x0-R M950x0-DF DC and AC parameters 9 DC and AC parameters This section summarizes the operating and measurement conditions and the DC/AC characteristics of the device. Table 8. Operating conditions (M950x0-W) Symbol Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature –40 85 °C Min. Max. Unit Supply voltage 1.8 5.5 V Ambient operating temperature -40 85 °C Min. Max. Unit Supply voltage 1.7 5.5 V Ambient operating temperature –40 85 °C Min. Max. Unit Load capacitance - 30 pF - Input rise and fall times - 50 ns - Input levels 0.2 VCC to 0.8 VCC V - Input and output timing references voltages 0.3 VCC to 0.7 VCC V VCC TA Parameter Table 9. Operating conditions (M950x0-R) Symbol VCC TA Parameter Table 10. Operating conditions (M95040-DF) Symbol VCC TA Parameter Table 11. AC measurement conditions Symbol CL Parameter Figure 18. AC measurement I/O waveform Input Levels Input and Output Timing Reference Levels 0.8 ₓ VCC 0.7 ₓ VCC 0.3 ₓ VCC 0.2 ₓ VCC DS1639 - Rev 14 page 27/46 M950x0-W M950x0-R M950x0-DF DC and AC parameters Table 12. Cycling performance Symbol Parameter Test condition Min. Max. - 4,000,000 TA ≤ 25 °C, Ncycle VCC(min) < VCC < VCC(max) Write cycle endurance Unit Write cycle(1) TA = 85 °C, - VCC(min) < VCC < VCC(max) 1,200,000 1. A Write cycle is executed when either a page write, a byte write, a WRSR, a WRID or an LID instruction is decoded. When using the byte write, the page write or the WRID instruction, refer also to Section 5.5 Error correction code (ECC x 1) . Table 13. Memory cell data retention Parameter Data Test condition Min. Max. Unit - 200 Year TA = 55 °C retention(1) 1. The data retention behavior is checked in production, while the 200-year limit is defined from characterization and qualification results. Table 14. Capacitance Symbol(1) COUT CIN Parameter Test condition Min. Max. Unit VOUT = 0 V - 8 pF Input capacitance (D) VIN = 0 V - 8 pF Input capacitance (other pins) VIN = 0 V - 6 pF Output capacitance (Q) 1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 5 MHz DS1639 - Rev 14 page 28/46 M950x0-W M950x0-R M950x0-DF DC and AC parameters Table 15. DC characteristics (M950x0-W) Symbol Test conditions in addition to those defined in Table 8 and Table 11 Parameter Min. Max. Unit ILI Input leakage current VIN = VSS or VCC - ±2 µA ILO Output leakage current S = VCC, VOUT = VSS or VCC - ±2 µA - 2 - 2 - 5 - 5 - 3 VCC= 2.5 V, C= 0.1 VCC / 0.9 VCC at fC = 5 MHz, Q = open ICC Supply current (Read) VCC= 2.5 V, C = 0.1 VCC / 0.9 VCC at fC = 10 MHz, Q = open VCC= 5.5 V, C = 0.1 VCC / 0.9 VCC at fC = 20 MHz, Q = open ICC0 (1) Supply current (Write) During tW, S = VCC, 2.5 V ≤ VCC < 5.5 V S = VCC, VCC= 5.5 V, ICC1 Supply current VIN = VSS or VCC (Standby Power mode) S = VCC, VCC= 2.5 V, VIN = VSS or VCC mA mA µA - 2 VIL Input low voltage - –0.45 0.3 VCC V VIH Input high voltage - 0.7 VCC VCC+1 V VOL Output low voltage VCC = 2.5 V and IOL = 1.5 mA - 0.4 V VOH Output high voltage 0.8 VCC - V 0.5 1.5 V VRES(1) Internal reset threshold voltage VCC = 2.5 V and IOH = 0.4 mA or VCC = 5 V and IOH = 2 mA - 1. Evaluated by characterization - not tested in production. DS1639 - Rev 14 page 29/46 M950x0-W M950x0-R M950x0-DF DC and AC parameters Table 16. DC characteristics (M950x0-R or M950x0-DF) Symbol Test conditions in addition to those defined in Table 9, Table 10 and Table 11 Parameter Min Max Unit ILI Input leakage current VIN = VSS or VCC - ±2 µA ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC - ±2 µA ICC Supply current (Read) - 2 mA ICC0 (2) Supply current (Write) VCC = 1.8 V or 1.7 V, during tW, S = VCC - 5 mA ICC1 Supply current (Standby Power mode) VCC = 1.8 V or 1.7 V, S = VCC, VIN = VSS or VCC - 1 µA VIL Input low voltage VCC < 2.5 V –0.45 0.25 VCC V VIH Input high voltage VCC < 2.5 V 0.75 VCC VCC+1 V VOL Output low voltage IOL = 0.15 mA, VCC = 1.8 V or 1.7 V - 0.3 V VOH Output high voltage IOH = –0.1 mA, VCC = 1.8 V or 1.7 V 0.8 VCC - V Internal reset threshold voltage - 0.5 1.5 V VRES(2) VCC= 1.8 V or 1.7 V, C = 0.1 VCC or 0.9 VCC at fC = 5 MHz , Q = open 1. If the application uses the M950x0-R or M95040-DF devices with 2.5 V ≤ VCC ≤ 5.5 V and -40 °C ≤ TA ≤ +85 °C, refer to Table 15. 2. Evaluated by characterization - not tested in production. DS1639 - Rev 14 page 30/46 M950x0-W M950x0-R M950x0-DF DC and AC parameters Table 17. AC characteristics Test conditions specified in Table 8, Table 9, Table 10 and Table 11 Symbol Alt. fC fSCK Parameter Clock frequency VCC ≥ 1.7 V or 1.8 V VCC ≥ 2.5VCC VCC ≥ 4.5V Min. Max. Unit Min. Max. Min. Max. D.C. 5 D.C. 10 D.C. 20 MHz tSLCH tCSS1 S active setup time 60 - 30 - 15 - ns tSHCH tCSS2 S not active setup time 60 - 30 - 15 - ns tSHSL tCS S deselect time 90 - 40 - 20 - ns tCHSH tCSH S active hold time 60 - 30 - 15 - ns tCHSL - S not active hold time 60 - 30 - 15 - ns (1) tCLH Clock high time 80 - 40 - 20 - ns tCL(1) tCLL Clock low time 80 - 40 - 20 - ns (2) tRC Clock rise time - 2 - 2 - 2 µs tCHCL (2) tFC Clock fall time - 2 - 2 - 2 µs tDVCH tDSU Data in setup time 20 - 10 - 5 - ns tCHDX tDH Data in hold time 20 - 10 - 10 - ns tHHCH - Clock low hold time after HOLD not active 60 - 30 - 15 - ns tHLCH - Clock low hold time after HOLD active 60 - 30 - 15 - ns tCLHL - Clock low setup time before HOLD active 0 - 0 - 0 - ns tCLHH - Clock low setup time before HOLD not active 0 - 0 - 0 - ns tSHQZ (2) tDIS Output disable time - 80 - 40 - 20 ns Clock low to output valid - 80 - 40 - 20 ns tHO Output hold time 0 - 0 - 0 - ns (2) tRO Output rise time - 80 - 40 - 20 ns tQHQL(2) tFO Output fall time - 80 - 40 - 20 ns tHHQV tLZ HOLD high to output valid - 80 - 40 - 20 ns tHLQZ tHZ HOLD low to output High-Z - 80 - 40 - 20 ns tW tWC Write time - 5 - 5 - 5 ms tCH tCLCH tCLQV (3) tCLQX tQLQH (2) tV 1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max). 2. Evaluated by characterization - not tested in production. 3. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a read setup time tSU = 0 ns, tCL can be equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU. DS1639 - Rev 14 page 31/46 M950x0-W M950x0-R M950x0-DF DC and AC parameters Figure 19. Serial input timing tSHSL S tCHSL tCH tSLCH tCHSH tSHCH C tDVCH tCL tCHCL tCLCH tCHDX D LSB IN MSB IN High impedance Q Figure 20. Hold timing S tHLCH tCLHL tHHCH C tCLHH tHLQZ tHHQV Q HOLD Figure 21. Serial output timing S tSHSL tCH C tCLQV tCLCH tCHCL tCL tSHQZ tCLQX Q tQLQH tQHQL D DS1639 - Rev 14 ADDR LSB IN page 32/46 M950x0-W M950x0-R M950x0-DF Package information 10 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 10.1 SO8N package information This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package. Figure 22. SO8N – Outline h x 45˚ A2 A c b ccc e D 0.25 mm GAUGE PLANE SEATING PLANE C k 8 E1 E 1 A1 L L1 1. Drawing is not to scale. Table 18. SO8N – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.100 - 0.230 0.0030 - 0.0091 D(2) 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1(3) 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. DS1639 - Rev 14 page 33/46 M950x0-W M950x0-R M950x0-DF SO8N package information Figure 23. SO8N - Recommended footprint 3.9 6.7 0.6 (x8) 1.27 1. DS1639 - Rev 14 Dimensions are expressed in millimeters. page 34/46 M950x0-W M950x0-R M950x0-DF TSSOP8 package information 10.2 TSSOP8 package information This TSSOP is an 8-lead, 3 x 6.4 mm, 0.65 mm pitch, thin shrink small outline package. Figure 24. TSSOP8 – Outline D 8 5 k E1 E A1 1 L L1 4 A2 A c b e 6P_TSSOP8_ME_V3 1. Drawing is not to scale. Table 19. TSSOP8 – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.200 - - 0.0472 A1 0.050 - 0.150 0.0020 - 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 D(2) 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1(3) 4.300 4.400 4.500 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° - 8° 0° - 8° aaa - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. DS1639 - Rev 14 page 35/46 M950x0-W M950x0-R M950x0-DF TSSOP8 package information Figure 25. TSSOP8 – Recommended footprint 1.55 0.65 0.40 2.35 5.80 7.35 1. DS1639 - Rev 14 Dimensions are expressed in millimeters. page 36/46 M950x0-W M950x0-R M950x0-DF UFDFPN8 (DFN8) package information 10.3 UFDFPN8 (DFN8) package information This UFDFPN is a 8-lead, 2 x 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package. Figure 26. UFDFPN8 - Outline D N A B A ccc C Pin #1 ID marking E A1 C eee C Seating plane A3 Side view 2x aaa C 1 aaa C 2x 2 Top view D2 e 1 2 L3 Datum A b L1 L L3 Pin #1 ID marking E2 K L e/2 L1 e Terminal tip Detail “A” Even terminal ND-1 x e Bottom view 1. 2. 3. 4. DS1639 - Rev 14 See Detail “A” Maximum package warpage is 0.05 mm. Exposed copper is not systematic and can appear partially or totally according to the cross section. Drawing is not to scale. The central pad (the area E2 by D2 in the above illustration) must be either connected to VSS or left floating (not connected) in the end application. page 37/46 M950x0-W M950x0-R M950x0-DF UFDFPN8 (DFN8) package information Table 20. UFDFPN8 - Mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.450 0.550 0.600 0.0177 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 b(2) 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 1.900 2.000 2.100 0.0748 0.0787 0.0827 D2 1.200 - 1.600 0.0472 - 0.0630 E 2.900 3.000 3.100 0.1142 0.1181 0.1220 E2 1.200 - 1.600 0.0472 - 0.0630 e - 0.500 - - 0.0197 - K 0.300 - - 0.0118 - - L 0.300 - 0.500 0.0118 - 0.0197 L1 - - 0.150 - - 0.0059 L3 0.300 - - 0.0118 - - aaa - - 0.150 - - 0.0059 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee(3) - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 3. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. Figure 27. UFDFPN8 - Recommended footprint 1.600 0.500 0.300 0.600 1.600 1.400 1. DS1639 - Rev 14 Dimensions are expressed in millimeters. page 38/46 M950x0-W M950x0-R M950x0-DF Ordering information 11 Ordering information Table 21. Ordering information scheme Example: M95 040-D W MN 6 T P Device type M95 = SPI serial access EEPROM Device function 040 = 4 Kbit (512 x 8) 040-D = 4 Kbit (512 x 8) plus identification page 020 = 2 Kbit (256 x 8) 010 = 1 Kbit (128 x 8) Operating voltage W = VCC = 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V F = VCC = 1.7 to 5.5 V Package(1) MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) MC = UFDFPN8 (DFN8) Device grade 6 = Industrial temperature range, –40 to 85 °C Device tested with standard test flow Option blank = tube packing T = Tape and reel packing Plating technology G or P = RoHS compliant and halogen-free (ECOPACK2) 1. All packages are ECOPACK2 (RoHS-compliant and free of brominated, chlorinated and antimony-oxide flame retardants). Note: For a list of available options (memory, package, and so on) or for further information on any aspect of this device, contact your nearest ST sales office. Note: Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DS1639 - Rev 14 page 39/46 M950x0-W M950x0-R M950x0-DF Revision history Table 22. Document revision history Date Version Changes Document renamed from “M95040 M95020 M95010” to “M950x0 M950x0-W M950x0-R” Silhouette of UDFPN8 (MB or MC) on the cover page updated. Section6.3: Read Status Register (RDSR)updated. Text modified in Section6.3.1: WIPbit. 02-Feb-2012 10 Table8:Absolutemaximum ratings updated. Figure24:UFDFPN8(MLP8) 8-leadultrathin finepitchdualflatpackagenolead 2 × 3mm, outline modified. Table24: UFDFPN8 (MLP8)8-leadultra thinfine pitch dual flat package no lead 2 × 3mm, data updated. Removed tables of available products from Section 11: Part numbering. Document renamed from “M95040 M95020 M95010” to “M950x0-W M950x0R”. Silhouette of UDFPN8 (MB or MC) on the cover page updated. 24-May-2013 11 Section6.3: Read Status Register (RDSR)updated. Text modified in Section6.3.1: WIPbit. Table8and Table24 updated. Tables 8, 13, 15, 17, 19 removed. Figure24modified. Removed tables of available products from Section 11: Part numbering. Added “M95040-DF” part number. Updated: Updated: 17-Oct-2013 12 • Features: Single supply voltage, high-speed clock frequency, memory array, write cycles and data retention • Section 1: Description • Figure 6: Block diagram • Section 6: Instructions: updated introduction and added Section 6.7 to Section 6.10 • Section 7.2: Initial delivery state • Note (1) under Table 8: Absolute maximum ratings. • Table 16: DC characteristics (M950x0-W, device grade 6), Table 18: AC characteristics (M950x0-W, device grade 6) and Table 25: Ordering information scheme Added Table 13: Cycling performance, Table 14: Memory cell data retention, Table 17: DC characteristics (M950x0-R or M95040-DF, device grade 6) and Table 19: AC characteristics (M950x0-R or M95040-DF, device grade 6). Renamed Table 20 and Table 21. Updated footnotes: 28-Aug-2014 13 • 1 in Table 13: Cycling performance; • 1 in Table 14: Memory cell data retention; • 2 in Table 19: AC characteristics (M950x0-R or M95040-DF, device grade 6); • 2 in Table 21: AC characteristics (M950x0-R, device grade 6). Updated Table 20 with new title AC characteristics (M950x0-W, device grade 6) and addition of footnote 1. Updated Table 21 with new title AC characteristics (M950x0-R, device grade 6) and addition of footnote 1. Updated Table 25: Ordering information scheme. DS1639 - Rev 14 page 40/46 M950x0-W M950x0-R M950x0-DF Date Version Changes Updated: 05-Apr-2022 14 • Section Features, Section 2 Block diagram, Section 3.8 VSS ground, Section 4 Connecting to the SPI bus, Section 5.1 Supply voltage (VCC) and its subsection, Section 7.1 Power-up state, Section 7.2 Initial delivery state, Section 10.1 SO8N package information, Section 10.2 TSSOP8 package information • Notes 1 and 2 of Table 7. Absolute maximum ratings, note of Table 12. Cycling performance, note of Table 13. Memory cell data retention, • Table 11. AC measurement conditions, Table 15. DC characteristics (M950x0-W), Table 16. DC characteristics (M950x0-R or M950x0-DF), Table 17. AC characteristics, Table 21. Ordering information scheme Added: • Section 3.7 VCC supply voltage, Section 5.5 Error correction code (ECC x 1) Removed: Table 19. AC characteristics (M950x0-R or M95040-DF, device grade 6), Table 20. AC characteristics (M950x0-W, device grade 6), Table 21. AC characteristics (M950x0-R, device grade 6) DS1639 - Rev 14 page 41/46 M950x0-W M950x0-R M950x0-DF Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4 3.1 Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Serial data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Serial clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.4 Chip select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.6 Write protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.8 VSS ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 5 Operating features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 5.1 6 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.1 Operating supply voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.5 Active power and Standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.4 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.5 Error correction code (ECC x 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 6.1 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 Read Status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 Write status register (WRSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.5 Read from memory array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.6 Write to Memory array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DS1639 - Rev 14 page 42/46 M950x0-W M950x0-R M950x0-DF Contents 7 6.7 Read identification page (available only in M95040-D device) . . . . . . . . . . . . . . . . . . . . . . . . 21 6.8 Write identification page (available only in M95040-D device) . . . . . . . . . . . . . . . . . . . . . . . . 22 6.9 Read lock status (available only in M95040-D device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.10 Lock identification page (available only in M95040-D device) . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 10 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 11 10.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.3 UFDFPN8 (DFN8) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 DS1639 - Rev 14 page 43/46 M950x0-W M950x0-R M950x0-DF List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Signal names . . . . . . . . . . . . . . . . . . . . . . . Write-protected block size . . . . . . . . . . . . . . . Instruction set . . . . . . . . . . . . . . . . . . . . . . . Significant bits within the address bytes . . . . . Status register format . . . . . . . . . . . . . . . . . . Address range bits . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . Operating conditions (M950x0-W) . . . . . . . . . Operating conditions (M950x0-R). . . . . . . . . . Operating conditions (M95040-DF). . . . . . . . . AC measurement conditions . . . . . . . . . . . . . Cycling performance . . . . . . . . . . . . . . . . . . Memory cell data retention . . . . . . . . . . . . . . Capacitance . . . . . . . . . . . . . . . . . . . . . . . . DC characteristics (M950x0-W) . . . . . . . . . . . DC characteristics (M950x0-R or M950x0-DF) . AC characteristics . . . . . . . . . . . . . . . . . . . . SO8N – Mechanical data . . . . . . . . . . . . . . . TSSOP8 – Mechanical data . . . . . . . . . . . . . UFDFPN8 - Mechanical data . . . . . . . . . . . . . Ordering information scheme. . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . DS1639 - Rev 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 10 12 12 15 18 26 27 27 27 27 28 28 28 29 30 31 33 35 38 39 40 page 44/46 M950x0-W M950x0-R M950x0-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. DS1639 - Rev 14 Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . 8-pin package connections (top view) . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . Bus master and memory devices on the SPI bus. SPI modes supported . . . . . . . . . . . . . . . . . . . Hold condition activation . . . . . . . . . . . . . . . . . Write enable (WREN) sequence . . . . . . . . . . . . Write disable (WRDI) sequence . . . . . . . . . . . . Read Status Register (RDSR) sequence . . . . . . Write status register (WRSR) sequence . . . . . . . Read from memory array (READ) sequence . . . Byte write (WRITE) sequence . . . . . . . . . . . . . Page write (WRITE) sequence . . . . . . . . . . . . . Read identification page sequence . . . . . . . . . . Write identification page sequence . . . . . . . . . . Read lock status sequence . . . . . . . . . . . . . . . Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . AC measurement I/O waveform . . . . . . . . . . . . Serial input timing . . . . . . . . . . . . . . . . . . . . . . Hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . Serial output timing . . . . . . . . . . . . . . . . . . . . . SO8N – Outline . . . . . . . . . . . . . . . . . . . . . . . SO8N - Recommended footprint . . . . . . . . . . . . TSSOP8 – Outline . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Recommended footprint. . . . . . . . . . UFDFPN8 - Outline . . . . . . . . . . . . . . . . . . . . . UFDFPN8 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 4 . 6 . 7 . 9 13 14 16 17 18 19 20 21 22 23 24 27 32 32 32 33 34 35 36 37 38 page 45/46 M950x0-W M950x0-R M950x0-DF IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS1639 - Rev 14 page 46/46