M95160-x
M95080-x
16 Kbit and 8 Kbit serial SPI bus EEPROM
with high speed clock
Features
■
Compatible with SPI bus serial interface
(positive clock SPI modes)
■
Single supply voltage:
– 4.5 V to 5.5 V for M95xxx
– 2.5 V to 5.5 V for M95xxx-W
– 1.8 V to 5.5 V for M95xxx-R
– 1.7 V to 5.5 V for M95xxx-F
SO8 (MN)
150 mil width
■
High speed: 10 MHz
■
Status Register
■
Hardware protection of the Status Register
■
Byte and page write (up to 32 bytes)
■
Self-timed programming cycle
■
Adjustable size read-only EEPROM area
■
Enhanced ESD protection
■
More than 1 million write cycles
■
More than 40-year data retention
■
Packages
– ECOPACK® (RoHS compliant)
Table 1.
TSSOP8 (DW)
169 mil width
UFDFPN8 (MB, MC)
2 × 3 mm (MLP)
Device summary
Reference
Part number
WLCSP (CS)1)
M95160
M95160-W
M95160-x
M95160-R
1. Preliminary data.
M95160-F
M95080
M95080-x
M95080-W
M95080-R
July 2011
Doc ID 8028 Rev 11
1/49
www.st.com
1
Contents
M95160-x, M95080-x
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1
Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1
4.1.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.3
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.4
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1
2/49
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Doc ID 8028 Rev 11
M95160-x, M95080-x
7
Contents
6.3.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.3
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.4
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Doc ID 8028 Rev 11
3/49
List of tables
M95160-x, M95080-x
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
4/49
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Operating conditions (M95160 and M95080) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (M95160-W and M95080-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (M95160-R and M95080-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating conditions (M95160-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics (M95160 and M95080, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics (M95160 and M95080, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95160-W and M95080-W, device grade 3). . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M95160-W and M95080-W, device grade 6). . . . . . . . . . . . . . . . . . . . 29
DC characteristics (M95160-R and M95080-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC characteristics (M95160-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC characteristics (M95160 and M95080, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 32
AC characteristics (M95160 and M95080, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 33
AC characteristics (M95160-W and M95080-W, device grade 3). . . . . . . . . . . . . . . . . . . . 34
AC characteristics (M95160-W and M95080-W, device grade 6). . . . . . . . . . . . . . . . . . . . 35
AC characteristics for M95160-Wxx6/S and M95080-Wxx6/S . . . . . . . . . . . . . . . . . . . . . . 36
AC characteristics (M95160-R and M95080-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
AC characteristics (M95160-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 41
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
WLCSP-R 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package mechanical
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 44
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Doc ID 8028 Rev 11
M95160-x, M95080-x
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
M95160 WLCSP connections (top view, marking side, with balls on the underside) . . . . . . 7
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 41
UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
WLCSP-R 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package outline . . . . . . . . . . . . . . . 43
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 44
Doc ID 8028 Rev 11
5/49
Description
1
M95160-x, M95080-x
Description
The M95160-x and M95080-x are electrically erasable programmable memory (EEPROM)
devices. They are accessed by a high-speed SPI-compatible bus. The memory array is
organized as 2048 x 8 bit (M95160-x), and 1024 x 8 bit (M95080-x).
Figure 1.
Logic diagram
VCC
D
Q
C
S
M95xxx
W
HOLD
VSS
AI01789C
The device is accessed by a simple serial interface that is SPI-compatible. The bus signals
are C, D and Q, as shown in Table 2 and Figure 1.
The device is selected when Chip Select (S) is taken low. Communications with the device
can be interrupted using Hold (HOLD).
Table 2.
Signal names
Signal name
6/49
Function
Direction
C
Serial Clock
Input
D
Serial Data input
Input
Q
Serial Data output
Output
S
Chip Select
Input
W
Write Protect
Input
HOLD
Hold
Input
VCC
Supply voltage
VSS
Ground
Doc ID 8028 Rev 11
M95160-x, M95080-x
Figure 2.
Description
8-pin package connections (top view)
M95xxx
S
Q
W
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
C
D
AI01790D
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
Figure 3.
M95160 WLCSP connections (top view, marking side, with balls on the
underside)
Q
VSS
D
S
HOLD
W
VCC
C
Orientation reference
ai15166
Caution:
EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet
(UV) light. Consequently, EEPROM dice delivered in wafer form or in WLCSP package by
STMicroelectronics must never be exposed to UV light.
Doc ID 8028 Rev 11
7/49
Signal description
2
M95160-x, M95080-x
Signal description
During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held high or low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Table 14. to Table 19.). These signals are described next.
2.1
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
8/49
Doc ID 8028 Rev 11
M95160-x, M95080-x
2.6
Signal description
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all write instructions.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
Doc ID 8028 Rev 11
9/49
Connecting to the SPI bus
3
M95160-x, M95080-x
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such
as the Read from Memory Array and Read Status Register instructions) have been clocked
into the device.
Figure 4. shows three devices, connected to an MCU, on an SPI bus. Only one device is
selected at a time, so only one device drives the Serial Data output (Q) line at a time, all the
others being high impedance.
Figure 4.
Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
C Q D
SPI Bus Master
SPI Memory
Device
R
CS3
VCC
C Q D
VSS
C Q D
VCC
VSS
SPI Memory
Device
R
VSS
SPI Memory
Device
R
CS2 CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 4 shows an example of three memory devices connected to an MCU, on an SPI bus.
Only one memory device is selected at a time, so only one memory device drives the Serial
Data output (Q) line at a time, the other memory devices are high impedance.
The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may be in a state where all input/output SPI buses are
high impedance at the same time (for example, if the Bus Master is reset during the
transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high): this ensures that S and C do not become high at the same
time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ.
10/49
Doc ID 8028 Rev 11
M95160-x, M95080-x
3.1
Connecting to the SPI bus
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
CPOL=0, CPHA=0
●
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5., is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
●
C remains at 1 for (CPOL=1, CPHA=1)
Figure 5.
SPI modes supported
CPOL CPHA
0
0
C
1
1
C
D
MSB
Q
MSB
AI01438B
Doc ID 8028 Rev 11
11/49
Operating features
M95160-x, M95080-x
4
Operating features
4.1
Supply voltage (VCC)
4.1.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 9, Table 10 and
Table 11). This voltage must remain stable and valid until the end of the transmission of the
instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In
order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with
a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package
pins.
4.1.2
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until VCC
reaches the POR threshold voltage (this threshold is defined in DC characteristics tables 15,
16, 17, 18, 19 and 20 as VRES).
When VCC passes over the POR threshold, the device is reset and is in the following state:
●
in Standby Power mode
●
deselected (note that, to be executed, an instruction must be preceded by a falling
edge on Chip Select (S))
●
Status Register value:
–
the Write Enable Latch (WEL) is reset to 0
–
Write In Progress (WIP) is reset to 0
–
The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
When VCC passes over the POR threshold, the device is reset and enters the Standby
Power mode. The device must not be accessed until VCC reaches a valid and stable VCC
voltage within the specified [VCC(min), VCC(max)] range defined in Table 9, Table 10 and
Table 11.
4.1.3
Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 4).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Table 9, Table 10 and Table 11 and the rise time must not vary faster than 1 V/µs.
12/49
Doc ID 8028 Rev 11
M95160-x, M95080-x
4.1.4
Operating features
Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum
VCC operating voltage defined in Table 9, Table 10 and Table 11), the device must be:
4.2
●
deselected (Chip Select S should be allowed to follow the voltage applied on VCC)
●
in Standby Power mode (there should not be any internal write cycle in progress).
Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes ICC, as specified in Table 14. to Table 19.
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to ICC1.
4.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low.
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
4.4
Status Register
Figure 6. shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits
Doc ID 8028 Rev 11
13/49
Operating features
4.5
M95160-x, M95080-x
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
●
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
Power-up
–
Write Disable (WRDI) instruction completion
–
Write Status Register (WRSR) instruction completion
–
Write (WRITE) instruction completion
●
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
●
The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status
Register to be protected.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
●
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 3.
Write-protected block size
Status Register bits
Protected array addresses
Protected block
14/49
BP1
BP0
M95160-x
M95080-x
0
0
none
none
none
0
1
Upper quarter
0600h - 07FFh
0300h - 03FFh
1
0
Upper half
0400h - 07FFh
0200h - 03FFh
1
1
Whole memory
0000h - 07FFh
0000h - 03FFh
Doc ID 8028 Rev 11
M95160-x, M95080-x
Memory organization
The memory is organized as shown in Figure 6.
Figure 6.
Block diagram
HOLD
W
High voltage
generator
Control logic
S
C
D
I/O shift register
Q
Address register
and counter
Data
register
Status
Register
Size of the
read-only
EEPROM
area
Y decoder
5
Memory organization
1 page
X decoder
AI01272d
Doc ID 8028 Rev 11
15/49
Instructions
6
M95160-x, M95080-x
Instructions
Each instruction starts with a single-byte code, as summarized in Table 4.
If an invalid instruction is sent (one not contained in Table 4.), the device automatically
deselects itself.
Table 4.
Instruction set
Instruction
6.1
Description
Instruction format
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7., to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 7.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI02281E
16/49
Doc ID 8028 Rev 11
M95160-x, M95080-x
6.2
Instructions
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8., to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
Power-up
●
WRDI instruction execution
●
WRSR instruction completion
●
WRITE instruction completion.
Figure 8.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03750D
Doc ID 8028 Rev 11
17/49
Instructions
6.3
M95160-x, M95080-x
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.
The status and control bits of the Status Register are as follows:
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
6.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 5.) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 5.
Status Register format
b7
SRWD
b0
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
18/49
Doc ID 8028 Rev 11
M95160-x, M95080-x
Figure 9.
Instructions
Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
MSB
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI02031E
Doc ID 8028 Rev 11
19/49
Instructions
6.4
M95160-x, M95080-x
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 10.
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the selftimed write cycle that takes tW to complete (as specified in Table 21, Table 22, Table 23,
Table 24, Table 26 and Table 27).
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write
cycle tW, and, 0 when the write cycle is complete. The WEL bit (Write enable latch) is also
reset at the end of the write cycle tW.
The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 and SRWD bits:
●
The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read only, as defined in Table 3.
●
The SRWD bit (Status Register Write Disable bit), in accordance with the signal read
on the Write Protect pin (W), allows the user to set or reset the Write protection mode
of the Status Register itself, as defined in Table 6. When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the tW Write cycle.
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
Table 6.
Protection modes
W
SRWD
signal
bit
1
0
0
0
1
0
1
1
Mode
Write protection of the
Status Register
Status Register is
writable (if the WREN
Software- instruction has set the
protected WEL bit)
(SPM)
The values in the BP1
and BP0 bits can be
changed
Memory content
Protected area(1)
Unprotected area(1)
Write-protected
Ready to accept
Write instructions
Status Register is
Hardware- Hardware write-protected
protected The values in the BP1
Write-protected
(HPM)
and BP0 bits cannot be
changed
Ready to accept
Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 3.
20/49
Doc ID 8028 Rev 11
M95160-x, M95080-x
Instructions
The protection features of the device are summarized in Table 6.
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases need to be considered, depending on the state of the Write Protect (W) input pin:
●
If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction.
●
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are software-protected (SPM) by the Block
Protect (BP1, BP0) bits in the Status Register, are also hardware-protected against
data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
●
either setting the SRWD bit after driving the Write Protect (W) input pin low
●
or driving the Write Protect (W) input pin low after setting the SRWD bit
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
Table 7.
Address range bits(1)
Device
M95160-x
M95080-x
A10-A0
A9-A0
Address bits
1. b15 to b11 are Don’t Care on the M95160-x.
b15 to b10 are Don’t Care on the M95080-x.
Figure 10. Write Status Register (WRSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register In
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI02282D
Doc ID 8028 Rev 11
21/49
Instructions
6.5
M95160-x, M95080-x
Read from Memory Array (READ)
As shown in Figure 11., to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 11. Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
1
0
MSB
Data Out 1
High Impedance
7
Q
6
5
4
3
2
Data Out 2
1
0
7
MSB
AI01793D
1. Depending on the memory size, as shown in Table 7., the most significant address bits are Don’t Care.
22/49
Doc ID 8028 Rev 11
M95160-x, M95080-x
6.6
Instructions
Write to Memory Array (WRITE)
As shown in Figure 12., to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period tW (as specified in Table 22. to Table 26.), at the end of which the Write in Progress
(WIP) bit is reset to 0.
In the case of Figure 12., Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte. If,
though, Chip Select (S) continues to be driven low, as shown in Figure 13., the next byte of
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
Note:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
●
if a Write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
●
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 12. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte
1
0
7
6
5
4
3
2
1
0
High Impedance
Q
AI01795D
1. Depending on the memory size, as shown in Table 7., the most significant address bits are Don’t Care.
Doc ID 8028 Rev 11
23/49
Instructions
M95160-x, M95080-x
Figure 13. Page Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte 1
1
0
7
6
5
4
3
2
0
1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Data Byte 2
D
7
6
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte N
1
0
6
5
4
3
2
1
0
AI01796D
1. Depending on the memory size, as shown in Table 7., the most significant address bits are Don’t Care.
24/49
Doc ID 8028 Rev 11
M95160-x, M95080-x
Delivery state
7
Delivery state
7.1
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
8
Maximum rating
Stressing the device outside the ratings listed in Table 8. may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 8.
Absolute maximum ratings
Symbol
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
TSTG
Storage temperature
–65
150
°C
TLEAD
Lead temperature during soldering
TA
Parameter
See note (1)
°C
VO
Output voltage
–0.50
VCC+0.6
V
VI
Input voltage
–0.50
6.5
V
VCC
Supply voltage
–0.50
6.5
V
VESD
Electrostatic discharge voltage (human body model)(2)
–4000
4000
V
®
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω)
Doc ID 8028 Rev 11
25/49
DC and AC parameters
9
M95160-x, M95080-x
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 9.
Operating conditions (M95160 and M95080)
Symbol
VCC
TA
Table 10.
Parameter
Min.
Max.
Unit
Supply voltage
4.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Ambient operating temperature (device grade 3)
–40
125
°C
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Ambient operating temperature (device grade 3)
–40
125
°C
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Min.
Max.
Unit
Supply voltage
1.7
5.5
V
Ambient operating temperature
–40
85
°C
Operating conditions (M95160-W and M95080-W)
Symbol
VCC
TA
Table 11.
Parameter
Operating conditions (M95160-R and M95080-R)
Symbol
VCC
TA
Table 12.
Parameter
Operating conditions (M95160-F)(1)
Symbol
VCC
TA
Parameter
1. Preliminary data.
Table 13.
AC measurement conditions(1)
Symbol
CL
Parameter
Min.
Load capacitance
Max.
30
Input rise and fall times
Unit
pF
50
ns
Input pulse voltages
0.2VCC to 0.8VCC
V
Input and output timing reference voltages
0.3VCC to 0.7VCC
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
26/49
Typ.
Doc ID 8028 Rev 11
M95160-x, M95080-x
DC and AC parameters
Figure 14. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825B
Table 14.
Symbol
COUT
CIN
Capacitance(1)
Parameter
Test condition
Max.
Unit
VOUT = 0 V
8
pF
Input capacitance (D)
VIN = 0 V
8
pF
Input capacitance (other pins)
VIN = 0 V
6
pF
Output capacitance (Q)
Min.
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.
Table 15.
Symbol
DC characteristics (M95160 and M95080, device grade 3)
Parameter
Test condition
Min.
Max.
Unit
ILI
Input leakage current
VIN = VSS or VCC
±2
µA
ILO
Output leakage current
S = VCC, VOUT = VSS or VCC
±2
µA
ICC
Supply current
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 5 V, Q = open
3
mA
ICC1
Supply current (Standby) S = VCC, VCC = 5 V, VIN = VSS or VCC
5
µA
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
0.4
V
VOL
(1)
Output low voltage
IOL = 2 mA, VCC = 5 V
VOH (1) Output high voltage
VRES(2)
IOH = –2 mA, VCC = 5 V
Internal reset threshold
voltage
0.8 VCC
2.5
V
3.5
V
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Characterized only, not 100% tested.
Doc ID 8028 Rev 11
27/49
DC and AC parameters
Table 16.
Symbol
M95160-x, M95080-x
DC characteristics (M95160 and M95080, device grade 6)
Parameter
Test conditions
Min.
Max.
Unit
ILI
Input leakage current
VIN = VSS or VCC
±2
µA
ILO
Output leakage current
S = VCC, VOUT = VSS or VCC
±2
µA
ICC
Supply current
C = 0.1VCC/0.9VCC at 10 MHz,
VCC = 5 V, Q = open
5
mA
ICC1
Supply current
(Standby)
S = VCC, VCC = 5 V,
VIN = VSS or VCC
2
µA
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL(1)
Output low voltage
IOL = 2 mA, VCC = 5 V
0.4
V
Output high voltage
IOH = –2 mA, VCC = 5 V
VOH
(1)
VRES(2)
Internal reset threshold
voltage
0.8 VCC
2.5
V
3.5
V
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Characterized only, not 100% tested.
Table 17.
Symbol
DC characteristics (M95160-W and M95080-W, device grade 3)
Parameter
Test conditions
Max.
Unit
ILI
Input leakage
current
VIN = VSS or VCC
±2
µA
ILO
Output leakage
current
S = VCC, VOUT = VSS or VCC
±2
µA
ICC
Supply current
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open
2
mA
ICC1
Supply current
(Standby)
S = VCC, VCC = 2.5 V, VIN = VSS or VCC
2
µA
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL
Output low voltage
0.4
V
VOH
Output high voltage IOH = –0.4 mA, VCC = 2.5 V
VRES(1)
IOL = 1.5 mA, VCC = 2.5 V
Internal reset
threshold voltage
0.8 VCC
1.0
1. Characterized only, not 100% tested.
28/49
Min.
Doc ID 8028 Rev 11
V
1.65
V
M95160-x, M95080-x
Table 18.
Symbol
DC and AC parameters
DC characteristics (M95160-W and M95080-W, device grade 6)
Parameter
Test conditions
Min.
Max.
Unit
ILI
Input leakage
current
VIN = VSS or VCC
±2
µA
ILO
Output leakage
current
S = VCC, VOUT = VSS or VCC
±2
µA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5V, Q = open, Process SA
2
mA
C = 0.1VCC/0.9VCC at 10 MHz,
VCC = 2.5 V, Q = open, Process GB or
SB
5
mA
S = VCC, 2.5 V
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