M95256-RMC6TG

M95256-W M95256-R M95256-DF Datasheet 256-Kbit serial SPI bus EEPROM with high-speed clock Features SO8N • • (150 mil width) • TSSOP8 (169 mil width) • • • UFDFPN8 (DFN8) (2 x 3 mm) WLSCP8 (1.289 x 1.376 mm) Product status link M95256-DF M95256-R M95256-W • • • • • Compatible with the serial peripheral interface (SPI) bus Memory array – 256-Kbit (32 Kbytes) of EEPROM – Page size: 64 bytes – Additional write lockable page (Identification page) Write time – Byte Write within 5 ms – Page Write within 5 ms Write protect – quarter array – half array – whole memory array High-speed clock: 20 MHz Single supply voltage: – 2.5 V to 5.5 V for M95256-W – 1.8 V to 5.5 V for M95256-R – 1.7 V to 5.5 V for M95256-DF Operating temperature range: from -40 °C up to +85 °C Enhanced ESD protection More than 4 million Write cycles More than 200-year data retention Packages – SO8N (ECOPACK2) – TSSOP8 (ECOPACK2) – UFDFPN8 (ECOPACK2) – WLCSP8 (ECOPACK2) DS4712 - Rev 22 - September 2021 For further information contact your local STMicroelectronics sales office. www.st.com M95256-W M95256-R M95256-DF Description 1 Description The M95256 devices are electrically erasable programmable memories (EEPROMs) organized as 32768 x 8 bits, accessed through the SPI bus. The M95256-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95256-R can operate with a supply voltage from 1.8 V to 5.5 V and the M95256-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C. The M95256-DF, -DR or -DW (hereinafter referred to as M95256-Dx) offer an additional page, named the Identification page (64 bytes). The Identification page can be used to store sensitive application parameters that can be (later) permanently locked in read-only mode. Figure 1. Logic diagram VCC D C S M95xxx Q W HOLD VSS The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is selected when Chip select (S) is driven low. Communications with the device can be interrupted when the HOLD is driven low. Table 1. Signal names Signal name DS4712 - Rev 22 Function Direction C Serial clock Input D Serial data input Input Q Serial data output Output S Chip select Input W Write protect Input HOLD Hold Input VCC Supply voltage - VSS Ground - page 2/51 M95256-W M95256-R M95256-DF Description Figure 2. 8-pin package connections (top view) M95xxx 1. S 1 8 VCC Q 2 7 HOLD W 3 6 C VSS 4 5 D See Section 10 Package information for package dimensions, and how to identify pin 1. Figure 3. WLCSP connections 1 A 2 HOLD B C 3 Q Q S 2 1 HOLD VSS VSS D VCC W W Marking side (top view) C D D C A B S VCC D E 3 C E Bump side (bottom view) MS69235 MS51613V1 Table 2. Signals versus bump position DS4712 - Rev 22 Position A B C D E 1 HOLD - VCC - C 2 - S - D - 3 Q - VSS - W page 3/51 M95256-W M95256-R M95256-DF Block diagram 2 Block diagram The memory is organized as shown in the following figure. Figure 4. Block diagram DATA REGISTER + ECC /S SENSE AMPLIFIERS X DECODER PAGE LATCHES Q I/O D C HOLD 1. = Identification page DS4712 - Rev 22 STATUS REGISTER CONTROL LOGIC Y DECODER ARRAY W CUSTOM AREA(1) HV GENERATOR + SEQUENCER ADDRESS REGISTER MS67262 page 4/51 M95256-W M95256-R M95256-DF Signal description 3 Signal description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Section 9 DC and AC parameters). These signals are described next. 3.1 Serial data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial clock (C). 3.2 Serial data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial clock (C). 3.3 Serial clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial data input (D) are latched on the rising edge of Serial clock (C). Data on Serial data output (Q) change from the falling edge of Serial clock (C). 3.4 Chip select (S) When this input signal is high, the device is deselected and Serial data output (Q) is at high impedance. The device is in the Standby power mode, unless an internal Write cycle is in progress. Driving Chip select (S) low selects the device, placing it in the Active power mode. After power-up, a falling edge on Chip select (S) is required prior to the start of any instruction. 3.5 Hold (HOLD) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial data output (Q) is high impedance, and Serial data input (D) and Serial clock (C) are Don’t care. To start the Hold condition, the device must be selected, with Chip select (S) driven low. 3.6 Write protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status register). This pin must be driven either high or low, and must be stable during all Write instructions. 3.7 VCC supply voltage VCC is the supply voltage. 3.8 VSS ground VSS is the reference for all signals, including the VCC supply voltage. DS4712 - Rev 22 page 5/51 M95256-W M95256-R M95256-DF Connecting to the SPI bus 4 Connecting to the SPI bus All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial data input (D) is sampled on the first rising edge of the Serial clock (C) after Chip select (S) goes low. All output data bytes are shifted out of the device, most significant bit first. The Serial data output (Q) is latched on the first falling edge of the Serial clock (C) after the instruction (such as the Read from Memory array and Read Status register instructions) have been clocked into the device. Figure 5. Bus master and memory devices on the SPI bus VCC SPI interface with (CPOL, CPHA) = (0, 0) or 1, 1) SDO SDI SCK C Q D SPI bus master R CS3 CS2 CS1 VCC SPI memory device S W HOLD (1) (1) C Q D R VCC SPI memory device C Q D R SPI memory device S W HOLD (1) VCC (1) S W HOLD (1) (1) VSS 1. The Write protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate. MS19755V3 Figure 5 shows an example of three memory devices connected to an SPI bus master. Only one memory device is selected at a given time, so only one memory device drives the Serial data output (Q) line at that time. The other memory devices are in high impedance state. The pull-up resistor R ensures that a device is not selected if the Bus master leaves the S line in the high impedance state. In applications where the bus master can enter a state where the whole input/output SPI bus is high-impedance at a given time (for example, if the bus master is reset during the transmission of an instruction), it is advised to connect the clock line (C) to an external pull-down resistor so that, if all inputs/outputs become high-impedance, the C line is pulled low (while the S line is pulled high). This ensures that S and C do not become high at the same time, and so, that the tSHCH requirement is met. The typical value of R is 100 kΩ. DS4712 - Rev 22 page 6/51 M95256-W M95256-R M95256-DF SPI modes 4.1 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two modes: • CPOL = 0, CPHA = 0 • CPOL = 1, CPHA = 1 For these two modes, input data is latched in on the rising edge of Serial clock (C), and output data is available from the falling edge of Serial clock (C). The difference between the two modes, as shown in Figure 6, is the clock polarity when the bus master is in Stand-by mode and not transferring data: • C remains at 0 for (CPOL = 0, CPHA = 0) • C remains at 1 for (CPOL = 1, CPHA = 1) Figure 6. SPI modes supported CPOL CPHA 0 0 C 1 1 C D Q DS4712 - Rev 22 MSB MSB page 7/51 M95256-W M95256-R M95256-DF Operating features 5 Operating features 5.1 Supply voltage (VCC) 5.1.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 9 DC and AC parameters). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually in the range between 10 and 100 nF) close to the VCC / VSS device pins. 5.1.2 Device reset In order to prevent erroneous instruction decoding and inadvertent Write operations during power‑up, a power‑on‑reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the POR threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 9 DC and AC parameters). At power-up, when VCC passes over the POR threshold, the device is reset and is in the following state: • • • in Standby power mode, deselected, Status register values: – the Write enable latch (WEL) bit is reset to 0 – the Write in progress (WIP) bit is reset to 0 – the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits). It is important to note that the device must not be accessed until VCC reaches a valid and stable level within the specified [VCC(min), VCC(max)] range, as defined under Operating conditions in Section 9 DC and AC parameters. 5.1.3 Power-up conditions When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip select (S) line is not allowed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 5. Bus master and memory devices on the SPI bus). In addition, the Chip select (S) input offers a built-in safety feature, as the S input is edge-sensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip select (S). This ensures that Chip select (S) must have been high, prior to going low to start the first operation. The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Section 9 DC and AC parameters. 5.1.4 Power-down During power-down (continuous decrease of the VCC supply voltage below the minimum VCC operating voltage defined in Section 9 DC and AC parameters), the device must be: • deselected (Chip select S must be allowed to follow the voltage applied on VCC) • DS4712 - Rev 22 in Standby power mode (there must not be any internal write cycle in progress) page 8/51 M95256-W M95256-R M95256-DF Active power and Standby power modes 5.2 Active power and Standby power modes When Chip select (S) is low, the device is selected, and in the Active power mode. The device consumes ICC. When Chip select (S) is high, the device is deselected. If a Write cycle is not currently in progress, the device then goes into the Standby power mode, and the device consumption drops to ICC1, as specified in DC characteristics (see Section 9 DC and AC parameters). 5.3 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. To enter the Hold condition, the device must be selected, with Chip select (S) low. During the Hold condition, the Serial data output (Q) is high impedance, and the Serial data input (D) and the Serial clock (C) are Don’t care. Normally, the device is kept selected for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition has the effect of resetting the state of the device: this mechanism can be used, if required, to reset the ongoing processes. This resets the internal logic, except the WEL and WIP bits of the Status register. In the specific case where the device has moved in a Write command (Inst + Address + data bytes, each data byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command. Figure 7. Hold condition activation C HOLD Hold condition Hold condition The Hold condition starts when the Hold (HOLD) signal is driven low when Serial clock (C) is already low (as shown in Figure 7). Figure 7 also shows what happens if the rising and falling edges are not timed to coincide with Serial clock (C) being low. 5.4 Status register The Status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.3 Read Status register (RDSR) for a detailed description of the Status register bits. DS4712 - Rev 22 page 9/51 M95256-W M95256-R M95256-DF Data protection and protocol control 5.5 Data protection and protocol control The device features the following data protection mechanisms: • Before accepting the execution of the Write and Write Status register instructions, the device checks whether the number of clock pulses comprised in the instructions is a multiple of eight. • All instructions that modify data must be preceded by a Write enable (WREN) instruction to set the Write enable latch (WEL) bit. • The Block protect (BP1, BP0) bits in the Status register are used to configure part of the memory as read‑only. • The Write protect (W) signal is used (in conjunction with the SRWD bit) to protect the Block protect (BP1, BP0) bits in the Status register. For any instruction to be accepted, and executed, Chip select (S) must be driven high after the rising edge of Serial clock (C) for the last bit of the instruction, and before the next rising edge of Serial clock (C). Two points to note in the previous sentence: • The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status register (RDSR) and Read (READ) instructions). • The “next rising edge of Serial clock (C)” might (or might not) be the next bus transaction for some other device on the SPI bus. Table 3. Write-protected block size Status register bits DS4712 - Rev 22 Protected block Protected array addresses 0 None None 0 1 Upper quarter 6000h - 7FFFh 1 0 Upper half 4000h - 7FFFh 1 1 Whole memory 0000h - 7FFFh BP1 BP0 0 page 10/51 M95256-W M95256-R M95256-DF Instructions 6 Instructions Each command is composed of bytes (MSBit transmitted first), initiated with the instruction byte, as summarized in Table 4. If an invalid instruction is sent (one not contained in Table 4), the device automatically enters in a Wait state until deselected. Table 4. Instruction set Instruction Description Instruction format WREN Write enable 0000 0110 WRDI Write disable 0000 0100 RDSR Read Status register 0000 0101 WRSR Write Status register 0000 0001 READ Read from Memory array 0000 0011 WRITE Write to Memory array 0000 0010 (1) Read Identification page 1000 0011 WRID(1) Write Identification page 1000 0010 RDLS(1) Reads the Identification page lock status 1000 0011 Locks the Identification page in read-only mode 1000 0010 RDID LID(1) 1. Instruction available only for the M95256-D device. For read and write commands to memory array and Identification page the address is defined by two bytes as explained in the following table. Table 5. Significant bits within the address bytes Instruction READ or WRITE RDID or WRID RDLS or LID Note: DS4712 - Rev 22 MSB address byte LSB address byte b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 x A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 A5 A4 A3 A2 A1 A0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 A: Significant address bit. x: bit is Don’t care. page 11/51 M95256-W M95256-R M95256-DF Write enable (WREN) 6.1 Write enable (WREN) The Write enable latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write enable instruction to the device. As shown in Figure 8, to send this instruction to the device, Chip select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial data input (D). The device then enters a wait state. It waits for the device to be deselected by Chip select (S) being driven high. Figure 8. Write enable (WREN) sequence S 0 1 2 3 4 5 6 7 C Instruction D Q DS4712 - Rev 22 High impedance MS41478V1 page 12/51 M95256-W M95256-R M95256-DF Write disable (WRDI) 6.2 Write disable (WRDI) One way of resetting the Write enable latch (WEL) bit is to send a Write disable instruction to the device. As shown in Figure 9, to send this instruction to the device, Chip select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial data input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip select (S) being driven high. The Write enable latch (WEL) bit, in fact, becomes reset by any of the following events: • Power-up • WRDI instruction execution • WRSR instruction completion • WRITE instruction completion. Figure 9. Write disable (WRDI) sequence S 0 1 2 3 4 5 6 7 C Instruction D Q DS4712 - Rev 22 High Impedance page 13/51 M95256-W M95256-R M95256-DF Read Status register (RDSR) 6.3 Read Status register (RDSR) The Read Status register (RDSR) instruction is used to read the Status register. The Status register may be read at any time, even while a Write or Write Status register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write in progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status register continuously, as shown in Figure 10. Figure 10. Read Status register (RDSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction D Q High impedance Status Register Out 7 MSB 6 5 4 3 2 1 Status Register Out 0 7 6 5 4 MSB 3 2 1 0 7 MS47548V1 The status and control bits of the Status register are detailed in the following subsections. 6.3.1 WIP bit The Write in progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such cycle is in progress. 6.3.2 WEL bit The Write enable latch (WEL) bit indicates the status of the internal Write enable latch. When set to 1, the internal Write enable latch is set. When set to 0, the internal Write enable latch is reset, and no Write or Write Status Register instruction is accepted. The WEL bit is returned to its reset state by the following events: • Power-up • Write Disable (WRDI) instruction completion • Write Status Register (WRSR) instruction completion • Write (WRITE) instruction completion 6.3.3 BP1, BP0 bits The Block protect (BP1, BP0) bits are non volatile. They define the size of the area to be software-protected against Write instructions. These bits are written with the Write Status register (WRSR) instruction. When one or both of the Block protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3. Writeprotected block size) becomes protected against Write (WRITE) instructions. The Block protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. DS4712 - Rev 22 page 14/51 M95256-W M95256-R M95256-DF Read Status register (RDSR) 6.3.4 SRWD bit The Status register Write Disable (SRWD) bit is operated in conjunction with the Write protect (W) signal. The Status register Write Disable (SRWD) bit and Write protect (W) signal enable the device to be put in the Hardware Protected mode (when the Status register Write Disable (SRWD) bit is set to 1, and Write protect (W) is driven low). In this mode, the non-volatile bits of the Status register (SRWD, BP1, BP0) become read-only bits and the Write Status register (WRSR) instruction is no longer accepted for execution. Table 6. Status register format b7 SRWD b0 0 0 0 BP1 BP0 WEL WIP Status register Write protect Block protect bits Write enable latch bit Write in progress bit DS4712 - Rev 22 page 15/51 M95256-W M95256-R M95256-DF Write Status register (WRSR) 6.4 Write Status register (WRSR) The Write Status register (WRSR) instruction is used to write new values to the Status register. Before it can be accepted, a Write enable (WREN) instruction must have been previously executed. The Write Status register (WRSR) instruction is entered by driving Chip select (S) low, followed by the instruction code, the data byte on Serial Data input (D) and Chip select (S) driven high. Chip select (S) must be driven high after the rising edge of Serial clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial clock (C). Otherwise, the Write Status register (WRSR) instruction is not executed. The following figure shows the instruction sequence. Figure 11. Write Status register (WRSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction D Status Register In 7 6 5 4 3 2 1 0 MSB Q High impedance MS47556V1 Driving the Chip select (S) signal high at a byte boundary of the input data triggers the self-timed Write cycle that takes tW to complete (as specified in AC tables in Section 9 DC and AC parameters). While the Write Status register cycle is in progress, the Status register may still be read to check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed Write cycle tW, and 0 when the Write cycle is complete. The WEL bit (Write enable latch) is also reset at the end of the Write cycle tW. The Write Status register (WRSR) instruction enables the user to change the values of the BP1, BP0 and SRWD bits: • The Block protect (BP1, BP0) bits define the size of the area that is to be treated as read-only, as defined in Table 3. • The SRWD (Status register Write Disable) bit, in accordance with the signal read on the Write protect pin (W), enables the user to set or reset the Write protection mode of the Status register itself, as defined in Table 7. When in Write-protected mode, the Write Status register (WRSR) instruction is not executed. The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including the tW Write cycle. The Write Status register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in the Status register. Bits b6, b5, b4 are always read as 0. DS4712 - Rev 22 page 16/51 M95256-W M95256-R M95256-DF Write Status register (WRSR) Table 7. Protection modes W signal SRWD bit 1 0 0 0 1 1 0 1 Memory content Mode Softwareprotected (SPM) Hardwareprotected (HPM) Write protection of the Status register Status register is writable (if the WREN instruction has set the WEL bit). The values in the BP1 and BP0 bits can be changed. Status register is Hardware write-protected. The values in the BP1 and BP0 bits cannot be changed. Protected area (1) Unprotected area(1) Writeprotected Ready to accept Write instructions Writeprotected Ready to accept Write instructions 1. As defined by the values in the Block protect (BP1, BP0) bits of the Status register. See Table 3. The protection features of the device are summarized in Table 7. When the Status register Write Disable (SRWD) bit in the Status register is 0 (its initial delivery state), it is possible to write to the Status register (provided that the WEL bit has previously been set by a WREN instruction), regardless of the logic level applied on the Write protect (W) input pin. When the Status register Write Disable (SRWD) bit in the Status register is set to 1, two cases should be considered, depending on the state of the Write protect (W) input pin: • If Write protect (W) is driven high, it is possible to write to the Status register (provided that the WEL bit has previously been set by a WREN instruction). • If Write protect (W) is driven low, it is not possible to write to the Status register even if the WEL bit has previously been set by a WREN instruction. (Attempts to write to the Status register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area, which are Softwareprotected (SPM) by the Block protect (BP1, BP0) bits in the Status register, are also hardware-protected against data modification. Regardless of the order of the two events, the Hardware-protected mode (HPM) can be entered by: • either setting the SRWD bit after driving the Write protect (W) input pin low, • or driving the Write protect (W) input pin low after setting the SRWD bit. Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to pull high the Write protect (W) input pin. If the Write protect (W) input pin is permanently tied high, the Hardware-protected mode (HPM) can never be activated, and only the Software-protected mode (SPM), using the Block protect (BP1, BP0) bits in the Status register, can be used. DS4712 - Rev 22 page 17/51 M95256-W M95256-R M95256-DF Read from Memory array (READ) 6.5 Read from Memory array (READ) As shown in Figure 12, to send this instruction to the device, Chip select (S) is first driven low. The bits of the instruction byte and address bytes are then shifted in, on Serial data input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial data output (Q). Figure 12. Read from Memory array (READ) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D 3 2 1 0 MSB High Impedance Q Data Out 1 7 6 5 4 3 Data Out 2 2 1 0 7 MSB Note: Depending on the memory size, as shown in Table 5. Significant bits within the address bytes, the most significant address bits are Don’t care. If Chip select (S) continues to be driven low, the internal address register is incremented automatically, and the byte of data at the new address is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip select (S) high. The rising edge of the Chip select (S) signal can occur at any time during the cycle. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. DS4712 - Rev 22 page 18/51 M95256-W M95256-R M95256-DF Write to Memory array (WRITE) 6.6 Write to Memory array (WRITE) As shown in Figure 13, to send this instruction to the device, Chip select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial data input (D). The instruction is terminated by driving Chip select (S) high at a byte boundary of the input data. The self‑timed Write cycle, triggered by the Chip select (S) rising edge, continues for a period tW (as specified in AC characteristics in Section 9 DC and AC parameters), at the end of which the Write in Progress (WIP) bit is reset to 0. Figure 13. Byte Write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction D Q 16-bit address 15 14 13 Data byte 3 2 1 0 7 6 5 4 3 2 1 0 High impedance Note: Depending on the memory size, as shown in Table 5. Significant bits within the address bytes, the most significant address bits are Don’t care. In the case of Figure 13, Chip select (S) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. However, if Chip select (S) continues to be driven low (as shown in Figure 14), the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal Write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If more bytes are sent than will fit up to the end of the page, a condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size are overwritten from location 0 of the same page. The instruction is not accepted, and is not executed, under the following conditions: • if the Write enable latch (WEL) bit has not been set to 1 (by executing a Write enable instruction just before), • if a Write cycle is already in progress, • if the device has not been deselected, by driving high Chip select (S), at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in), • if the addressed page is in the region protected by the Block protect (BP1 and BP0) bits. Note: The self-timed write cycle tW is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as “1”. DS4712 - Rev 22 page 19/51 M95256-W M95256-R M95256-DF Write to Memory array (WRITE) Figure 14. Page Write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D Data Byte 1 3 2 1 0 7 6 5 4 3 2 1 0 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data Byte 2 D 1. DS4712 - Rev 22 Data Byte 3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Byte N 6 5 4 3 2 1 0 Depending on the memory size, as shown in Table 5. Significant bits within the address bytes, the most significant address bits are Don’t care. page 20/51 M95256-W M95256-R M95256-DF Write to Memory array (WRITE) 6.6.1 Cycling with Error Correction Code (ECC x 4) The M95256 devices offer an error correction code (ECC) logic. The ECC is an internal logic function transparent for the SPI communication protocol. The ECC logic is implemented on each group of four EEPROM bytes (A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer. Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group. As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the four bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in Table 13. Cycling performance by groups of four bytes. DS4712 - Rev 22 page 21/51 M95256-W M95256-R M95256-DF Read Identification page (available only in M95256-D devices) 6.7 Read Identification page (available only in M95256-D devices) The Identification page (64 bytes) is an additional page that can be written and (later) permanently locked in Read-only mode. This page is read with the Read Identification page instruction (see Table 4. Instruction set). The Chip select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial data input (D). Address bit A10 must be 0, upper address bits are Don't care, and the data byte pointed to by the lower address bits [A5:A0] is shifted out on Serial data output (Q). If Chip select (S) continues to be low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. The number of bytes to read in the ID page must not exceed the page boundary, otherwise unexpected data are read (for instance when reading the ID page from location 24d, the number of bytes must be lower than or equal to 40d, as the ID page boundary is 64 bytes). The read cycle is terminated by driving Chip select (S) high. The rising edge of the Chip select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a write cycle is currently in progress. Figure 15. Read Identification page sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction D 16-bit address 15 14 13 3 2 1 0 MSB Q High impedance Data Out 1 7 6 5 4 3 2 Data Out 2 1 0 7 MSB DS4712 - Rev 22 page 22/51 M95256-W M95256-R M95256-DF Write Identification page (available only in M95256-D devices) 6.8 Write Identification page (available only in M95256-D devices) The Identification page (64 bytes) is an additional page that can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification page instruction (see Table 4. Instruction set). The Chip select signal (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in on Serial data input (D). Address bit A10 must be 0, upper address bits are Don't care, the lower address bits [A5:A0] define the byte address within the Identification page. The instruction sequence is shown in Figure 16. Figure 16. Write Identification page sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction D 16-bit address 15 14 13 3 2 Data byte 1 0 7 6 5 4 3 2 1 0 High impedance Q DS4712 - Rev 22 page 23/51 M95256-W M95256-R M95256-DF Read Lock status (available only in M95256-D devices) 6.9 Read Lock status (available only in M95256-D devices) The Read Lock status instruction (see Table 4. Instruction set) is used to check whether the Identification page is locked or not in Read-only mode. The Read Lock status sequence is defined with the Chip select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial data input (D). Address bit A10 must be 1, all other address bits are Don't care. The Lock bit is the LSB (least significant bit) of the byte read on Serial data output (Q). It is at “1” when the lock is active and at “0” when the lock is not active. If Chip select (S) continues to be driven low, the same data byte is shifted out. The read cycle is terminated by driving Chip select (S) high. The following figure shows the instruction sequence. Figure 17. Read Lock status sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-bit address 15 14 13 D 3 2 1 0 MSB Data Out 1 High impedance Q 7 6 5 4 3 2 Data Out 2 1 0 7 MSB DS4712 - Rev 22 page 24/51 M95256-W M95256-R M95256-DF Lock ID (available only in M95256-D devices) 6.10 Lock ID (available only in M95256-D devices) The Lock ID instruction permanently locks the Identification page in read-only mode. Before this instruction can be accepted, a Write enable (WREN) instruction must have been executed. The Lock ID instruction is issued by driving Chip select (S) low, sending the instruction code, the address and a data byte on Serial data input (D), and driving Chip select (S) high. In the address sent, A10 must be equal to 1, all other address bits are Don't Care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't care. Chip select (S) must be driven high after the rising edge of Serial clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial clock (C). Otherwise, the Lock ID instruction is not executed. Driving Chip select (S) high at a byte boundary of the input data triggers the self-timed write cycle whose duration is tW (as specified in AC characteristics in Section 9 DC and AC parameters). The instruction sequence is shown in Figure 18. The instruction is discarded, and is not executed, under the following conditions: • If a Write cycle is already in progress • If Block protect bits (BP1,BP0) = (1,1) • If a rising edge on Chip select (S) happens outside of a byte boundary. • If the Write enable latch (WEL) bit has not been set to 1 (by executing a Write enable instruction just before) Figure 18. Lock ID sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction D 16-bit address 15 14 13 3 2 Data byte 1 0 7 6 5 4 3 2 1 0 High impedance Q DS4712 - Rev 22 page 25/51 M95256-W M95256-R M95256-DF Power-up and delivery state 7 Power-up and delivery state 7.1 Power-up state After power-up, the device is in the following state: • Standby power mode • Deselected (after power-up, a falling edge is required on Chip select (S) before any instructions can be started) • Not in the Hold condition • The Write enable latch (WEL) is reset to 0 • Write in progress (WIP) is reset to 0 The SRWD, BP1 and BP0 bits of the Status register are unchanged from the previous power-down (they are non-volatile bits). 7.2 Initial delivery state The device is delivered with the memory array and Identification page bits set to all 1s (each byte = FFh). The Status register Write Disable (SRWD) and Block protect (BP1 and BP0) bits are initialized to 0. DS4712 - Rev 22 page 26/51 M95256-W M95256-R M95256-DF Maximum ratings 8 Maximum ratings Stressing the device outside the ratings listed in Table 8 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 8. Absolute maximum ratings Symbol Parameter Min. Max. TAMB Ambient operating temperature –40 130 TSTG Storage temperature –65 150 TLEAD Lead temperature during soldering See note °C (1) VO Output voltage –0.50 VCC + 0.6 VI Input voltage –0.50 6.5 VCC Supply voltage –0.50 6.5 IOL DC output current (Q = 0) - 5 IOH DC output current (Q = 1) - 5 Electrostatic discharge voltage (human body model) (2) - 4000 VESD Unit V mA V 1. Compliant with JEDEC standard J-STD-020 (for small-body, Sn-Pb or Pb free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS directive 2011/65/EU of July 2011). 2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-Q100-002 (compliant with ANSI/ESDA/JEDEC JS-001-2012, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω). DS4712 - Rev 22 page 27/51 M95256-W M95256-R M95256-DF DC and AC parameters 9 DC and AC parameters This section summarizes the operating conditions and the DC/AC characteristics. Table 9. Operating conditions (M95256-W, device grade 6) Symbol Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature –40 85 °C Min. Max. Unit Supply voltage 1.8 5.5 V Ambient operating temperature -40 85 °C Min. Max. Unit Supply voltage 1.7 5.5 V Ambient operating temperature –40 85 °C Min. Max. Unit Load capacitance - 100 pF - Input rise and fall times - 25 ns - Input pulse voltages 0.2 VCC to 0.8 VCC V - Input and output timing reference voltages 0.3 VCC to 0.7 VCC V VCC TA Parameter Table 10. Operating conditions (M95256-R, device grade 6) Symbol VCC TA Parameter Table 11. Operating conditions (M95256-DF, device grade 6) Symbol VCC TA Parameter Table 12. AC measurement conditions Symbol CL Parameter Figure 19. AC measurement I/O waveform Input Levels Input and Output Timing Reference Levels 0.8 ₓ VCC 0.7 ₓ VCC 0.3 ₓ VCC 0.2 ₓ VCC DS4712 - Rev 22 page 28/51 M95256-W M95256-R M95256-DF DC and AC parameters Table 13. Cycling performance by groups of four bytes Symbol Ncycle Parameter Write cycle endurance(1) Test condition Min. Max. TA ≤ 25 °C, VCC(min) < VCC < VCC(max) - 4,000,000 TA = 85 °C, VCC(min) < VCC < VCC(max) - 1,200,000 Unit Write cycle(2) 1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer. The Write cycle endurance is evaluated by characterization and qualification. 2. A Write cycle is executed when either a Page write, a Byte write, a WRSR, a WRID or an LID instruction is decoded. When using the Byte write, the Page write or the WRID instruction, refer also to Section 6.6.1 Cycling with Error Correction Code (ECC x 4). Table 14. Memory cell data retention Parameter Test condition Min. Max. Unit - 200 Year TA = 55 °C Data retention(1) 1. The data retention behaviour is checked in production, while the 200-year limit is evaluated by characterization and qualification results. Table 15. Capacitance Symbol COUT CIN Test condition(1) Min. Max. Unit VOUT = 0 V - 8 pF Input capacitance (D) VIN = 0 V - 8 pF Input capacitance (other pins) VIN = 0 V - 6 pF Parameter Output capacitance (Q) 1. Evaluated By Characterization at TA = 25 °C and frequency of 5 MHz – Not tested in production. DS4712 - Rev 22 page 29/51 M95256-W M95256-R M95256-DF DC and AC parameters Table 16. DC characteristics (M95256-W, device grade 6) Symbol Parameter Test conditions Min. Max. Unit ILI Input leakage current VIN = VSS or VCC - ±2 µA ILO Output leakage current S = VCC, Q = VSS or VCC - ±2 µA - 2 mA - 5 mA - 5 mA - 2 µA - 3 µA VCC = 2.5 V, C = 0.1 VCC / 0.9 VCC ICC Supply current (Read) at 10 MHz, Q = open VCC = 5.5 V, C = 0.1 VCC / 0.9 VCC at 20 MHz, Q = open ICC0 (1) Supply current (Write) During tW, S = VCC, 2.5 V ≤ VCC ≤ 5.5 V S = VCC, VCC= 2.5 V, ICC1 Supply current VIN = VSS or VCC (Standby Power mode) S = VCC, VCC= 5.5 V, VIN = VSS or VCC VIL Input low voltage - –0.45 0.3 VCC V VIH Input high voltage - 0.7 VCC VCC+1 V VOL Output low voltage - 0.4 V VOH Output high voltage 0.8 VCC - V Min Max Unit VCC = 2.5 V and IOL = 1.5 mA or VCC = 5 V and IOL = 2 mA VCC = 2.5 V and IOH = –0.4 mA or VCC = 5 V and IOH = –2 mA 1. Evaluated By Characterization - Not tested in production. Table 17. DC characteristics (M95256-R, device grade 6) Symbol Test conditions(1) Parameter ILI Input leakage current VIN = VSS or VCC - ±2 µA ILO Output leakage current S = VCC, Q = VSS or VCC - ±2 µA ICC Supply current (Read) - 2 mA ICC0 (2) Supply current (Write) VCC = 1.8 V , during tW, S = VCC - 3 mA ICC1 Supply current (Standby Power mode) VCC = 1.8 V, S = VCC, VIN = VSS or VCC - 1 µA VIL Input low voltage 1.8 V ≤ VCC < 2.5 V – 0.45 0.25 VCC V VIH Input high voltage 1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC+1 V VOL Output low voltage IOL = 0.15 mA, VCC = 1.8 V - 0.3 V VOH Output high voltage IOH = –0.1 mA, VCC = 1.8 V 0.8 VCC - V VCC= 1.8 V, C = 0.1 VCC / 0.9 VCC at 5 MHz, Q = open 1. If the application uses the M95256-R with 2.5 V < VCC < 5.5 V and - 40 °C < TA < + 85 °C, refer to Table 16. DC characteristics (M95256-W, device grade 6) instead of the above table. 2. Evaluated By Characterization - Not tested in production. DS4712 - Rev 22 page 30/51 M95256-W M95256-R M95256-DF DC and AC parameters Table 18. DC characteristics (M95256-DF, device grade 6) Symbol Test conditions(1) Parameter Min. Max. Unit ILI Input leakage current VIN = VSS or VCC - ±2 µA ILO Output leakage current S = VCC, Q = VSS or VCC - ±2 µA ICC Supply current (Read) - 2 mA ICC0(2) Supply current (Write) VCC = 1.7 V, during tW, S = VCC - 3 mA ICC1 Supply current (Standby) VCC = 1.7 V, S = VCC, VIN = VSS or VCC - 1 µA VIL Input low voltage 1.7 V ≤ VCC < 2.5 V – 0.45 0.25 VCC V VIH Input high voltage 1.7 V ≤ VCC < 2.5 V 0.75 VCC VCC+1 V VOL Output low voltage IOL = 0.15 mA, VCC = 1.7 V - 0.3 V VOH Output high voltage IOH = –0.1 mA, VCC = 1.7 V 0.8 VCC - V VCC = 1.7 V, C = 0.1 VCC / 0.9 VCC, at 5 MHz, Q = open 1. If the application uses the M95256-DF devices at 2.5 V ≤ VCC ≤ 5.5 V and –40 °C ≤ TA ≤ +85 °C, refer to Table 16. DC characteristics (M95256-W, device grade 6), rather than to the above table. 2. Evaluated By Characterization - Not tested in production. DS4712 - Rev 22 page 31/51 M95256-W M95256-R M95256-DF DC and AC parameters Table 19. AC characteristics Test conditions specified either in Table 9, in Table 10 or in Table 11 and in Table 12 Symbol Alt. fC fSCK Parameter Clock frequency 1.7 V ≤ VCC < 2.5 V 2.5 V ≤ VCC < 4.5 V VCC ≥ 4.5V Min. Max. Unit Min. Max. Min. Max. - 5 - 10 - 20 MHz tSLCH tCSS1 S active setup time 60 - 30 - 15 - ns tSHCH tCSS2 S not active setup time 60 - 30 - 15 - ns tSHSL tCS S deselect time 90 - 40 - 20 - ns tCHSH tCSH S active hold time 60 - 30 - 15 - ns tCHSL - S not active hold time 60 - 30 - 15 - ns tCH(1) tCLH Clock high time 80 - 40 - 20 - ns tCL(1) tCLL Clock low time 80 - 40 - 20 - ns tCLCH(2) tRC Clock rise time - 2 - 2 - 2 µs tCHCL(2) tFC Clock fall time - 2 - 2 - 2 µs tDVCH tDSU Data in setup time 20 - 10 - 5 - ns tCHDX tDH Data in hold time 20 - 10 - 10 - ns tHHCH - Clock low hold time after HOLD not active 60 - 30 - 15 - ns tHLCH - Clock low hold time after HOLD active 60 - 30 - 15 - ns tCLHL - Clock low setup time before HOLD active 0 - 0 - 0 - ns tCLHH - Clock low setup time before HOLD not active 0 - 0 - 0 - ns tSHQZ(2) tDIS Output disable time - 80 - 40 - 20 ns tCLQV tV Clock low to output valid - 80 - 40 - 20 ns tCLQX tHO Output hold time 0 - 0 - 0 - ns tQLQH(2) tRO Output rise time - 20 - 20 - 10 ns tQHQL(2) tFO Output fall time - 20 - 20 - 10 ns tHHQV tLZ HOLD high to output valid - 80 - 40 - 20 ns tHLQZ(2) tHZ HOLD low to output High-Z - 80 - 40 - 20 ns tW tWC Write time - 5 - 5 - 5 ms 1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max). 2. Evaluated By Characterization - Not tested in production. DS4712 - Rev 22 page 32/51 M95256-W M95256-R M95256-DF DC and AC parameters Figure 20. Serial input timing tSHSL S tCHSL tCH tSLCH tCHSH tSHCH C tDVCH tCL tCHCL tCLCH tCHDX D LSB IN MSB IN High impedance Q Figure 21. Hold timing S tHLCH tCLHL tHHCH C tCLHH tHLQZ tHHQV Q HOLD Figure 22. Serial output timing S tSHSL tCH C tCLQV tCLCH tCHCL tCL tSHQZ tCLQX Q tQLQH tQHQL D DS4712 - Rev 22 ADDR LSB IN page 33/51 M95256-W M95256-R M95256-DF Package information 10 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 10.1 SO8N package information SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package. Figure 23. SO8N – Outline h x 45˚ A A2 c ccc b e 0.25 mm D GAUGE PLANE k 8 E1 1 E A1 L L1 1. DS4712 - Rev 22 Drawing is not to scale. page 34/51 M95256-W M95256-R M95256-DF SO8N package information Table 20. SO8N – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.170 - 0.230 0.0067 - 0.0091 D 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. Figure 24. SO8N - Recommended footprint 3.9 6.7 0.6 (x8) 1.27 1. DS4712 - Rev 22 Dimensions are expressed in millimeters. page 35/51 M95256-W M95256-R M95256-DF TSSOP8 package information 10.2 TSSOP8 package information TSSOP8 is an 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package. Figure 25. TSSOP8 – Outline D 8 5 c E1 1 E 4 α A1 CP A2 A b 1. L L1 e Drawing is not to scale. Table 21. TSSOP8 – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.200 - - 0.0472 A1 0.050 - 0.150 0.0020 - 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 CP - - 0.100 - - 0.0039 D 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1 4.300 4.400 4.500 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - α 0° - 8° 0° - 8° 1. Values in inches are converted from mm and rounded to four decimal digits. DS4712 - Rev 22 page 36/51 M95256-W M95256-R M95256-DF TSSOP8 package information Figure 26. TSSOP8 – Recommended footprint 2.3 1.0 7.0 0.65 0.35 1. DS4712 - Rev 22 Dimensions are expressed in millimeters. page 37/51 M95256-W M95256-R M95256-DF UFDFPN8 (DFN8) package information 10.3 UFDFPN8 (DFN8) package information UFDFPN8 is an 8-lead, 2 × 3 mm, 0.55 mm thickness ultra thin profile fine pitch dual flat package. Figure 27. UFDFPN8 - Outline D N A B A ccc C Pin #1 ID marking E A1 C eee C Seating plane A3 Side view 2x aaa C 1 aaa C 2x 2 Top view D2 e 1 2 L3 Datum A b L1 L L3 Pin #1 ID marking E2 K L e/2 L1 e Terminal tip Detail “A” Even terminal ND-1 x e Bottom view 1. 2. 3. 4. DS4712 - Rev 22 See Detail “A” Maximum package warpage is 0.05 mm. Exposed copper is not systematic and can appear partially or totally according to the cross section. Drawing is not to scale. The central pad (the area E2 by D2 in the above illustration) must be either connected to VSS or left floating (not connected) in the end application. page 38/51 M95256-W M95256-R M95256-DF UFDFPN8 (DFN8) package information Table 22. UFDFPN8 - Mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.450 0.550 0.600 0.0177 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 b(2) 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 1.900 2.000 2.100 0.0748 0.0787 0.0827 D2 1.200 - 1.600 0.0472 - 0.0630 E 2.900 3.000 3.100 0.1142 0.1181 0.1220 E2 1.200 - 1.600 0.0472 - 0.0630 e - 0.500 - - 0.0197 - K 0.300 - - 0.0118 - - L 0.300 - 0.500 0.0118 - 0.0197 L1 - - 0.150 - - 0.0059 L3 0.300 - - 0.0118 - - aaa - - 0.150 - - 0.0059 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee(3) - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 3. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. Figure 28. UFDFPN8 - Recommended footprint 1.400 0.500 0.300 0.600 1.200 1.300 1. DS4712 - Rev 22 Dimensions are expressed in millimetres. page 39/51 M95256-W M95256-R M95256-DF WLCSP8 (CS) package information 10.4 WLCSP8 (CS) package information This WLCSP is a 8-bump, 1.289 x 1.376 mm, 0.4 mm pitch wafer level chip scale package. Figure 29. WLCSP8 - Outline bbb Z D X e2 Y e Detail A E e3 aaa Reference F Wafer back side H A A2 (4X) e1 G Orientation Bump side Side view Bump A1 eee Z b Ø ccc M Ø ddd M Z Z X Y Z Detail A Rotated 90 ° 1. 2. 3. DS4712 - Rev 22 Seating plane Drawing is not to scale Primary datum Z and seating plane are defined by the spherical crowns of the bump. Bump position designation per JESD 95-1, SPP-010. page 40/51 M95256-W M95256-R M95256-DF WLCSP8 (CS) package information Table 23. WLCSP8 - Mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.500 0.540 0.580 0.0197 0.0213 0.0228 A1 - 0.190 - - 0.0075 - A2 - 0.350 - - 0.0138 - b(2) - 0.270 - - 0.0106 - D - 1.289 1.309 - 0.0507 0.0515 E - 1.376 1.396 - 0.0542 0.0550 e - 0.800 - - 0.0315 - e1 - 0.693 - - 0.0273 - e2 - 0.400 - - 0.0157 - e3 - 0.400 - - 0.0157 - F - 0.342 - - 0.0135 - G - 0.245 - - 0.0096 - H - 0.245 - - 0.0096 - aaa - 0.110 - - 0.0043 - bbb - 0.110 - - 0.0043 - ccc - 0.110 - - 0.0043 - ddd - 0.060 - - 0.0024 - eee - 0.060 - - 0.0024 - 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 30. WLCSP8 - Recommended footprint 0.400 0.800 0.693 0.400 8 bumps x Ø 0.270 1. DS4712 - Rev 22 Dimensions are expressed in millimeters. page 41/51 M95256-W M95256-R M95256-DF Ordering information 11 Ordering information Table 24. Ordering information scheme Example: M95 256 -D W MN 6 T P \K Device type M95 = SPI serial access EEPROM Device function 256 = 256 Kbit Device family Blank = Without Identification page D = With additional Identification page Operating voltage W = VCC = 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V F = VCC = 1.7 to 5.5 V Package(1) MN = SO8N (150 mil width) DW = TSSOP8 (169 mil width) MC = UFDFPN8 (DFN8) CS = WLCSP8 Device grade 6 = Industrial temperature range, –40 to 85 °C Device tested with standard test flow Option blank = tube packing T = Tape and reel packing Plating technology G or P = RoHS compliant and halogen-free (ECOPACK2) Process(2) /K = Manufacturing technology code 1. All packages are ECOPACK2 (RoHS-compliant and free of brominated, chlorinated and antimony-oxide flame retardants). 2. These process letters appear on the device package (marking) and on the shipment box. Please contact your nearest ST Sales Office for further information Note: DS4712 - Rev 22 Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. page 42/51 M95256-W M95256-R M95256-DF Revision history Table 25. Document revision history Date Revision Changes 17‑Nov‑1999 2.1 New -V voltage range added (including the tables for DC characteristics, AC characteristics, and ordering information). 07‑Feb-2000 2.2 New -V voltage range extended to M95256 (including AC characteristics, and ordering information). 22‑Feb-2000 2.3 tCLCH and tCHCL, for the M95xxx-V, changed from 1ms to 100ns 15-Mar-2000 2.4 -V voltage range changed to 2.7-3.6V 29-Jan-2001 2.5 12-Jun-2001 2.6 Lead Soldering Temperature in the Absolute Maximum Ratings table amended Illustrations and Package Mechanical data updated Correction to header of Table 12B TSSOP14 Illustrations and Package Mechanical data updated Document promoted from Preliminary Data to Full Data Sheet 08-Feb-2002 2.7 Announcement made of planned upgrade to 10 MHz clock for the 5V, –40 to 85°C, range. 09-Aug-2002 2.8 M95128 split off to its own datasheet. Data added for new and forthcoming products, including availability of the SO8 narrow package. 24-Feb-2003 2.9 Omission of SO8 narrow package mechanical data remedied 26-Jun-2003 2.10 -V voltage range removed 21-Nov-2003 3.0 Table of contents, and Pb-free options added. -S voltage range extended to -R. VIL(min) improved to –0.45V 17-Mar-2004 4.0 Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified 21-Oct-2004 5.0 M95128 datasheet merged back in. Product List summary table added. AEC-Q100-002 compliance. Device Grade information clarified. tHHQX corrected to tHHQV. 10MHz product becomes standard M95128 part numbers removed from document. PDIP8 package removed. Delivery state paragraph added. Section 3.8: Operating supply voltage (VCC) added and information removed below Section 4: Operating features. Power up state removed below Section 6: Delivery state. Figure 18: SPI modes supported modified and Note 2 added. Note 1 added to Table 8. 13-Apr-2006 6 ICC1 specified over the whole VCC range and ICC0 added in Table 14, Table 15 and Table 16. ICC specified over the whole VCC range in Table 14. Table 17: AC Characteristics (M95256, Device Grade 6) added. tCHHL and tCHHH replaced by tCLHL and tCLHH, respectively. Figure 21: Hold timing modified. Process added to Table 25: Ordering information scheme. Note 1 added to Table 25. Note 1 removed from Table 20: AC characteristics (M95256-DR, M95256-R device grade 6). TA added to Table 7: Absolute maximum ratings. Order of sections modified. M95256-DF with device grade 6 temperature range removed. Section 3.7: VSS ground added, Section 3.8: Operating supply voltage (VCC) modified. Small text changes. 15-Oct-2007 7 Section 5.4: Write Status Register (WRSR), Section 5.5: Read from Memory Array (READ) and Section 6: Delivery state updated. Note 2 below Figure 17: Bus master and memory devices on the SPI bus removed, replaced by explanatory paragraph. TLEAD added to Table 7: Absolute maximum ratings. DS4712 - Rev 22 page 43/51 M95256-W M95256-R M95256-DF Date Revision Changes Test conditions modified for ICC0 and ICC1, and VIH min modified in Table 17: AC characteristics (M95256, device grade 3). tW modified and “preliminary data” note removed in Table 20: AC characteristics (M95256-DR, M95256-R device grade 6). Blank option removed below Plating technology, process A modified and process V removed in Table 25: Ordering information scheme. Table 26: Available M95256x products (package, voltage range, temperature grade) added. SO8N and SO8W package specifications updated (see Section 10: Package mechanical data). Package mechanical data: inches calculated from mm and rounded to 3 decimal digits. Section 3.8: Operating supply voltage (VCC) modified. Small text changes. Frequency corrected on page 1. 27-Mar-2008 8 VIL and VIH modified in Table 16: DC characteristics (M95256-R, M95256-DR, device grade 6). AB Process added to Table 25: Ordering information scheme. 15-Jul-2008 9 WLCSP package added (see Figure 3: WLCSP connections (top view, marking side, with balls on the underside) and Section 10: Package mechanical data). Updated Section 3.8: Operating supply voltage (VCC) Updated Section 4.3: Data protection and protocol control Updated Section 5.4: Write Status Register (WRSR) 24-Jun-2010 10 Added note in Section 5.6: Write to Memory Array (WRITE) Updated Table 7: Absolute maximum ratings Added Table 20: AC characteristics (M95256-DR, M95256-R device grade 6) Updated Table 20: AC characteristics (M95256-DR, M95256-R device grade 6) Updated Section 1: Description. 07-Sep-2010 11 Updated Section 5.7: Read Identification Page (available only in M95256-DR devices). Updated Section 5.8: Write Identification Page. Updated Section 5.9: Read Lock Status (available only in M95256-DR devices). Updated Features. Updated Section 5.8: Write Identification Page. Added Figure 25: TSSOP8 – 8 lead thin shrink small outline, package outline. 12-Nov-2010 12 Added Table 23: UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3 mm, package mechanical data. Updated Section 11: Part numbering. Updated Table 26: Available M95256x products (package, voltage range, temperature grade). Updated Figure 25, Figure 26. Deleted: • SO8 (MW) picture under Features • SO8 (MW) mechanical dimensions Updated: 22-Mar-2011 13 • UFDFPN8 (MB) with UFDFPN8 (MB, MC) picture under Features • Section 5.6.1: ECC (error correction code) and Write cycling • Section 7: Connecting to the SPI bus • Table 7: Absolute maximum ratings Process letter K substituted with only concerned products (M95256-D and M95256 in MLP8 package MC).9 DS4712 - Rev 22 page 44/51 M95256-W M95256-R M95256-DF Date Revision Changes Rephrased “test condition” text in: • Table 14: DC characteristics (M95256, device grade 3) • Table 20: DC characteristics (current M95080-W products) • Table 16: DC characteristics (M95256-W, device grade 3) • Table 23: DC characteristics (current and new M95080-R and M95080-DR products) • Table 18: AC characteristics (M95256, device grade 3) • Table 31: AC characteristics, M95080-W, device grade 6 • table 20: AC characteristics (M95256-W, device grade 3) • Table 36: AC characteristics (M95080-R, M95080-DR device grade 6) Added: • Caution under Figure 3: WLCSP connections (top view, marking side, with balls on the underside) • MC = UFDFPN8 package in Section 11: Part numbering Updated: 20-May-2011 14 • Added: • 19-Jul-2011 15 UFDFPN8 offered in only one package version Table 15: Memory cell characteristics MC package added (UFDFPN8) Updated: • 23-Nov-2011 17-Jan-2012 16 17 Footnote 3 below Table 7: Absolute maximum ratings • Footnotes 1, 2, 4, 5 below Table 15: DC characteristics (M95256-W, device grade 6) • Footnotes 1, 2, 3, 5 below Table 17: DC characteristics (M95256-R, M95256-DR, device grade 6) • Table 19: AC characteristics, M95256-W, device grade 6 headings, TQLQH and TQHQL values. One footnote removed and one added • Table 21: AC characteristics (M95256-DR, M95256-R device grade 6), new columns for new pairs of products. Footnote 2 edited. Updated Figure 25: UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package outline. Datasheet split into: • M95256-125 datasheet for automotive products (range 3) • M95256-W, M95256-R, M95256-DR, M95256-DF (this datasheet) for standard products (range 6). Added: • 21-Jun-2012 18 1.7 V device (M95256-DF) Updated: • Figure 15: Block diagram • Table 58: M95080-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data and Figure 42: M95080-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline • Cycling and data retention values (Table 19 and Table 20) Deleted: • UFDFPN8 package rev MB Updated: 24-Jul-2012 19 • WLCSP package reference from “CT” to “CS” • Figure 3: WLCSP connections (top view, marking side, with bumps on the underside) • Figure 42: M95080-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline. Document reformatted. Updated: 09-Apr-2013 20 • Package figure on cover page • Section 7.2: Initial delivery state • Note (1) in Table 7: Absolute maximum ratings Deleted former footnote 1 in Table 17: DC characteristics (M95256-DF, device grade 6). Replaced “ball” by “bump” in the entire document. DS4712 - Rev 22 page 45/51 M95256-W M95256-R M95256-DF Date Revision Changes Removed obsolete product M95256-DR. Updated Features, Section 1: Description and Section 6: Instructions. 06-Mar-2017 21 Updated Figure 1: Logic diagram, Figure 3: WLCSP connections (top view, marking side, with bumps on the underside), Figure 4: Block diagram, Figure 6: SPI modes supported, Figure 8: Write Enable (WREN) sequence and Figure 9: Write Disable (WRDI) sequence. Updated Table 1: Signal names, tables in Section 6: Instructions and Table 11: AC measurement conditions. Updated footnote 2 of Table 7: Absolute maximum ratings and added footnote 6 to Table 15: DC characteristics (M95256-W, device grade 6). Updated Section 10: Package information and its subsections. Added: • Table 2. Signals versus bump position Updated: 28-Sep-2021 22 • Section 1 Description • Figure 4. Block diagram • Section 4 Connecting to the SPI bus • Figure 5. Bus master and memory devices on the SPI bus • Figure 16. Write Identification page sequence • Table 15. Capacitance • Table 19. AC characteristics • Section 11 Ordering information Deleted: DS4712 - Rev 22 • Table 19. AC characteristics (M95256-W, device grade 6) • Table 20. AC characteristics (M95256-R, device grade 6) page 46/51 M95256-W M95256-R M95256-DF Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4 3.1 Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Serial data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Serial clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.4 Chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.5 Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.6 Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 5 Operating features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 5.1 6 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Active power and Standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.4 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 6.1 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3 Read Status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DS4712 - Rev 22 6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 page 47/51 M95256-W M95256-R M95256-DF Contents 6.3.4 6.4 Write Status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.5 Read from Memory array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.6 Write to Memory array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.6.1 7 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Cycling with Error Correction Code (ECC x 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.7 Read Identification page (available only in M95256-D devices) . . . . . . . . . . . . . . . . . . . . . . . 22 6.8 Write Identification page (available only in M95256-D devices) . . . . . . . . . . . . . . . . . . . . . . . 23 6.9 Read Lock status (available only in M95256-D devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.10 Lock ID (available only in M95256-D devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 10 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 11 10.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.2 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.3 UFDFPN8 (DFN8) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.4 WLCSP package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 DS4712 - Rev 22 page 48/51 M95256-W M95256-R M95256-DF List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . Signals versus bump position . . . . . . . . . . . . . . . Write-protected block size . . . . . . . . . . . . . . . . . . Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . Significant bits within the address bytes . . . . . . . . Status register format . . . . . . . . . . . . . . . . . . . . . Protection modes. . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . Operating conditions (M95256-W, device grade 6) . Operating conditions (M95256-R, device grade 6) . Operating conditions (M95256-DF, device grade 6) AC measurement conditions . . . . . . . . . . . . . . . . Cycling performance by groups of four bytes . . . . . Memory cell data retention . . . . . . . . . . . . . . . . . Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . DC characteristics (M95256-W, device grade 6). . . DC characteristics (M95256-R, device grade 6) . . . DC characteristics (M95256-DF, device grade 6) . . AC characteristics . . . . . . . . . . . . . . . . . . . . . . . SO8N – Mechanical data . . . . . . . . . . . . . . . . . . TSSOP8 – Mechanical data . . . . . . . . . . . . . . . . UFDFPN8 - Mechanical data . . . . . . . . . . . . . . . . WLCSP8 - Mechanical data. . . . . . . . . . . . . . . . . Ordering information scheme. . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . DS4712 - Rev 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 10 11 11 15 17 27 28 28 28 28 29 29 29 30 30 31 32 35 36 39 41 42 43 page 49/51 M95256-W M95256-R M95256-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. DS4712 - Rev 22 Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . 8-pin package connections (top view) . . . . . . . . WLCSP connections . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . Bus master and memory devices on the SPI bus. SPI modes supported . . . . . . . . . . . . . . . . . . . Hold condition activation . . . . . . . . . . . . . . . . . Write enable (WREN) sequence . . . . . . . . . . . . Write disable (WRDI) sequence . . . . . . . . . . . . Read Status register (RDSR) sequence . . . . . . . Write Status register (WRSR) sequence . . . . . . Read from Memory array (READ) sequence . . . Byte Write (WRITE) sequence . . . . . . . . . . . . . Page Write (WRITE) sequence . . . . . . . . . . . . Read Identification page sequence . . . . . . . . . . Write Identification page sequence . . . . . . . . . . Read Lock status sequence . . . . . . . . . . . . . . . Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . AC measurement I/O waveform . . . . . . . . . . . . Serial input timing . . . . . . . . . . . . . . . . . . . . . . Hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . Serial output timing . . . . . . . . . . . . . . . . . . . . . SO8N – Outline . . . . . . . . . . . . . . . . . . . . . . . SO8N - Recommended footprint . . . . . . . . . . . . TSSOP8 – Outline . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Recommended footprint. . . . . . . . . . UFDFPN8 - Outline . . . . . . . . . . . . . . . . . . . . . UFDFPN8 - Recommended footprint . . . . . . . . . WLCSP8 - Outline. . . . . . . . . . . . . . . . . . . . . . WLCSP8 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 3 . 4 . 6 . 7 . 9 12 13 14 16 18 19 20 22 23 24 25 28 33 33 33 34 35 36 37 38 39 40 41 page 50/51 M95256-W M95256-R M95256-DF IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS4712 - Rev 22 page 51/51