M95M04-DWMN3TP/V

M95M04-A125 M95M04-A145 Datasheet Automotive 4-Mbit serial SPI bus EEPROM Features TSSOP8 169 mil width SO8N • • • • • 150 mil width • Maximum clock frequency – 10 MHz full range of VCC • • Schmitt trigger inputs for noise filtering Short write cycle time – Byte write within 4 ms – Page write within 4 ms ESD protection (human body model) – 4000 V Packages – RoHS-compliant and halogen-free (ECOPACK2) – TSSOP8 package ECOPACK2 – SO8N package ECOPACK2 Product status link M95M04-A125 M95M04-A145 AEC-Q100 grade 0 conform qualification Compatible with the serial peripheral interface (SPI) bus Memory array – 4-Mbit (512-Kbyte) of EEPROM – Page size: 512-byte – Write protection by block: 1/4, 1/2 or whole memory Additional write lockable page (identification page) Extended temperature and voltage range – Up to 145 °C (VCC from 2.9 V to 5.5 V) • • DS11938 - Rev 4 - August 2023 For further information contact your local STMicroelectronics sales office. www.st.com M95M04-A125 M95M04-A145 Description 1 Description The M95M04-A125 and M95M04-A145 are 4-Mbit serial EEPROM automotive grade devices operating up to 145 °C. They are compliant with the very high level of reliability defined by the automotive standard AEC-Q100 grade 0. The devices are accessed by a simple serial SPI compatible interface running at up to 10 MHz. The memory array is based on advanced true EEPROM technology (electrically erasable programmable memory). The M95M04-A125 and M95M04-A145 are byte-alterable memories (524288 × 8 bits) organized as 1024 pages of 512 bytes in which the data integrity is significantly improved with an embedded error correction code logic. The M95M04-A125 and M95M04-A145 offer an additional identification page (512 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters that can later be permanently locked in read-only mode. Figure 1. Logic diagram DATA REGISTER + ECC S SENSE AMPLIFIERS PAGE LATCHES X DECODER W ARRAY I/O STATUS REGISTER Y DECODER Q D CONTROL LOGIC C HOLD DS11938 - Rev 4 CUSTOM AREA HV GENERATOR + SEQUENCER ADDRESS REGISTER page 2/40 M95M04-A125 M95M04-A145 Description Figure 2. 8-pin package connections S Q W VSS 1. 1 2 3 4 8 7 6 5 VCC HOLD C D See Section 9 Package information for package dimensions and how to identify pin-1. Table 1. Signal names DS11938 - Rev 4 Signal name Description C Serial clock D Serial data input Q Serial data output S Chip select W Write protect HOLD Hold VCC Supply voltage VSS Ground page 3/40 M95M04-A125 M95M04-A145 Signal description 2 Signal description All input signals must be held high or low (according to voltages of VIH or VIL, as specified in Table 14). These signals are described below. 2.1 Serial data output (Q) This output signal is used to transfer data serially out of the device during a read operation. Data is shifted out on the falling edge of serial clock (C), most significant bit (MSB) first. In all other cases, the serial data output is in high impedance. 2.2 Serial data input (D) This input signal is used to transfer data serially into the device. D input receives instructions, addresses, and the data to be written. Values are latched on the rising edge of serial clock (C), most significant bit (MSB) first. 2.3 Serial clock (C) This input signal allows to synchronize the timing of the serial interface. Instructions, addresses, or data present at serial data input (D) are latched on the rising edge of serial clock (C). Data on serial data output (Q) changes after the falling edge of serial clock (C). 2.4 Chip select (S) Driving chip select (S) low selects the device in order to start communication. Driving chip select (S) high deselects the device and serial data output (Q) enters the high impedance state. 2.5 Hold (HOLD) The hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. 2.6 Write protect (W) This pin is used to write-protect the status register. 2.7 VSS ground VSS is the reference for all signals, including the VCC supply voltage. 2.8 VCC supply voltage VCC is the supply voltage pin. Refer to Section 3.1 Active power and standby power modes and to Section 5.1 Supply voltage (VCC). DS11938 - Rev 4 page 4/40 M95M04-A125 M95M04-A145 Operating features 3 Operating features 3.1 Active power and standby power modes When chip select (S) is low, the device is selected and in the active power mode. When chip select (S) is high, the device is deselected. If a write cycle is not currently in progress, the device then goes in to the standby power mode, and the device consumption drops to ICC1, as specified in Table 14. 3.2 SPI modes The device can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: • • CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of serial clock (C), and output data is available from the falling edge of serial clock (C). The difference between the two modes, as shown in Figure 3, is the clock polarity when the bus master is in stand-by mode and not transferring data: • • C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Figure 3. SPI modes supported CPOL CPHA 0 0 C 1 1 C D Q DS11938 - Rev 4 MSB MSB page 5/40 M95M04-A125 M95M04-A145 Hold mode 3.3 Hold mode The hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. The hold mode starts when the hold (HOLD) signal is driven low and the serial clock (C) is low (as shown in Figure 4). During the hold mode, the serial data output (Q) is high impedance, and the signals present on serial data input (D) and serial clock (C) are not decoded. The hold mode ends when the hold (HOLD) signal is driven high and the serial clock (C) is or becomes low. Figure 4. Hold mode activation C HOLD Hold condition Hold condition Deselecting the device while it is in hold mode resets the paused communication. 3.4 3.4.1 Protocol control and data protection Protocol control The chip select (S) input offers a built-in safety feature, as the S input is edge-sensitive as well as level-sensitive: after power-up, the device is not selected until a falling edge has first been detected on chip select (S). This ensures that chip select (S) must have been high prior to going low, in order to start the first operation. For Write commands (WRITE, WRSR, WRID, LID) to be accepted and executed: • • • • • the write enable latch (WEL) bit must be set by a write enable (WREN) instruction a falling edge and a low state on chip select (S) during the whole command must be decoded instruction, address and input data must be sent as multiple of eight bits the command must include at least one data byte chip select (S) must be driven high exactly after a data byte boundary Write command can be discarded at any time by a rising edge on chip select (S) outside of a byte boundary. To execute read commands (READ, RDSR, RDID, RDLS), the device must decode: • • a falling edge and a low level on chip select (S) during the whole command instruction and address as multiples of eight bits (byte) From this step, data bits are shifted out until the rising edge on chip select (S). DS11938 - Rev 4 page 6/40 M95M04-A125 M95M04-A145 Protocol control and data protection 3.4.2 Status register and data protection The status register format is shown in Figure 5 and the status and control bits of the status register are as follows: Figure 5. Status register format Note: Bits b6, b5, and b4 are always read as 0. WIP bit The WIP bit (write in progress) is a read-only flag that indicates the ready/busy state of the device. When a write command (WRITE, WRSR, WRID) has been decoded and a write cycle (tW) is in progress, the device is busy and the WIP bit is set to 1. When WIP=0, the device is ready to decode a new command. During a write cycle, reading continuously the WIP bit allows to detect when the device becomes ready (WIP=0) to decode a new command. Note: During a write lock ID, the device is busy but the WIP bit stays stable set to 0. WEL bit The WEL bit (write enable latch) bit is a flag that indicates the status of the internal write enable latch. When WEL is set to 1, the Write instructions (WRITE, WRSR, WRID, LID) are executed; when WEL is set to 0, any decoded Write instruction is not executed. The WEL bit is set to 1 with the WREN instruction. The WEL bit is reset to 0 after the following events: • • Write disable (WRDI) instruction completion Write instructions (WRITE, WRSR, WRID, LID) completion including the write cycle time tW • Power-up BP1, BP0 bits The block protect bits (BP1, BP0) are non-volatile. BP1,BP0 bits define the size of the memory block to be protected against write instructions, as defined in Figure 5. These bits are written with the write status register (WRSR) instruction, provided that the status register is not protected (refer to “SRWD bit and W input signal”). DS11938 - Rev 4 page 7/40 M95M04-A125 M95M04-A145 Identification page Table 2. Write-protected block size Status register bits Protected block Protected array addresses 0 None None 0 1 Upper quarter 6.00.00h - 7.FF.FFh 1 0 Upper half 4.00.00h - 7.FF.FFh 1 1 Whole memory 0.00.00h - 7.FF.FFh plus Identification page BP1 BP0 0 SRWD bit and W input signal The status register write disable (SRWD) bit is operated in conjunction with the write protect pin (W) signal. When the SRWD bit is written to 0, it is possible to write the status register, regardless of whether the pin write protect (W) is driven high or low. When the SRWD bit is written to 1, two cases have to be considered, depending on the state of the W input pin: • • Case 1: if pin W is driven high, it is possible to write the status register. Case 2: if pin W is driven low, it is not possible to write the status register (WRSR is discarded) and therefore SRWD,BP1,BP0 bits cannot be changed (the size of the protected memory block defined by BP1,BP0 bits is frozen). Case 2 can be entered in either sequence: • • Writing SRWD bit to 1 after driving pin W low, or Driving pin W low after writing SRWD bit to 1. The only way to exit case 2 is to pull pin W high. Note: if pin W is permanently tied high, the status register cannot be write-protected. The protection features of the device are summarized in Table 3. Table 3. Protection modes 3.5 SRWD bit W signal 0 X 1 1 1 0 Status Status register is writable Status Register is write-protected Identification page The M95M04-A125 and M95M04-A145 offer an identification page (512 bytes) in addition to the 4 Mbits memory. The identification page contains two fields: • • Note: DS11938 - Rev 4 Device identification: the three first byte are programmed by STMicroelectronics with the device identification code, as shown in Table 4. Application parameters: the bytes after the device identification code are available for application specific data. If the end application does not need to read the device identification code, this field can be overwritten and used to store application-specific data. Once the application-specific data are written in the Identification page, the whole Identification page should be permanently locked in Read-only mode. The read, write, lock identification page instructions are detailed in Section 4 Instructions. page 8/40 M95M04-A125 M95M04-A145 Identification page Table 4. Device identification bytes Address in Content Value 00h ST manufacturer code 20h 01h SPI family code 00h 02h Memory density code 13h (4 Mbit) identification page DS11938 - Rev 4 page 9/40 M95M04-A125 M95M04-A145 Instructions 4 Instructions Each command is composed of bytes (MSBit transmitted first), initiated with the instruction byte, as summarized in Table 5. If an invalid instruction is sent (one not contained in Table 5), the device automatically enters a Wait state until deselected. Table 5. Instruction set Instruction Description Instruction format WREN Write enable 0000 0110 WRDI Write disable 0000 0100 RDSR Read status register 0000 0101 WRSR Write status register 0000 0001 READ Read from memory array 0000 0011 WRITE Write to memory array 0000 0010 RDID Read identification page 1000 0011 WRID Write identification page 1000 0010 RDLS Reads the identification page lock status. 1000 0011 LID Locks the identification page in read-only mode. 1000 0010 For read and write commands to memory array and identification page, the address is defined by three bytes as explained in Table 6. Table 6. Significant bits within the address bytes Instruction READ or WRITE Upper address byte b23 b22 b21 b20 b19 b18 Middle address byte Lower address byte b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 X(1) X X X X X X X X X X X X X X X X X 0 X A8 A7 A6 A5 A4 A3 A2 A1 A0 X X X X X X X X X X X X X 1 X X RDID or WRID RDLS or LID A18(2) A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 X X X X X X X X 1. X: bit is Don’t care 2. A: Significant address bit DS11938 - Rev 4 page 10/40 M95M04-A125 M95M04-A145 Write enable (WREN) 4.1 Write enable (WREN) The WREN instruction must be decoded by the device before a write instruction (WRITE, WRSR, WRID or LID). As shown in Figure 6, to send this instruction to the device, chip select (S) is driven low, the bits of the instruction byte are shifted in (MSB first) on serial data input (D) after what the chip select (S) input is driven high and the WEL bit is set (status register bit). Figure 6. Write enable (WREN) sequence S 0 1 2 3 4 5 6 7 C Instruction D High Impedance Q 4.2 Write disable (WRDI) One way of resetting the WEL bit (in the status register) is to send a write disable instruction to the device. As shown in Figure 7, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction byte are shifted in (MSB first), on serial data input (D), after what the chip select (S) input is driven high and the WEL bit is reset (status register bit). If a write cycle is currently in progress, the WRDI instruction is decoded and executed and the WEL bit is reset to 0 with no effect on the ongoing write cycle. Figure 7. Write disable (WRDI) sequence S 0 1 2 3 4 5 6 7 C Instruction D Q DS11938 - Rev 4 High Impedance page 11/40 M95M04-A125 M95M04-A145 Read status register (RDSR) 4.3 Read status register (RDSR) The read status register (RDSR) instruction is used to read the content of the status register. As shown in Figure 8, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte are shifted in (MSB first) on serial data Input (D), the status register content is then shifted out (MSB first) on serial data output (Q). If chip select (S) continues to be driven low, the status register content is continuously shifted out. The status register can always be read, even if a Write cycle (tW) is in progress. The status register functionality is detailed in Section 3.4.2 Status register and data protection. Figure 8. Read status register (RDSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction D Q High Impedance Status Register Out 7 MSB DS11938 - Rev 4 6 5 4 3 2 Status Register Out 1 0 7 6 5 4 3 2 1 0 7 MSB page 12/40 M95M04-A125 M95M04-A145 Write status register (WRSR) 4.4 Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. The write status register (WRSR) instruction is entered (MSB first) by driving chip select (S) low, sending the instruction code followed by the data byte on serial data input (D), and driving the chip select (S) signal high. The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including the write cycle (tW). The write status register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0 bits in the status register (see Section 3.4.2). The status register functionality is detailed in Section 3.4.2 Status register and data protection. The instruction is not accepted, and is not executed, if a write cycle is currently in progress. Figure 9. Write status register (WRSR) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction StatusRegister In 7 D High Impedance 6 5 4 3 2 1 0 MSB Q DS11938 - Rev 4 page 13/40 M95M04-A125 M95M04-A145 Read from memory array (READ) 4.5 Read from memory array (READ) The READ instruction is used to read the content of the memory. As shown in Figure 10, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte and address bytes are shifted in (MSB first) on serial data input (D) and the addressed data byte is then shifted out (MSB first) on serial data output (Q). The first addressed byte can be any byte within any page. If chip select (S) continues to be driven low, the internal address register is automatically incremented, and the next byte of data is shifted out. The whole memory can therefore be read with a single READ instruction. When the highest address is reached, the address counter rolls over to zero, allowing the read cycle to be continued indefinitely. The read cycle is terminated by driving chip select (S) high at any time when the data bits are shifted out on serial data output (Q). The instruction is not accepted, and is not executed, if a write cycle is currently in progress. DT13878aV2 Figure 10. Read from memory array (READ) sequence 1. Depending on the memory size, as shown in Table 6, the most significant address bits are don’t care. DS11938 - Rev 4 page 14/40 M95M04-A125 M95M04-A145 Write to memory array (WRITE) 4.6 Write to memory array (WRITE) The WRITE instruction is used to write new data in the memory. As shown in Figure 11, to send this instruction to the device, chip select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in (MSB first), on serial data input (D). The instruction is terminated by driving chip select (S) high at a data byte boundary. Figure 11 shows a single byte write. Figure 11. Byte write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction 23 22 21 D Q Note: 24-bit address 3 2 Data byte 1 0 7 6 5 4 3 2 1 0 High impedance Depending on the memory size, as shown in Table 6, the most significant address bits are "Don’t care". A page write is used to write several bytes inside a page, with a single internal write cycle. For a page write, chip select (S) has to remain low, as shown in Figure 12, so that the next data bytes are shifted in. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the address counter exceeds the page boundary (the page size is 512 bytes), the internal address pointer rolls over to the beginning of the same page where next data bytes will be written. If more than 512-byte are received, only the last 512 bytes are written. For both byte write and page write, the self-timed write cycle starts from the rising edge of chip select (S), and continues for a period tW (as specified in Table 15). The instruction is discarded, and is not executed, under the following conditions: • • • Note: DS11938 - Rev 4 If a write cycle is already in progress If the addressed page is in the region protected by the block protect (BP1 and BP0) bits If one of the conditions defined in Section 3.4.1 Protocol control is not satisfied The self-timed write cycle tW is internally executed as a sequence of two consecutive events: [erase addressed byte(s)], followed by [program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as “1”. page 15/40 M95M04-A125 M95M04-A145 Write to memory array (WRITE) Figure 12. Page write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 1 0 C Instruction 24-bit address 23 D 22 21 3 2 Data byte 1 1 0 7 6 5 4 3 2 S C D Note: DS11938 - Rev 4 7 6 5 4 3 2 Data byte 3 1 0 7 6 5 4 3 2 Data byte N 1 0 6 5 4 3 2 1 0 DT30906V2 Data byte 2 Depending on the memory size, as shown in Table 6, the most significant address bits are "Don’t Care". page 16/40 M95M04-A125 M95M04-A145 Read identification page (RDID) 4.7 Read identification page (RDID) The read identification page instruction is used to read the identification page (additional page of 512 bytes which can be written and later permanently locked in read-only mode). The chip select (S) signal is first driven low, the bits of the instruction byte and address bytes are then shifted in (MSB first) on serial data input (D). Address bit A10 must be 0 and the other upper address bits are Don't Care (it might be easier to define these bits as 0. The data byte pointed to by the lower address bits [A8:A0] is shifted out (MSB first) on serial data output (Q). The first byte addressed can be any byte within the identification page. If chip select (S) continues to be driven low, the internal address register is automatically incremented and the byte of data at the new address is shifted out. Note that there is no roll over feature in the identification page. The address of bytes to read must not exceed the page boundary. The read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at any time when the data bits are shifted out. The instruction is not accepted, and is not executed, if a write cycle is currently in progress. Figure 13. Read identification page sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction 24-bit address 23 22 21 D 3 2 1 0 MSB High impedance Q Data Out 1 7 6 5 4 3 Data Out 2 2 1 0 7 MSB The first three bytes of the identification page offer information about the device itself. Refer to Section 3.5 Identification page for more information. DS11938 - Rev 4 page 17/40 M95M04-A125 M95M04-A145 Write identification page (WRID) 4.8 Write identification page (WRID) The write identification page instruction is used to write the identification page (additional page of 512 bytes, which can also be permanently locked in read-only mode). The chip select signal (S) is first driven low, and then the bits of the instruction byte, address bytes, and at least one data byte are shifted in (MSB first) on serial data input (D). Address bit A10 must be 0 and the other upper address bits are "Don't Care" (it might be easier to define these bits as 0. The lower address bits [A8:A0] define the byte address inside the identification page. The self-timed write cycle starts from the rising edge of chip select (S), and continues for a period tW (as specified in Table 15). Figure 14. Write identification page sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction D 24-bit address 23 22 21 3 2 Data byte 1 0 7 6 5 4 3 2 1 0 High impedance Q Note: The first three bytes of the identification page offer the device identification code (refer to Section 3.5 Identification page for more information). Using the WRID command on these first three bytes overwrites the device identification code. The instruction is discarded, and is not executed, under the following conditions: • • • DS11938 - Rev 4 If a write cycle is already in progress If the block protect bits (BP1,BP0) = (1,1) If one of the conditions defined in Section 3.4.1 Protocol control is not satisfied. page 18/40 M95M04-A125 M95M04-A145 Read lock status (RDLS) 4.9 Read lock status (RDLS) The read lock status instruction is used to read the lock status. To send this instruction to the device, chip select (S) first has to be driven low. The bits of the instruction byte and address bytes are then shifted in (MSB first) on serial data input (D). Address bit A10 must be 1; all other address bits are "Don't Care" (it might be easier to define these bits as 0. The lock bit is the LSB (least significant bit) of the byte read on serial data output (Q). It is at ‘1’ when the lock is active and at ‘0’ when the lock is not active. If chip select (S) continues to be driven low, the same data byte is shifted out. The read cycle is terminated by driving chip select (S) high. The instruction sequence is shown in Figure 15. The read lock status instruction is not accepted and not executed if a write cycle is currently in progress. Figure 15. Read lock status sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C 24-bit address 3 23 22 21 D 2 1 0 MSB Data Out 2 Data Out 1 High impedance 7 Q 6 5 4 3 2 1 0 DT30910V2 Instruction 7 MSB 4.10 Lock identification page (LID) The lock identification page (LID) command is used to permanently lock the identification page in read-only mode. The LID instruction is issued by driving chip select (S) low, sending (MSB first) the instruction code, the address and a data byte on serial data input (D), and driving chip select (S) high. In the address sent, A10 must be equal to 1. All other address bits are "Don't Care" (it might be easier to define these bits as 0. The data byte sent must have the b0 bit equal to 1 (b0 = 1) and the others value of the bits b7 to b1 are "Don't Care". The data byte sent must be equal to the binary value xxxx xxx1, where x = Don't care. The LID instruction is terminated by driving chip select (S) high at a data byte boundary, otherwise, the instruction is not executed. Figure 16. Lock ID sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C D 24-bit address 23 22 21 3 2 Data byte 1 0 7 6 5 4 3 High impedance Q 2 1 0 DT30911V2 Instruction Driving chip select (S) high at a byte boundary of the input data triggers the self-timed write cycle which duration is tW (specified in Table 15). The instruction sequence is shown in Figure 16. The instruction is discarded, and is not executed, under the following conditions: • • • DS11938 - Rev 4 If a write cycle is already in progress If the block protect bits (BP1,BP0) = (1,1) If one of the conditions defined in Section 3.4.1 Protocol control is not satisfied. page 19/40 M95M04-A125 M95M04-A145 Application design recommendations 5 Application design recommendations 5.1 Supply voltage (VCC) 5.1.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 9 and Table 10). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal Write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. 5.1.2 Power-up conditions When the power supply is turned on, VCC continuously rises from VSS to VCC. During this time, the chip select (S) line is not allowed to float but should follow the VCC voltage. The S line must be connected to VCC via a suitable pull-up resistor (see Figure 17). The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 14. To prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the internal threshold voltage (this threshold is defined in the Table 14 as VRES). When VCC passes over the POR threshold, the device is reset and in the following state: • • • In the standby power mode Deselected Status register values: • – Write enable latch (WEL) bit is reset to 0. – Write in progress (WIP) bit is reset to 0. – SRWD, BP1 and BP0 bits remain unchanged (nonvolatile bits). Not in the hold condition As soon as the VCC voltage has reached a stable value within the [VCC(min), VCC(max)] range, the device is ready for operation. DS11938 - Rev 4 page 20/40 M95M04-A125 M95M04-A145 Implementing devices on SPI bus 5.1.3 Power-down At power down, the power-on-reset (POR) circuit resets and locks the device as soon as the VCC reached the internal threshold voltage. During power-down (continuous decrease in the VCC supply voltage below the minimum VCC operating voltage defined in Table 14), the device must be: 5.2 • deselected (chip select (S) should be allowed to follow the voltage applied on VCC), • in standby power mode (there should not be any internal write cycle in progress). Implementing devices on SPI bus Figure 17 shows an example of three devices, connected to the SPI bus master. Only one device is selected at a time, so that only the selected device drives the serial data output (Q) line. All the other devices outputs are then in high impedance. Figure 17. Bus master and memory devices on the SPI bus V CC SPI interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDO SDI SCK C Q D V CC C Q V CC D C Q V CC D SPI bus master R CS3 CS2 CS1 SPI memory device S W HOLD R SPI memory device S W HOLD R SPI memory device S W HOLD V SS Note: DS11938 - Rev 4 The write protect (W) and hold (HOLD) signals must be driven high or low as appropriate. A pull-up resistor connected on each S input (represented in Figure 17) ensures that each device is not selected if the bus master leaves the S line in the high impedance state. page 21/40 M95M04-A125 M95M04-A145 Cycling with error correction code (ECCx4) 5.3 Cycling with error correction code (ECCx4) The error correction code (ECC) is an internal logic function which is transparent for the SPI communication protocol. The ECC logic is implemented on each group of four EEPROM bytes (a group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group (a group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in Table 8. DS11938 - Rev 4 page 22/40 M95M04-A125 M95M04-A145 Delivery state 6 Delivery state The device is delivered with: • • • DS11938 - Rev 4 the memory array set to all 1s (each byte = FFh), The status register bits set to '0' (byte = 00h), Identification page: the first three bytes define the device identification code (value defined in Table 4). The content of the following bytes is "Don’t care". page 23/40 M95M04-A125 M95M04-A145 Absolute maximum ratings 7 Absolute maximum ratings Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Absolute maximum ratings Symbol Parameter Min. Max. Unit 150 °C 150 °C (1) °C TSTG Storage temperature -65 TAMR Ambient operating temperature -40 TLEAD Lead temperature during soldering See note VO Voltage on Q pin -0.50 VCC + 0.5 V VI Input voltage -0.50 6.5 V IOL DC output current (Q = 0) - 5 mA IOH DC output current (Q = 1) - 5 mA VCC Supply voltage - 0.50 6.5 V VESD Electrostatic pulse (human body model)(2) - 4000 V 1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS directive 2011/65/EU of July 2011). 2. Positive and negative pulses applied on pin pairs, in accordance with AEC-Q100-002 (compliant with ANSI/ESDA/JEDEC JS-001, C1=100 pF, R1=1500 Ω, R2=500 Ω) DS11938 - Rev 4 page 24/40 M95M04-A125 M95M04-A145 DC and AC parameters 8 DC and AC parameters This section summarizes the operating conditions and the DC/AC characteristics of the device. Table 8. Cycling performance by groups of 4 bytes Symboil Parameter Write cycles endurance(1)(2) NCycle Conditions Min. Max. Unit TA ≤ 25 °C, 2.9 V ≤ VCC ≤ 5.5 V - 1 000 000 TA ≤ 85 °C, 2.9 V ≤ VCC ≤ 5.5 V - 500 000 TA ≤ 125 °C, 2.9 V ≤ VCC ≤ 5.5 V - 200 000 TA ≤ 145 °C(4), 2.9 V ≤ VCC ≤ 5.5 V - 100 000 Write cycles(3) 1. The write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer, or for the status register byte (refer also to Cycling with error correction code (ECCx4)). The write cycle endurance is evaluated by characterization – not tested in production. 2. In case of intensive write status register in the application, contact you local ST sales 3. A write cycle is executed when either a page write, a byte write, a WRSR, or a WRID instruction is decoded. When using the byte write, the page write or the WRID, refer also to Cycling with error correction code (ECCx4). 4. For temperature range 4 only. Table 9. Operating conditions (voltage range W, temperature range 4) Symbol Conditions Min. Max. Unit Supply voltage - 2.9 5.5 V TA Ambient operating temperature - -40 145 °C fC Operating clock frequency - 10 MHz Conditions Min. Max. Unit Supply voltage - 2.9 5.5 V TA Ambient operating temperature - -40 125 °C fC Operating clock frequency - 10 MHz VCC Parameter 5.5 V ≥ VCC ≥ 2.9 V, capacitive load on Q pin ≤ 100 pF Table 10. Operating conditions (voltage range W, temperature range 3) Symbol VCC Parameter 5.5 V ≥ VCC ≥ 2.9 V, capacitive load on Q pin ≤ 100 pF Table 11. AC measurement conditions DS11938 - Rev 4 Symbol Parameter Min. Max. Unit CL Load capacitance - 100 pF - Input rise and fall times - 25 ns - Input pulse voltages 0.2 VCC to 0.8 VCC V - Input and output timing reference voltages 0.3 VCC to 0.7 VCC V page 25/40 M95M04-A125 M95M04-A145 DC and AC parameters Figure 18. AC measurement I/O waveform Input and Output Timing Reference Levels Input Levels 0.8 ₓ VCC DT00825cV2 0.7 ₓ VCC 0.3 ₓ VCC 0.2 ₓ VCC Table 12. Memory cell data retention Parameter Data retention(1) Test conditions Data retention performance per cell 2.9 V ≤ VCC ≤ 5.5 V 10 years at 55 °C after max cycling 1. The data retention endurance is evaluated by characterization – not tested in production. Table 13. Capacitance Symbol Parameter Test conditions (1) Min. Max. Unit COUT Output capacitance (Q) VOUT = 0 V - 8 pF Input capacitance (D) VIN = 0 V - 8 pF Input capacitance (other pins) VIN = 0 V - 6 pF CIN 1. Sampled only, not 100% tested, at TA = 25 °C and at a frequency of 5 MHz. DS11938 - Rev 4 page 26/40 M95M04-A125 M95M04-A145 DC and AC parameters Table 14. DC characteristics Symbol Specific test conditions (in addition to conditions specified in Table 9) Parameter Min. Max. ILI Input leakage current VIN = VSS or VCC - 2 ILO Output leakage current S = VCC, VOUT = VSS or VCC - 3 - 2 VCC = 3.6 V, fC = 10 MHz, ICC Supply current (Read) C = 0.1 VCC/0.9 VCC, Q = open VCC = 5.5 V, fC = 10 MHz, C = 0.1 VCC/0.9 VCC, Q = open ICC0(1) Supply current (Write) 2.9 V < VCC < 5.5 V, during tW, S = VCC t° = amb, VCC = 3.6 V, S = VCC VIN = VSS or VCC t° = amb, VCC = 5.5 V, S = VCC VIN = VSS or VCC t° = 125 °C, VCC = 3.6 V, S = VCC ICC1 Supply current VIN = VSS or VCC (Standby power mode) t° = 125 °C, VCC = 5.5 V, S = VCC VIN = VSS or VCC t° = 145 °C, VCC = 3.6 V, S = VCC VIN = VSS or VCC t° = 145 °C, VCC = 5.5 V, S = VCC VIN = VSS or VCC µA mA - 3 - 2(2) - 2 - 3 - 10 - 15 - 20 - 30 Input low voltage - –0.45 0.3 VCC VIH Input high voltage - 0.7 VCC VCC+1 VOL Output low voltage IOL = 2 mA - 0.4 VOH Output high voltage IOH = –2 mA 0.8 VCC - 0.5 1.5 Internal reset threshold voltage - mA µA VIL VRES(1) Unit V 1. Average value during the write cycle (tW) 2. Characterized only, not 100% tested. DS11938 - Rev 4 page 27/40 M95M04-A125 M95M04-A145 DC and AC parameters Table 15. AC characteristics (10 MHz) Symbol Alt. Min. Max. Unit fC fSCK Clock frequency - 10 MHz tSLCH tCSS1 S active setup time 30 - tSHCH tCSS2 S not active setup time 30 - tSHSL tCS S deselect time 40 - tCHSH tCSH S active hold time 30 - tCHSL - S not active hold time 30 - tCH(1) tCLH Clock high time 40 - (1) tCLL Clock low time 40 - tCLCH(2) tRC Clock rise time - 2 (2) tFC Clock fall time - 2 tCL tCHCL Parameter µs tDVCH tDSU Data in setup time 10 - tCHDX tDH Data in hold time 10 - tHHCH - Clock low hold time after HOLD not active 30 - tHLCH - Clock low hold time after HOLD active 30 - tCLHL - Clock low set-up time before HOLD active 0 - tCLHH - Clock low set-up time before HOLD not active 0 - tSHQZ(2) tDIS Output disable time - 40 Clock low to output valid - 40 tCLQV (3) tV tCLQX tHO Output hold time 0 - tQLQH(2) tRO Output rise time - 40 (2) tFO Output fall time - 40 tHHQV tLZ HOLD high to output valid - 40 tHLQZ(2) tHZ HOLD low to output high-Z - 40 tW tWC Write time - 4(4) tQHQL ns ns ms 1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 2. Value evaluated by characterization – not tested in production. 3. tCLQV must be compatible with tCL (clock low time): if tSU is the Read setup time of the SPI bus master, tCL must be equal to (or greater than) tCLQV+tSU. 4. Write time for LID instruction is 10 ms. DS11938 - Rev 4 page 28/40 M95M04-A125 M95M04-A145 DC and AC parameters Figure 19. Serial input timing tSHSL S tCHSL tCH tSLCH tCHSH tSHCH C tDVCH tCL tCHCL tCLCH tCHDX D LSB IN DT01447dV2 MSB IN High impedance Q Figure 20. Hold timing S tHLCH tCLHL tHHCH C tCLHH tHLQZ tHHQV DT01448cV2 Q HOLD Figure 21. Serial output timing S tSHSL tCH C tCLQV tCLCH tCHCL tCL tSHQZ tCLQX tQLQH tQHQL D DS11938 - Rev 4 ADDR LSB IN DT01449gV2 Q page 29/40 M95M04-A125 M95M04-A145 Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 SO8N package information This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package. Figure 22. SO8N – Outline h x 45˚ A A2 c b ccc e 0.25 mm D GAUGE PLANE SEATING PLANE k C E1 1 E A1 L L1 O7_SO8_ME_V2 8 1. Drawing is not to scale. DS11938 - Rev 4 page 30/40 M95M04-A125 M95M04-A145 SO8N package information Table 16. SO8N – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.170 - 0.230 0.0067 - 0.0091 D(2) 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1(3) 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. Note: The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side. Figure 23. SO8N - Footprint example 1.27 O7_SO8N_FP_V2 3.9 6.7 0.6 (x8) 1. Dimensions are expressed in millimeters. DS11938 - Rev 4 page 31/40 M95M04-A125 M95M04-A145 TSSOP8 package information 9.2 TSSOP8 package information This TSSOP is an 8-lead, 3 x 6.4 mm, 0.65 mm pitch, thin shrink small outline package. Figure 24. TSSOP8 – Outline D 8 5 Seating plane C k E1 E L A1 Pin 1 identification L1 D e E1 A2 A aaa C DT_6P_A_TSSOP8_ME_V4 4 1 c A1 b e 1. Drawing is not to scale. Table 17. TSSOP8 – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.200 - - 0.0472 A1 0.050 - 0.150 0.0020 - 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 D(2) 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1(3) 4.300 4.400 4.500 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° - 8° 0° - 8° aaa - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. DS11938 - Rev 4 page 32/40 M95M04-A125 M95M04-A145 TSSOP8 package information Note: The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of the mold flash, tie bar burrs, gate burrs, and interleads flash, but including any mismatch between the top and bottom of the plastic body. The measurement side for the mold flash, protrusions, or gate burrs is the bottom side. Figure 25. TSSOP8 – Footprint example 1.55 2.35 7.35 DT_6P_TSSOP8_FP_V2 0.65 0.40 5.80 1. Dimensions are expressed in millimeters. DS11938 - Rev 4 page 33/40 M95M04-A125 M95M04-A145 Ordering information 10 Ordering information Table 18. Ordering information scheme Example: M95 M04-D W DW 4 T P /V Device type M95 = SPI serial access EEPROM Device function M04-D = 4 Mbits (512 Kbytes) plus identification page Operating voltage W = VCC = 2.9 V to 5.5 V Package(1) MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) Device grade 3 = -40 to 125 °C. Automotive grade. Device tested with high reliability certified flow 4 = -40 to 145 °C. Automotive grade. Device tested with high reliability certified flow(2) Option T = Tape and reel packing blank = tube packing Planting technology P or G = ECOPACK2 Process /V = Manufacturing technology code 1. All packages are ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimonyoxide flame retardants). 2. The high reliability certified flow (HRCF) is described in quality note QNEE9801. Please ask your nearest ST sales office for a copy. Note: For a list of available options (speed, package, etc.) or for further information on any aspect of the devices, please contact your nearest ST sales office. Engineering samples Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DS11938 - Rev 4 page 34/40 M95M04-A125 M95M04-A145 Revision history Table 19. Document revision history Date Revision 04-Jan-2017 1 Changes Initial release. Updated: • • • 27-Apr-2020 2 Features, Section 3.4.2 Status register and data protection, Section 4.10 Lock identification page (LID), Section 5.3 Cycling with error correction code (ECCx4) Figure 1. Logic diagram Table 6. Significant bits within the address bytes, Table 7. Absolute maximum ratings, Table 8. Cycling performance by groups of 4 bytes, Table 9. Operating conditions (voltage range W, temperature range 4), Table 10. Operating conditions (voltage range W, temperature range 3) , Table 14. DC characteristics, table 15. AC characteristics (5 MHz), Table 15. AC characteristics (10 MHz), Table 18. Ordering information scheme Added: • Table 11. AC measurement conditions, Figure 20. Hold timing, Table 12. Memory cell data retention, Table 13. Capacitance Removed: Table 13. DC characteristics (voltage range W, temperature range 3), Table 17. AC characteristics (20 MHz) Updated: • 27-Apr-2021 3 • • Features, Section 3.1 Active power and standby power modes, Section 4.7 Read identification page (RDID), Section 4.8 Write identification page (WRID), Section 4.9 Read lock status (RDLS), Section 4.10 Lock identification page (LID), Section 5.3 Cycling with error correction code (ECCx4), Section 6 Delivery state note 2 on Table 7. Absolute maximum ratings Table 8. Cycling performance by groups of 4 bytes, Table 12. Memory cell data retention, Table 14. DC characteristics, table 15. AC characteristics (5 MHz), Table 15. AC characteristics (10 MHz) Updated: 03-Aug-2023 4 • • • • Section 4.6 Write to memory array (WRITE) Section 4.8 Write identification page (WRID) Section 4.10 Lock identification page (LID) Section 9.2 TSSOP8 package information Removed: Table 15. AC characteristics (5 MHz) DS11938 - Rev 4 page 35/40 M95M04-A125 M95M04-A145 Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 2.1 Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Serial data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Serial clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 Chip select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.6 Write protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.7 VSS ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.8 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Operating features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Hold mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.4 Protocol control and data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.5 4 5 3.4.1 Protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.4.2 Status register and data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.1 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 Write status register (WRSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 Read from memory array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 Write to memory array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 Read identification page (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 Write identification page (WRID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.9 Read lock status (RDLS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.10 Lock identification page (LID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5.1 DS11938 - Rev 4 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.1 Operating supply voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.3 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 page 36/40 M95M04-A125 M95M04-A145 Contents 5.2 Implementing devices on SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 Cycling with error correction code (ECCx4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 10 9.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 DS11938 - Rev 4 page 37/40 M95M04-A125 M95M04-A145 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. DS11938 - Rev 4 Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . 8-pin package connections. . . . . . . . . . . . . . . . SPI modes supported . . . . . . . . . . . . . . . . . . . Hold mode activation . . . . . . . . . . . . . . . . . . . . Status register format . . . . . . . . . . . . . . . . . . . Write enable (WREN) sequence . . . . . . . . . . . . Write disable (WRDI) sequence . . . . . . . . . . . . Read status register (RDSR) sequence . . . . . . . Write status register (WRSR) sequence . . . . . . . Read from memory array (READ) sequence. . . . Byte write (WRITE) sequence. . . . . . . . . . . . . . Page write (WRITE) sequence . . . . . . . . . . . . . Read identification page sequence . . . . . . . . . . Write identification page sequence . . . . . . . . . . Read lock status sequence . . . . . . . . . . . . . . . Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . Bus master and memory devices on the SPI bus. AC measurement I/O waveform . . . . . . . . . . . . Serial input timing . . . . . . . . . . . . . . . . . . . . . . Hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . Serial output timing . . . . . . . . . . . . . . . . . . . . . SO8N – Outline . . . . . . . . . . . . . . . . . . . . . . . SO8N - Footprint example . . . . . . . . . . . . . . . . TSSOP8 – Outline . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 5 . 6 . 7 11 11 12 13 14 15 16 17 18 19 19 21 26 29 29 29 30 31 32 33 page 38/40 M95M04-A125 M95M04-A145 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . Protection modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device identification bytes. . . . . . . . . . . . . . . . . . . . . . . . . Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Significant bits within the address bytes . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . Cycling performance by groups of 4 bytes . . . . . . . . . . . . . . Operating conditions (voltage range W, temperature range 4) Operating conditions (voltage range W, temperature range 3) AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC characteristics (10 MHz) . . . . . . . . . . . . . . . . . . . . . . . SO8N – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . DS11938 - Rev 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 8 . 8 . 9 10 10 24 25 25 25 25 26 26 27 28 31 32 34 35 page 39/40 M95M04-A125 M95M04-A145 IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2023 STMicroelectronics – All rights reserved DS11938 - Rev 4 page 40/40