NAND512W3A0AN6

NAND128-A, NAND256-A NAND512-A, NAND01G-A 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories PRELIMINARY DATA FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH DENSITY NAND FLASH MEMORIES – Up to 1 Gbit memory array – Up to 32 Mbit spare area – Cost effective solutions for mass storage applications NAND INTERFACE – x8 or x16 bus width – Multiplexed Address/ Data – Pinout compatibility for all densities SUPPLY VOLTAGE – 1.8V device: VDD = 1.7 to 1.95V – 3.0V device: VDD = 2.7 to 3.6V PAGE SIZE – x8 device: (512 + 16 spare) Bytes – x16 device: (256 + 8 spare) Words BLOCK SIZE – x8 device: (16K + 512 spare) Bytes – x16 device: (8K + 256 spare) Words PAGE READ / PROGRAM – Random access: 12µs (max) – Sequential access: 50ns (min) – Page program time: 200µs (typ) COPY BACK PROGRAM MODE – Fast page copy without external buffering FAST BLOCK ERASE – Block erase time: 2ms (Typ) STATUS REGISTER ELECTRONIC SIGNATURE CHIP ENABLE ‘DON’T CARE’ OPTION – Simple interface with microcontroller AUTOMATIC PAGE 0 READ AT POWER-UP OPTION – Boot from NAND support – Automatic Memory Download SERIAL NUMBER OPTION July 2004 Figure 1. Packages TSOP48 12 x 20mm WSOP48 12 x 17 x 0.65mm FBGA VFBGA55 8 x 10 x 1mm TFBGA55 8 x 10 x 1.2mm VFBGA63 8.5 x 15 x 1mm TFBGA63 8.5 x 15 x 1.2mm ■ ■ ■ HARDWARE DATA PROTECTION – Program/Erase locked during Power transitions DATA INTEGRITY – 100,000 Program/Erase cycles – 10 years Data Retention DEVELOPMENT TOOLS – Error Correction Code software and hardware models – Bad Blocks Management and Wear Leveling algorithms – PC Demo board with simulation software – File System OS Native reference software – Hardware simulation models 1/56 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 1. Product List Reference Part Number NAND128R3A NAND128W3A NAND128-A NAND1282R4A NAND128W4A NAND256R3A NAND256W3A NAND256-A NAND256R4A NAND256W4A NAND512R3A NAND512W3A NAND512-A NAND512R4A NAND512W4A NAND01GR3A NAND01GW3A NAND01G-A NAND01GR4A NAND01GW4A 2/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Figure 2. Table 3. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TSOP48 and WSOP48 Connections, x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TSOP48 and WSOP48 Connections, x16 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 FBGA55 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . . 11 FBGA55 Connections, x16 devices (Top view through package) . . . . . . . . . . . . . . . . . . 12 FBGA63 Connections, x8 devices (Top view through package) . . . . . . . . . . . . . . . . . . . 13 FBGA63 Connections, x16 devices (Top view through package) . . . . . . . . . . . . . . . . . . 14 MEMORY ARRAY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bad Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10.Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Inputs/Outputs (I/O0-I/O7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Inputs/Outputs (I/O8-I/O15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Enable (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 6. Address Insertion, x8 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 7. Address Insertion, x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 8. Address Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DEVICE OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11.Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12.Pointer Operations for Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Sequential Row Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13.Read (A,B,C) Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 14.Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15.Sequential Row Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 16.Sequential Row Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 17.Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 10. Copy Back Program Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 18.Copy Back Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 19.Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Write Protection Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 P/E/R Controller Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Error Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SR5, SR4, SR3, SR2 and SR1 are Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 12. Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Automatic Page 0 Read at Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Automatic Page 0 Read Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Chip Enable Don’t Care Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Chip Enable Don’t Care Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 20.Chip Enable Don’t Care Enabled and Automatic Page 0 Read at Power-Up . . . . . . . . . 28 Figure 21.Automatic Page 0 Read at Power-Up (Chip Enable Don’t Care Disabled) . . . . . . . . . . . 29 SOFTWARE ALGORITHMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 13. Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 22.Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 23.Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Wear-leveling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Error Correction Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 24.Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Hardware Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 14. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 32 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 15. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 16. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 17. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 18. DC Characteristics, 1.8V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 19. DC Characteristics, 3V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 20. AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 21. AC Characteristics for Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 25.Command Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 26.Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 27.Data Input Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 28.Sequential Data Output after Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 29.Read Status Register AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 30.Read Electronic Signature AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 31.Page Read A/ Read B Operation AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 32.Read C Operation, One Page AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 33.Page Program AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 34.Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 35.Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Ready/Busy Signal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 36.Ready/Busy AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 37.Ready/Busy Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 38.Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . . 45 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 39.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . 46 Table 22. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 46 Figure 40.WSOP48 – 48 lead Plastic Very Very Thin Small Outline, 12 x 17mm, Package Outline47 Table 23. WSOP48 lead Plastic Very Very Thin Small Outline, 12 x 17mm, Mechanical Data. . . . 47 Figure 41.VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . 48 Table 24. VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data . 48 Figure 42.TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline . . . . . . . . 49 5/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data 49 Figure 43.VFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . 50 Table 26. VFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data50 Figure 44.TFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . 51 Table 27. TFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data51 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 28. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 APPENDIX A.HARDWARE INTERFACE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 45.Connection to Microcontroller, Without Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 46.Connection to Microcontroller, With Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 47.Building Storage Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A SUMMARY DESCRIPTION The NAND Flash 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that uses NAND cell technology. The devices range from 128Mbits to 1Gbit and operate with either a 1.8V or 3V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width. The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or x16 Input/Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code (ECC). A Write Protect pin is available to give a hardware protection against program and erase operations. The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/ Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed in another page without having to resend the data to be programmed. The devices are available in the following packages: ■ TSOP48 12 x 20mm for all products WSOP48 12 x 17 x 0.65mm for 128Mb, 256Mb and 512Mb products ■ VFBGA55 (8 x 10 x 1mm, 6 x 8 ball array, 0.8mm pitch) for 128Mb and 256Mb products ■ TFBGA55 (8 x 10 x 1.2mm, 6 x 8 ball array, 0.8mm pitch) for 512Mb Dual Die product ■ VFBGA63 (8.5 x 15 x 1mm, 6 x 8 ball array, 0.8mm pitch) for the 512Mb product ■ TFBGA63 (8.5 x 15 x 1.2mm, 6 x 8 ball array, 0.8mm pitch) for the 1Gb Dual Die product Three options are available for the NAND Flash family: ■ Automatic Page 0 Read after Power-up, which allows the microcontroller to directly download the boot code from page 0. ■ Chip Enable Don’t Care, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation. ■ A Serial Number, which allows each device to be uniquely identified. The Serial Number options is subject to an NDA (Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your nearest ST Sales office. For information on how to order these options refer to Table 28., Ordering Information Scheme. Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to ’1’. See Table 2., Product Description, for all the devices available in the family. ■ 7/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 2. Product Description Timings Reference Part Number Density NAND128R3A NAND128-A NAND128W3A NAND128R4A NAND256R3A NAND256W3A NAND256R4A NAND512R3A NAND512W3A NAND512R4A NAND512R3A NAND512W3A NAND512R4A NAND01GR3A NAND01GW3A NAND01GR4A 512+16 Bytes 16K+512 Bytes x16 256+8 Words 8K+256 Words x8 512+16 Bytes 16K+512 Bytes x16 256+8 Words 8K+256 Words x8 512+16 Bytes 16K+512 Bytes x16 256+8 Words 8K+256 Words x8 512+16 Bytes 16K+512 Bytes 512Mbit NAND512W4A NAND01G-A x8 512Mbit NAND512W4A NAND512-A Block Size 256Mbit NAND256W4A NAND512-A Page Size 128Mbit NAND128W4A NAND256-A Bus Width x16 256+8 Words 8K+256 Words x8 512+16 Bytes 16K+512 Bytes x16 256+8 Words 8K+256 Words 1Gbit NAND01GW4A Memory Array 32 Pages x 1024 Blocks 32 Pages x 2048 Blocks 32 Pages x 4096 Blocks 32 Pages x 4096 Blocks 32 Pages x 8192 Blocks Figure 2. Logic Diagram Random Access Max Sequential Access Min Page Program Typical 1.7 to 1.95V 10µs 60ns 200µs 2.7 to 3.6V 10µs 50ns 200µs 1.7 to 1.95V 10µs 60ns 200µs 2.7 to 3.6V 10µs 50ns 200µs 1.7 to 1.95V 10µs 60ns 200µs 2.7 to 3.6V 10µs 50ns 200µs 1.7to 1.95V 10µs 60ns 200µs 2.7 to 3.6V 10µs 50ns 200µs 1.7to 1.95V 10µs 60ns 200µs 2.7 to 3.6V 10µs 50ns 200µs 1.7 to 1.95V 10µs 60ns 200µs 2.7 to 3.6V 10µs 50ns 200µs 1.7to 1.95V 15µs 60ns 200µs 2.7 to 3.6V 12µs 50ns 200µs 1.7 to 1.95V 15µs 60ns 200µs 2.7 to 3.6V 12µs 50ns 200µs 1.7 to 1.95V 15µs 60ns 200µs 2.7 to 3.6V 12µs 50ns 200µs 1.7 to 1.95V 15µs 60ns 200µs 2.7 to 3.6V 12µs 50ns 200µs Block Erase Typical Package 2ms TSOP48 WSOP48 VFBGA55 2ms TSOP48 WSOP48 VFBGA55 2ms TFBGA55 2ms TSOP48 WSOP48 VFBGA63 2ms TSOP48 TFBGA63 Table 3. Signal Names VDD I/O8-I/O15, x16 E I/O0-I/O7, x8/x16 R I/O8-15 Data Input/Outputs for x16 devices I/O0-7 Data Input/Outputs, Address Inputs, or Command Inputs for x8 and x16 devices AL Address Latch Enable CL Command Latch Enable E Chip Enable R Read Enable RB Ready/Busy (open-drain output) W Write Enable WP Write Protect CL VDD Supply Voltage WP VSS Ground NC Not Connected Internally DU Do Not Use W NAND Flash RB AL VSS AI07557C 8/56 Operating Voltage NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 3. Logic Block Diagram AL CL W E WP R Command Interface Logic P/E/R Controller, High Voltage Generator X Decoder Address Register/Counter NAND Flash Memory Array Page Buffer Cache Register Command Register Y Decoder I/O Buffers & Latches RB I/O0-I/O7, x8/x16 I/O8-I/O15, x16 AI07561b 9/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 4. TSOP48 and WSOP48 Connections, x8 devices NC NC NC NC NC NC RB R E 1 NC NC VDD VSS NC NC CL AL W WP NC NC NC NC NC 12 13 24 48 NAND Flash (x8) 37 36 25 NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC NC VDD VSS NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC AI07585B 10/56 Figure 5. TSOP48 and WSOP48 Connections, x16 devices NC NC NC NC NC NC RB R E 1 NC NC VDD VSS NC NC CL AL W WP NC NC NC NC NC 12 13 24 48 NAND Flash (x16) 37 36 25 VSS I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 NC NC VDD NC NC NC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 VSS AI07559B NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 6. FBGA55 Connections, x8 devices (Top view through package) 1 A 2 3 4 5 6 7 8 DU DU B DU C WP AL VSS E W RB D NC R CL NC NC NC E NC NC NC NC NC NC F NC NC NC NC NC NC G NC NC NC NC NC NC H NC I/O0 NC NC NC VDD J NC I/O1 NC VDD I/O5 I/O7 K VSS I/O2 I/O3 I/O4 I/O6 VSS L DU DU M DU DU AI09366b 11/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 7. FBGA55 Connections, x16 devices (Top view through package) 1 A 2 3 4 5 6 7 8 DU DU DU B C WP AL VSS E W RB D NC R CL NC NC NC E NC NC NC NC NC NC F NC NC NC NC NC NC G NC NC NC I/O5 I/O7 NC H I/O8 I/O1 I/O10 I/O12 I/O14 VDD J I/O0 I/O9 I/O3 VDD I/O6 I/O15 K VSS I/O2 I/O11 I/O4 I/O13 VSS L DU DU M DU DU AI09365b 12/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 8. FBGA63 Connections, x8 devices (Top view through package) 1 2 A DU DU B DU 3 4 5 6 7 8 C WP AL VSS E W RB D NC R CL NC NC NC E NC NC NC NC NC NC F NC NC NC NC NC NC G NC NC NC NC NC NC H NC I/O0 NC NC NC VDD J NC I/O1 NC VDD I/O5 I/O7 K VSS I/O2 I/O3 I/O4 I/O6 VSS 9 10 DU DU DU DU L DU DU DU DU M DU DU DU DU AI07586B 13/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 9. FBGA63 Connections, x16 devices (Top view through package) 1 2 A DU DU B DU 3 4 5 6 7 8 C WP AL VSS E W RB D NC R CL NC NC NC E NC NC NC NC NC NC F NC NC NC NC NC NC G NC NC NC I/O5 I/O7 NC H I/O8 I/O1 I/O10 I/O12 I/O14 VDD J I/O0 I/O9 I/O3 VDD I/O6 I/O15 K VSS I/O2 I/O11 I/O4 I/O13 VSS 9 10 DU DU DU DU L DU DU DU DU M DU DU DU DU AI07560B 14/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A MEMORY ARRAY ORGANIZATION The memory array is made up of NAND structures where 16 cells are connected in series. The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store Error correction Codes, software flags or Bad Block identification. In x8 devices the pages are split into a main area with two half pages of 256 Bytes each and a spare area of 16 Bytes. In the x16 devices the pages are split into a 256 Word main area and an 8 Word spare area. Refer to Figure 10., Memory Array Organization. Bad Blocks The NAND Flash 528 Byte/ 264 Word Page devices may contain Bad Blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional Bad Blocks may develop during the lifetime of the device. The Bad Block Information is written prior to shipping (refer to Bad Block Management section for more details). Table 4. shows the minimum number of valid blocks in each device. The values shown include both the Bad Blocks that are present when the device is shipped and the Bad Blocks that could develop later on. These blocks need to be managed using Bad Blocks Management, Block Replacement or Error Correction Codes (refer to SOFTWARE ALGORITHMS section). Table 4. Valid Blocks Density of Device Min Max 1Gbit 8032 8192 512Mbits 4016 4096 256Mbits 2008 2048 128Mbits 1004 1024 Figure 10. Memory Array Organization x8 DEVICES x16 DEVICES Block = 32 Pages Page = 528 Bytes (512+16) are Sp Block = 32 Pages Page = 264 Words (256+8) a Are are Sp Main Area 1st half Page 2nd half Page (256 bytes) (256 bytes) Block Page a Are Block Page 16 bits 8 bits 512 Bytes 256 Words 16 Bytes Page Buffer, 264 Words Page Buffer, 512 Bytes 512 Bytes 16 Bytes 8 Words 8 bits 256 Words 8 Words 16 bits AI07587 15/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram, and Table 3., Signal Names, for a brief overview of the signals connected to this device. Inputs/Outputs (I/O0-I/O7). Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read operation or input a command or data during a Write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/ O7 are left floating when the device is deselected or the outputs are disabled. Inputs/Outputs (I/O8-I/O15). Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data during a Read operation or input data during a Write operation. Command and Address Inputs only require I/O0 to I/O7. The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when the device is deselected or the outputs are disabled. Address Latch Enable (AL). The Address Latch Enable activates the latching of the Address inputs in the Command Interface. When AL is high, the inputs are latched on the rising edge of Write Enable. Command Latch Enable (CL). The Command Latch Enable activates the latching of the Command inputs in the Command Interface. When CL is high, the inputs are latched on the rising edge of Write Enable. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is low, VIL, the device is selected. If Chip Enable goes high, vIH, while the device is busy, the device remains selected and does not go into standby mode. When the device is executing a Sequential Row Read operation, Chip Enable must be held low (from the second page read onwards) during the time that the device is busy (tBLBH1). If Chip Enable goes high during tBLBH1 the operation is aborted. Read Enable (R). The Read Enable, R, controls the sequential data output during Read operations. Data is valid tRLQV after the falling edge of R. The falling edge of R also increments the internal column address counter by one. 16/56 Write Enable (W). The Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a recovery time of 1µs (min) is required before the Command Interface is ready to accept a command. It is recommended to keep Write Enable high during the recovery time. Write Protect (WP). The Write Protect pin is an input that gives a hardware protection against unwanted program or erase operations. When Write Protect is Low, VIL, the device does not accept any program or erase operations. It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down. Ready/Busy (RB). The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R Controller is currently active. When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the operation completes Ready/Busy goes High, VOH. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Refer to the Ready/Busy Signal Electrical Characteristics section for details on how to calculate the value of the pull-up resistor. VDD Supply Voltage. VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever VDD is below 2.5V (for 3V devices) or 1.5V (for 1.8V devices) to protect the device from any involuntary program/erase during power-transitions. Each device in a system should have VDD decoupled with a 0.1µF capacitor. The PCB track widths should be sufficient to carry the required program and erase currents VSS Ground. Ground, VSS, is the reference for the power supply. It must be connected to the system ground. NAND128-A, NAND256-A, NAND512-A, NAND01G-A BUS OPERATIONS There are six standard bus operations that control the memory. Each of these is described in this section, see Table 5., Bus Operations, for a summary. Command Input Command Input bus operations are used to give commands to the memory. Command are accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input commands. See Figure 25. and Table 20. for details of the timings requirements. Address Input Address Input bus operations are used to input the memory address. Three bus cycles are required to input the addresses for the 128Mb and 256Mb devices and four bus cycles are required to input the addresses for the 512Mb and 1Gb devices (refer to Tables 6 and 7, Address Insertion). The addresses are accepted when Chip Enable is Low, Address Latch Enable is High, Command Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses. See Figure 26. and Table 20. for details of the timings requirements. Data Input Data Input bus operations are used to input the data to be programmed. Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is input sequentially using the Write Enable signal. See Figure 27. and Table 20. and Table 21. for details of the timings requirements. Data Output Data Output bus operations are used to read: the data in the memory array, the Status Register, the Electronic Signature and the Serial Number. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal. See Figure 28. and Table 21. for details of the timings requirements. Write Protect Write Protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up. Standby When Chip Enable is High the memory enters Standby mode, the device is deselected, outputs are disabled and power consumption is reduced. Table 5. Bus Operations Bus Operation E AL CL R W WP I/O0 - I/O7 I/O8 - I/O15(1) Command Input VIL VIL VIH VIH Rising X(2) Command X Address Input VIL VIH VIL VIH Rising X Address X Data Input VIL VIL VIL VIH Rising X Data Input Data Input Data Output VIL VIL VIL Falling VIH X Data Output Data Output Write Protect X X X X X VIL X X Standby VIH X X X X X X X Note: 1. Only for x16 devices. 2. WP must be VIH when issuing a program or erase command. 17/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 6. Address Insertion, x8 Devices Bus Cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 1st A7 A6 A5 A4 A3 A2 A1 A0 2nd A16 A15 A14 A13 A12 A11 A10 A9 3rd A24 A23 A22 A21 A20 A19 A18 A17 4th(4) VIL VIL VIL VIL VIL VIL A26 A25 Note: 1. A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section. 2. Any additional address input cycles will be ignored. 3. The 4th cycle is only required for 512Mb and 1Gb devices. Table 7. Address Insertion, x16 Devices Bus Cycle I/O8I/O15 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 1st X A7 A6 A5 A4 A3 A2 A1 A0 2nd X A16 A15 A14 A13 A12 A11 A10 A9 3rd X A24 A23 A22 A21 A20 A19 A18 A17 4th(4) X VIL VIL VIL VIL VIL VIL A26 A25 Note: 1. 2. 3. 4. A8 is Don’t Care in x16 devices. Any additional address input cycles will be ignored. The 01h Command is not used in x16 devices. The 4th cycle is only required for 512Mb and 1Gb devices. Table 8. Address Definitions 18/56 Address Definition A0 - A7 Column Address A9 - A26 Page Address A9 - A13 Address in Block A14 - A26 Block Address A8 A8 is set Low or High by the 00h or 01h Command, and is Don’t Care in x16 devices NAND128-A, NAND256-A, NAND512-A, NAND01G-A COMMAND SET All bus write operations to the device are interpreted by the Command Interface. The Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. Device operations are selected by writing specific commands to the Com- mand Register. The two-step command sequences for program and erase operations are imposed to maximize data security. The Commands are summarized in Table 9., Commands. Table 9. Commands Bus Write Operations(1) Command 1st CYCLE 2nd CYCLE 3rd CYCLE Read A 00h - - Read B 01h(2) - - Read C 50h - - Read Electronic Signature 90h - - Read Status Register 70h - - Page Program 80h 10h - Copy Back Program 00h 8Ah 10h Block Erase 60h D0h - Reset FFh - - Command accepted during busy Yes Yes Note: 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown. 2. Any undefined command sequence will be ignored by the device. 19/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A DEVICE OPERATIONS Pointer Operations As the NAND Flash memories contain two different areas for x16 devices and three different areas for x8 devices (see Figure 11.) the read command codes (00h, 01h, 50h) are used to act as pointers to the different areas of the memory array (they select the most significant column address). The Read A and Read B commands act as pointers to the main memory area. Their use depends on the bus width of the device. ■ In x16 devices the Read A command (00h) sets the pointer to Area A (the whole of the main area) that is Words 0 to 255. ■ In x8 devices the Read A command (00h) sets the pointer to Area A (the first half of the main area) that is Bytes 0 to 255, and the Read B command (01h) sets the pointer to Area B (the second half of the main area) that is Bytes 256 to 511. In both the x8 and x16 devices the Read C command (50h), acts as a pointer to Area C (the spare memory area) that is Bytes 512 to 527 or Words 256 to 263. Once the Read A and Read C commands have been issued the pointer remains in the respective areas until another pointer code is issued. However, the Read B command is effective for only one operation, once an operation has been executed in Area B the pointer returns automatically to Area A. The pointer operations can also be used before a program operation, that is the appropriate code (00h, 01h or 50h) can be issued before the program command 80h is issued (see Figure 12.). Figure 11. Pointer Operations x8 Devices Area A (00h) Bytes 0- 255 Area B (01h) Area C (50h) 512 Bytes 256-511 Bytes -527 B A x16 Devices C Area A (00h) Area C (50h) Words 0- 255 Words 256 -263 Page Buffer C A Pointer (00h,01h,50h) Page Buffer Pointer (00h,50h) AI07592 Figure 12. Pointer Operations for Programming AREA A I/O 00h 80h Address Inputs Data Input 10h 00h 80h Address Inputs Data Input 10h Areas A, B, C can be programmed depending on how much data is input. Subsequent 00h commands can be omitted. AREA B I/O 01h 80h Address Inputs Data Input 10h 01h 80h Address Inputs Data Input 10h Areas B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program. AREA C I/O 50h 80h Address Inputs Data Input 10h 50h 80h Address Inputs Data Input 10h Only Areas C can be programmed. Subsequent 50h commands can be omitted. ai07591 20/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Read Memory Array Each operation to read the memory area starts with a pointer operation as shown in the Pointer Operations section. Once the area (main or spare) has been selected using the Read A, Read B or Read C commands four bus cycles (for 512Mb and 1Gb devices) or three bus cycles (for 128Mb and 256Mb devices) are required to input the address (refer to Table 6.) of the data to be read. The device defaults to Read A mode after powerup or a Reset operation. Devices, where page0 is read automatically at power-up, are available on request. When reading the spare area addresses: ■ A0 to A3 (x8 devices) ■ A0 to A2 (x16 devices) are used to set the start address of the spare area while addresses: ■ A4 to A7 (x8 devices) ■ A3 to A7 (x16 devices) are ignored. Once the Read A or Read C commands have been issued they do not need to be reissued for subsequent read operations as the pointer remains in the respective area. However, the Read B command is effective for only one operation, once an operation has been executed in Area B the pointer returns automatically to Area A and so another Read B command is required to start another read operation in Area B. Once a read command is issued three types of operations are available: Random Read, Page Read and Sequential Row Read. Random Read. Each time the command is issued the first read is Random Read. Page Read. After the Random Read access the page data is transferred to the Page Buffer in a time of tWHBH (refer to Table 21. for value). Once the transfer is complete the Ready/Busy signal goes High. The data can then be read out sequentially (from selected column address to last column address) by pulsing the Read Enable signal. Sequential Row Read. After the data in last column of the page is output, if the Read Enable signal is pulsed and Chip Enable remains Low then the next page is automatically loaded into the Page Buffer and the read operation continues. A Sequential Row Read operation can only be used to read within a block. If the block changes a new read command must be issued. Refer to Figure 15. and Figure 16. for details of Sequential Row Read operations. To terminate a Sequential Row Read operation set the Chip Enable signal to High for more than tEHEL. Sequential Row Read is not available when the Chip Enable Don't Care option is enabled. Figure 13. Read (A,B,C) Operations CL E W AL R tBLBH1 (read) RB I/O 00h/ 01h/ 50h Command Code Data Output (sequentially) Address Input Busy ai07595 21/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 14. Read Block Diagrams Read A Command, X8 Devices Read A Command, X16 Devices Area B Area A Area C (1st half Page) (2nd half Page) (Spare) Area C (Spare) Area A (main area) A9-A26(1) A9-A26(1) A0-A7 A0-A7 Read C Command, X8/x16 Devices Read B Command, X8 Devices Area B Area A Area C (1st half Page) (2nd half Page) (Spare) Area A A9-A26(1) Area A/ B Area C (Spare) A9-A26(1) A0-A3 (x8) A0-A2 (x16) A0-A7 A4-A7 (x8), A3-A7 (x16) are don't care AI07596 Note: 1. Highest address depends on device density. Figure 15. Sequential Row Read Operations tBLBH1 tBLBH1 tBLBH1 (Read Busy time) RB Busy Busy I/O 00h/ 01h/ 50h 1st Page Output Address Inputs Busy 2nd Page Output Nth Page Output Command Code ai07597 Figure 16. Sequential Row Read Block Diagrams Read A Command, x16 Devices Read A Command, x8 Devices Area B Area A Area C (1st half Page) (2nd half Page) (Spare) Area A (main area) 1st page 2nd page Nth page Block 1st page 2nd page Nth page Block Read B Command, x8 Devices Read C Command, x8/x16 Devices Area B Area A Area C (1st half Page) (2nd half Page) (Spare) Block Area C (Spare) Area A 1st page 2nd page Nth page Block Area A/ B Area C (Spare) 1st page 2nd page Nth page AI07598 22/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Page Program The Page Program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be programmed. The maximum number of consecutive partial page program operations allowed in the same page is three. After exceeding this a Block Erase command must be issued before any further program operations can take place in that page. Before starting a Page Program operation a Pointer operation can be performed to point to the area to be programmed. Refer to the Pointer Operations section and Figure 12. for details. Each Page Program operation consists of five steps (see Figure 17.): 1. one bus cycle is required to setup the Page Program command 2. four bus cycles are then required to input the program address (refer to Table 6.) 3. the data is then input (up to 528 Bytes/ 264 Words) and loaded into the Page Buffer 4. one bus cycle is required to issue the confirm command to start the P/E/R Controller. 5. The P/E/R Controller then programs the data into the array. Once the program operation has started the Status Register can be read using the Read Status Register command. During program operations the Status Register will only flag errors for bits set to '1' that have not been successfully programmed to '0'. During the program operation, only the Read Status Register and Reset commands will be accepted, all other commands will be ignored. Once the program operation has completed the P/ E/R Controller bit SR6 is set to ‘1’ and the Ready/ Busy signal goes High. The device remains in Read Status Register mode until another valid command is written to the Command Interface. Figure 17. Page Program Operation tBLBH2 (Program Busy time) RB Busy I/O 80h Page Program Setup Code Address Inputs Data Input 10h Confirm Code 70h SR0 Read Status Register ai07566 Note: Before starting a Page Program operation a Pointer operation can be performed. Refer to Pointer Operations section for details. 23/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Copy Back Program The Copy Back Program operation is used to copy the data stored in one page and reprogram it in another page. The Copy Back Program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block. If the Copy Back Program operation fails an error is signalled in the Status Register. However as the standard external ECC cannot be used with the Copy Back operation bit error due to charge loss cannot be detected. For this reason it is recommended to limit the number of Copy Back operations on the same data and or to improve the performance of the ECC. The Copy Back Program operation requires three steps: 1. The source page must be read using the Read A command (one bus write cycle to setup the command and then 4 bus write cycles to input the source page address). This operation copies all 264 Words/ 528 Bytes from the page into the Page Buffer. 2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is given with the 4 bus cycles to input the target page address. Refer to Table 10. for the addresses that must be the same for the Source and Target pages. 3. Then the confirm command is issued to start the P/E/R Controller. After a Copy Back Program operation, a partialpage program is not allowed in the target page until the block has been erased. See Figure 18. for an example of the Copy Back operation. Table 10. Copy Back Program Addresses Density Same Address for Source and Target Pages 128Mbit A23 256Mbit A24 512Mbit A25 1Gbit A25,A26 Figure 18. Copy Back Operation tBLBH1 tBLBH2 (Read Busy time) (Program Busy time) RB Busy I/O 00h Read Code Source Address Inputs 8Ah Copy Back Code Target Address Inputs 10h 70h SR0 Read Status Register ai07590b 24/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Block Erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to ‘1’. All previous data in the block is lost. An erase operation consists of three steps (refer to Figure 19.): 1. One bus cycle is required to setup the Block Erase command. 2. Only three bus cycles for 512Mb and 1Gb devices, or two for 128Mb and 256Mb devices are required to input the block address. The first cycle (A0 to A7) is not required as only addresses A14 to A26 (highest address depends on device density) are valid, A9 to A13 are ignored. In the last address cycle I/O0 to I/O7 must be set to VIL. 3. One bus cycle is required to issue the confirm command to start the P/E/R Controller. Once the erase operation has completed the Status Register can be checked for errors. Figure 19. Block Erase Operation tBLBH3 (Erase Busy time) RB Busy I/O 60h Block Erase Setup Code Block Address Inputs D0h Confirm Code 70h SR0 Read Status Register ai07593 Reset The Reset command is used to reset the Command Interface and Status Register. If the Reset command is issued during any operation, the operation will be aborted. If it was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. If the device has already been reset then the new Reset command will not be accepted. The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value of tBLBH4 depends on the operation that the device was performing when the command was issued, refer to Table 21. for the values. 25/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Read Status Register The device contains a Status Register which provides information on the current or previous Program or Erase operation. The various bits in the Status Register convey information and errors on the operation. The Status Register is read by issuing the Read Status Register command. The Status Register information is present on the output data bus (I/O0I/O7) on the falling edge of Chip Enable or Read Enable, whichever occurs last. When several memories are connected in a system, the use of Chip Enable and Read Enable signals allows the system to poll each device separately, even when the Ready/Busy pins are common-wired. It is not necessary to toggle the Chip Enable or Read Enable signals to update the contents of the Status Register. After the Read Status Register command has been issued, the device remains in Read Status Register mode until another command is issued. Therefore if a Read Status Register command is issued during a Random Read cycle a new read command must be issued to continue with a Page Read or Sequential Row Read operation. 26/56 The Status Register bits are summarized in Table 11., Status Register Bits. Refer to Table 11. in conjunction with the following text descriptions. Write Protection Bit (SR7). The Write Protection bit can be used to identify if the device is protected or not. If the Write Protection bit is set to ‘1’ the device is not protected and program or erase operations are allowed. If the Write Protection bit is set to ‘0’ the device is protected and program or erase operations are not allowed. P/E/R Controller Bit (SR6). The Program/Erase/ Read Controller bit indicates whether the P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R Controller is active (device is busy); when the bit is set to ‘1’, the P/E/R Controller is inactive (device is ready). Error Bit (SR0). The Error bit is used to identify if any errors have been detected by the P/E/R Controller. The Error Bit is set to ’1’ when a program or erase operation has failed to write the correct data to the memory. If the Error Bit is set to ‘0’ the operation has completed successfully. SR5, SR4, SR3, SR2 and SR1 are Reserved. NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 11. Status Register Bits Bit Name SR7 Write Protection Logic Level Definition '1' Not Protected '0' Protected Program/ Erase/ Read Controller '1' P/E/R C inactive, device ready '0' P/E/R C active, device busy SR5, SR4, SR3, SR2, SR1 Reserved Don’t Care SR0 Generic Error SR6 Read Electronic Signature The device contains a Manufacturer Code and Device Code. To read these codes two steps are required: 1. first use one Bus Write cycle to issue the Read Electronic Signature command (90h) 2. then perform two Bus Read operations – the first will read the Manufacturer Code and the second, the Device Code. Further Bus Read operations will be ignored. Refer to Table 12., Electronic Signature, for information on the addresses. ‘1’ Error – operation failed ‘0’ No Error – operation successful Table 12. Electronic Signature Part Number Manufacturer Code NAND128R3A Device code 33h 20h NAND128W3A 73h NAND128R4A 0043h 0020h NAND128W4A 0053h 35h NAND256R3A 20h NAND256W3A 75h NAND256R4A 0045h 0020h NAND256W4A 0055h NAND512R3A 36h 20h NAND512W3A 76h NAND512R4A 0046h 0020h NAND512W4A 0056h NAND01GR3A 39h 20h NAND01GW3A 79h NAND01GR4A 0049h 0020h NAND01GW4A 0059h 27/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A complete the Ready/Busy signal goes High. The data can then be read out sequentially on the I/O bus by pulsing the Read Enable, R, signal. Figure 20. and Figure 21. show the power-up waveforms for devices featuring the Automatic Page 0 Read option. Chip Enable Don’t Care Enabled. If the device is delivered with Chip Enable Don’t Care and Automatic Page 0 Read at Power-up, only the first page (Page 0) will be automatically read after the power-up sequence. Refer to Figure 20.. Chip Enable Don’t Care Disabled. If the device is delivered with the Automatic Page 0 Read option only (Chip Enable Don’t Care disabled), the device will automatically enter Sequential Row Read mode (Automatic Memory Download) after the power-up sequence, and start reading Page 0, Page 1, etc., until the last memory location is reached, each new page being accessed after a time tBLBH1. The Sequential Row Read operation can be inhibited or interrupted by de-asserting E (set to VIH) or by issuing a command. Automatic Page 0 Read at Power-Up Automatic Page 0 Read at Power-Up is an option available on all devices belonging to the NAND Flash 528 Byte/264 Word Page family. It allows the microcontroller to directly download boot code from page 0, without requiring any command or address input sequence. The Automatic Page 0 Read option is particularly suited for applications that boot from the NAND. Devices delivered with Automatic Page 0 Read at Power-Up can have the Chip Enable Don’t Care option either enabled or disabled. For details on how to order the different options, refer to Table 28., Ordering Information Scheme. Automatic Page 0 Read Description. At powerup, once the supply voltage has reached the threshold level, VDDth, all digital outputs revert to their reset state and the internal NAND device functions (reading, writing, erasing) are enabled. The device then automatically switches to read mode where, as in any read operation, the device is busy for a time tBLBH1 during which data is transferred to the Page Buffer. Once the data transfer is Figure 20. Chip Enable Don’t Care Enabled and Automatic Page 0 Read at Power-Up VDDth (1) VDD W E AL CL tBLBH1 RB R Data N I/O Busy Note: 1. 28/56 Data N+1 Data N+2 Last Data Data Output from Address N to Last Byte or Word in Page VDDth is equal to 2.5V for 3V Power Supply devices and to 1.5V for 1.8V Power Supply devices. ai08443b NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 21. Automatic Page 0 Read at Power-Up (Chip Enable Don’t Care Disabled) tBLBH1 tBLBH1 tBLBH1 tBLBH1 (Read Busy time) RB I/O Busy Busy Busy Page 0 Data Out Page 1 Data Out Busy Page 2 Data Out Page Nth Data Out ai08444 SOFTWARE ALGORITHMS This section gives information on the software algorithms that ST recommends to implement to manage the Bad Blocks and extend the lifetime of the NAND device. NAND Flash memories are programmed and erased by Fowler-Nordheim tunneling using a high voltage. Exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged. For this reason, the number of program and erase cycles is limited (see Table 14. for value) and it is recommended to implement Garbage Collection, a Wear-Leveling Algorithm and an Error Correction Code, to extend the number of program and erase cycles and increase the data retention. To help integrate a NAND memory into an application ST Microelectronics can provide: ■ A Demo board with NAND simulation software for PCs ■ File System OS Native reference software, which supports the basic commands of file management. Contact the nearest ST Microelectronics sales office for more details. Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad Block Information is written prior to shipping. Any block where the 6th Byte/ 1st Word in the spare area of the 1st or 2nd page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure 22. Block Replacement Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register. As the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. The Copy Back Program command can be used to copy the data to a valid block. See the “Copy Back Program” section for more details. Refer to Table 13. for the recommended procedure to follow if an error occurs during an operation. Table 13. Block Failure Operation Recommended Procedure Erase Block Replacement Program Block Replacement or ECC Read ECC 29/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 22. Bad Block Management Flowchart START Block Address = Block 0 Data = FFh? Increment Block Address NO Update Bad Block table YES NO Last block? YES END AI07588C Figure 23. Garbage Collection New Area (After GC) Old Area Valid Page Invalid Page Free Page (Erased) AI07599B Garbage Collection When a data page needs to be modified, it is faster to write to the first available page, and the previous page is marked as invalid. After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations it is recommended to implement a Garbage Collection algorithm. In a Garbage Collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure 23.). 30/56 Wear-leveling Algorithm For write-intensive applications, it is recommended to implement a Wear-leveling Algorithm to monitor and spread the number of write cycles per block. In memories that do not use a Wear-Leveling Algorithm not all blocks get used at the same rate. Blocks with long-lived data do not endure as many write cycles as the blocks with frequently-changed data. The Wear-leveling Algorithm ensures that equal use is made of all the available write cycles for each block. There are two wear-leveling levels: NAND128-A, NAND256-A, NAND512-A, NAND01G-A First Level Wear-leveling, new data is programmed to the free blocks that have had the fewest write cycles ■ Second Level Wear-leveling, long-lived data is copied to another block so that the original block can be used for more frequentlychanged data. The Second Level Wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold. Error Correction Code An Error Correction Code (ECC) can be implemented in the Nand Flash memories to identify and correct errors in the data. For every 2048 bits in the device it is recommended to implement 22 bits of ECC (16 bits for line parity plus 6 bits for column parity). An ECC model is available in VHDL or Verilog. Contact the nearest ST Microelectronics sales office for more details. ■ Hardware Simulation Models Behavioral simulation models. Denali Software Corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND Flash devices, and so allow software to be developed before hardware. IBIS simulations models. IBIS (I/O Buffer Information Specification) models describe the behavior of the I/O buffers and electrical characteristics of Flash devices. These models provide information such as AC characteristics, rise/fall times and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. IBIS models are used to simulate PCB connections and can be used to resolve compatibility issues when upgrading devices. They can be imported into SPICETOOLS. Figure 24. Error Detection New ECC generated during read XOR previous ECC with new ECC All results = zero? YES NO >1 bit = zero? NO YES 22 bit data = 0 11 bit data = 1 1 bit data = 1 No Error Correctable Error ECC Error ai08332 31/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The Program and Erase times and the number of Program/ Erase cycles per block are shown in Table 14. Table 14. Program, Erase Times and Program Erase Endurance Cycles NAND Flash Parameters Unit Min Page Program Time Block Erase Time Program/Erase Cycles (per block) Typ Max 200 500 µs 2 3 ms 100,000 cycles 10 years Data Retention MAXIMUM RATING Stressing the device above the ratings listed in Table 15., Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 15. Absolute Maximum Ratings Value Symbol Parameter Unit Min Max TBIAS Temperature Under Bias – 50 125 °C TSTG Storage Temperature – 65 150 °C VIO (1) 1.8V devices – 0.6 2.7 V Input or Output Voltage 3 V devices – 0.6 4.6 V 1.8V devices – 0.6 2.7 V 3 V devices – 0.6 4.6 V VDD Supply Voltage Note: 1. Minimum Voltage may undershoot to –2V for less than 20ns during transitions on input and I/O pins. Maximum voltage may overshoot to VDD + 2V for less than 20ns during transitions on I/O pins. 32/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measure- ment Conditions summarized in Table 16., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 16. Operating and AC Measurement Conditions NAND Flash Parameter Units Supply Voltage (VDD) Ambient Temperature (TA) Load Capacitance (CL) (1 TTL GATE and CL) Min Max 1.8V devices 1.7 1.95 V 3V devices 2.7 3.6 V Grade 1 0 70 °C Grade 6 –40 85 °C 1.8V devices 30 pF 3V devices (2.7 - 3.6V) 50 pF 3V devices (3.0 - 3.6V) 100 pF 1.8V devices 0 VDD V 3V devices 0.4 2.4 V Input Pulses Voltages 1.8V devices 0.9 V 3V devices 1.5 V 5 ns Input and Output Timing Ref. Voltages Input Rise and Fall Times Table 17. Capacitance Symbol Parameter Test Condition Typ Max Unit CIN Input Capacitance VIN = 0V 10 pF CI/O Input/Output Capacitance VIL = 0V 10 pF Note: TA = 25°C, f = 1 MHz. CIN and CI/O are not 100% tested. 33/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 18. DC Characteristics, 1.8V Devices Symbol Parameter IDD1 IDD2 IDD3 Operating Current Test Conditions Min Typ Max Unit Sequential Read tRLRL minimum E=VIL, IOUT = 0 mA - 8 15 mA Program - - 8 15 mA Erase - - 8 15 mA - 10 50 µA - 20 100 µA Stand-By Current (CMOS) 128Mb, 256Mb, 512Mb devices IDD5 Stand-By Current (CMOS) 512Mb and 1Gb Dual Die devices E=VDD-0.2, WP=0/VDD ILI Input Leakage Current VIN= 0 to VDDmax - - ±10 µA ILO Output Leakage Current VOUT= 0 to VDDmax - - ±10 µA VIH Input High Voltage - VDD-0.4 - VDD+0.3 V VIL Input Low Voltage - -0.3 - 0.4 V VOH Output High Voltage Level IOH = -100µA VDD-0.1 - - V VOL Output Low Voltage Level IOL = 100µA - - 0.1 V IOL (RB) Output Low Current (RB) VOL = 0.1V 3 4 VLKO VDD Supply Voltage (Erase and Program lockout) - - - 34/56 mA 1.5 V NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 19. DC Characteristics, 3V Devices Symbol Parameter IDD1 IDD2 IDD3 Operating Current Test Conditions Min Typ Max Unit Sequential Read tRLRL minimum E=VIL, IOUT = 0 mA - 10 20 mA Program - - 10 20 mA Erase - - 10 20 mA - - 1 mA - - 2 mA - 10 50 µA - 20 100 µA Stand-by Current (TTL), 128Mb, 256Mb, 512Mb devices IDD4 Stand-by Current (TTL) 512Mb and 1Gb Dual Die devices Stand-By Current (CMOS) 128Mb, 256Mb, 512Mb devices IDD5 Stand-By Current (CMOS) 512Mb and 1Gb Dual Die devices E=VIH, WP=0V/VDD E=VDD-0.2, WP=0/VDD ILI Input Leakage Current VIN= 0 to VDDmax - - ±10 µA ILO Output Leakage Current VOUT= 0 to VDDmax - - ±10 µA VIH Input High Voltage - 2.0 - VDD+0.3 V VIL Input Low Voltage - −0.3 - 0.8 V VOH Output High Voltage Level IOH = −400µA 2.4 - - V VOL Output Low Voltage Level IOL = 2.1mA - - 0.4 V IOL (RB) Output Low Current (RB) VOL = 0.4V 8 10 VLKO VDD Supply Voltage (Erase and Program lockout) - - - mA 2.5 V 35/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 20. AC Characteristics for Command, Address, Data Input Symbol tALLWL tALHWL tCLHWL tCLLWL Alt. Symbol 1.8V Devices Parameter 3V Unit Devices Address Latch Low to Write Enable Low tALS AL Setup time Min 0 0 ns CL Setup time Min 0 0 ns Address Latch High to Write Enable Low Command Latch High to Write Enable Low tCLS Command Latch Low to Write Enable Low tDVWH tDS Data Valid to Write Enable High Data Setup time Min 20 20 ns tELWL tCS Chip Enable Low to Write Enable Low E Setup time Min 0 0 ns AL Hold time Min 10 10 ns CL hold time Min 10 10 ns tWHALH tWHALL tWHCLH tWHCLL Write Enable High to Address Latch High tALH Write Enable High to Address Latch Low Write Enable High to Command Latch High tCLH Write Enable High to Command Latch Low tWHDX tDH Write Enable High to Data Transition Data Hold time Min 10 10 ns tWHEH tCH Write Enable High to Chip Enable High E Hold time Min 10 10 ns tWHWL tWH Write Enable High to Write Enable Low W High Hold time Min 20 15 ns tWLWH tWP Write Enable Low to Write Enable High W Pulse Width Min 40 25(1) ns tWLWL tWC Write Enable Low to Write Enable Low Write Cycle time Min 60 50 ns Note: 1. If tELWL is less than 10ns, tWLWH must be minimum 35ns, otherwise, tWLWH may be minimum 25ns. 36/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Table 21. AC Characteristics for Operations Symbol tALLRL1 tALLRL2 tBHRL Alt. Symbol Min 10 10 ns Read cycle Min 10 10 ns Min 20 20 ns Read Busy time, 128Mb, 256Mb, 512Mb Dual Die Max 10 10 µs Read Busy time, 512Mb, 1Gb Max 15 12 µs Program Busy time Max 500 500 µs Erase Busy time Max 3 3 ms Reset Busy time, during ready Max 5 5 µs Reset Busy time, during read Max 5 5 µs Reset Busy time, during program Max 10 10 µs Reset Busy time, during erase Max 500 500 µs Command Latch Low to Read Enable Low Min 10 10 ns Data Hi-Z to Read Enable Low Min 0 0 ns Address Latch Low to Read Enable Low tRR Ready/Busy High to Read Enable Low tBLBH1 tPROG tBLBH3 tBERS Ready/Busy Low to Ready/Busy High tBLBH4 tWHBH1 tRST tCLLRL tCLR tDZRL tIR 3V Unit Devices Read Electronic Signature tAR tBLBH2 1.8V Devices Parameter Write Enable High to Ready/Busy High tr(1) tr(1) tEHBH tCRY Chip Enable High to Ready/Busy High (E intercepted read) Max tEHEL tCEH Chip Enable High to Chip Enable Low(2) Min 100 100 ns tEHQZ tCHZ Chip Enable High to Output Hi-Z Max 20 20 ns tELQV tCEA Chip Enable Low to Output Valid Max 45 45 ns tRHBL tRB Read Enable High to Ready/Busy Low Max 100 100 ns tRHRL tREH Read Enable High to Read Enable Low Min 15 15 ns tRHQZ tRHZ Read Enable High to Output Hi-Z Min 15 15 Max 30 30 tRLRH tRP Read Enable Low to Read Enable High Read Enable Pulse Width Min 30 30 ns tRLRL tRC Read Enable Low to Read Enable Low Read Cycle time Min 60 50 ns tRLQV tREA Read Enable Low to Output Valid Max 35 35 ns tWHBH tR Write Enable High to Ready/Busy High Read Busy time, 128Mb, 256Mb, 512Mb Dual Die Max 10 10 µs Read Busy time, 512Mb, 1Gb Max 15 12 µs Read Enable High Hold time 60 + 60 + ns ns Read Enable Access time Read ES Access time(3) tWHBL tWB Write Enable High to Ready/Busy Low Max 100 100 ns tWHRL tWHR Write Enable High to Read Enable Low Min 80 60 ns tWLWL tWC Write Enable Low to Write Enable Low Min 60 50 ns Write Cycle time Note: 1. The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figures 36, 37 and 38. 2. To break the sequential read cycle, E must be held High for longer than tEHEL. 3. ES = Electronic Signature. 37/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 25. Command Latch AC Waveforms CL tWHCLL tCLHWL (CL Setup time) (CL Hold time) tWHEH tELWL (E Hold time) (E Setup time) E tWLWH W tALLWL tWHALH (ALSetup time) (AL Hold time) AL tDVWH tWHDX (Data Setup time) (Data Hold time) Command I/O ai08028 Figure 26. Address Latch AC Waveforms tCLLWL (CL Setup time) CL tELWL tWLWL tWLWL (E Setup time) tWLWL E tWLWH tWLWH tWLWH tWLWH W tWHWL tALHWL tWHWL tWHWL (AL Setup time) tWHALL tWHALL tWHALL (AL Hold time) AL tDVWH tDVWH (Data Setup time) tDVWH tDVWH tWHDX tWHDX tWHDX tWHDX (Data Hold time) I/O Adrress cycle 1 Adrress cycle 2 Adrress cycle 3 Adrress cycle 4 ai08029 Note: Address cycle 4 is only required for 512Mb and 1Gb devices. 38/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 27. Data Input Latch AC Waveforms tWHCLH (CL Hold time) CL tWHEH (E Hold time) E tALLWL tWLWL (ALSetup time) AL tWLWH tWLWH tWLWH W tDVWH tDVWH tDVWH (Data Setup time) tWHDX tWHDX tWHDX (Data Hold time) I/O Data In 0 Data In 1 Data In Last ai08030 Figure 28. Sequential Data Output after Read AC Waveforms tRLRL (Read Cycle time) E tRHRL tEHQZ (R High Holdtime) R tRHQZ tRLQV tRLQV tRHQZ tRLQV (R Accesstime) I/O Data Out Data Out Data Out tBHRL RB ai08031 Note: 1. CL = Low, AL = Low, W = High. 39/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 29. Read Status Register AC Waveform tCLLRL CL tWHCLL tCLHWL tWHEH E tELWL tWLWH W tELQV tWHRL tEHQZ R tDZRL tDVWH tWHDX tRLQV Status Register Output 70h I/O tRHQZ (Data Hold time) (Data Setup time) ai08032 Figure 30. Read Electronic Signature AC Waveform CL E W AL tALLRL1 R tRLQV (Read ES Access time) I/O 90h Read Electronic Signature Command 00h 1st Cycle Address Man. code Manufacturer and Device Codes Note: Refer to Table 12. for the values of the Manufacturer and Device Codes. 40/56 Device code ai08039b NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 31. Page Read A/ Read B Operation AC Waveform CL tEHEL E tWLWL tEHQZ W tWHBL tEHBH AL tALLRL2 tWHBH tRLRL tRHQZ (Read Cycle time) R tRLRH tRHBL tBLBH1 RB I/O 00h or 01h Command Code Add.N cycle 1 Add.N cycle 2 Add.N cycle 3 Data N Add.N cycle 4 Address N Input Busy Data N+1 Data N+2 Data Last Data Output from Address N to Last Byte or Word in Page ai08033b Note: Address cycle 4 is only required for 512Mb and 1Gb devices. 41/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 32. Read C Operation, One Page AC Waveform CL E W tWHBH tWHALL AL tALLRL2 tBHRL R I/O 50h Add. M cycle 1 Add. M Add. M cycle 2 cycle 3 Add. M cycle 4 Data M Data Last RB Command Code Address M Input Busy Data Output from M to Last Byte or Word in Area C ai08035 Note: 1. A0-A7 is the address in the Spare Memory area, where A0-A3 are valid and A4-A7 are ‘don’t care’. 42/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 33. Page Program AC Waveform CL E tWLWL tWLWL tWLWL (Write Cycle time) W tWHBL tBLBH2 (Program Busy time) AL R I/O 80h Add.N cycle 1 Add.N Add.N Add.N cycle 2 cycle 3 cycle 4 N Last 10h 70h SR0 RB Page Program Setup Code Address Input Data Input Confirm Code Page Program Read Status Register ai08037 Note: Address cycle 4 is only required for 512Mb and 1Gb devices. 43/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 34. Block Erase AC Waveform CL E tWLWL (Write Cycle time) W tBLBH3 tWHBL (Erase Busy time) AL R I/O 60h Add. cycle 1 Add. Add. cycle 2 cycle 3 D0h 70h SR0 RB Block Erase Setup Command Block Address Input Confirm Code Block Erase Read Status Register ai08038b Note: Address cycle 3 is required for 512Mb and 1Gb devices only. Figure 35. Reset AC Waveform W AL CL R I/O FFh tBLBH4 (Reset Busy time) RB ai08043 44/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Ready/Busy Signal Electrical Characteristics Figures 37, 36 and 38 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor RP can be calculated using the following equation: Figure 37. Ready/Busy Load Circuit (V – ) DDmax V OLmax R P min = ----------------------------------------------------------I OL + I L 1,85V R P min ( 1,8V ) = --------------------------3mA + I L ibusy RP VDD So, DEVICE 3,2V R P min ( 3V ) = --------------------------8mA + I L RB Open Drain Output where IL is the sum of the input currents of all the devices tied to the Ready/Busy signal. RP max is determined by the maximum value of tr. Figure 36. Ready/Busy AC Waveform VSS ready VDD VOH VOL AI07563B busy tr tf AI07564B Figure 38. Resistor Value Versus Waveform Timings For Ready/Busy Signal VDD = 1.8V, CL = 30pF VDD = 3.3V, CL = 100pF 400 400 4 4 400 tr, tf (ns) 2 1.7 ibusy (mA) tr, tf (ns) 200 300 2.4 200 0 0.85 30 1.7 1 60 1.7 2 1.2 1 90 0.57 0.43 1.7 1.7 3 2 200 120 100 3 300 ibusy (mA) 3 300 100 0.8 1 3.6 3.6 100 0.6 0 4 3.6 3.6 1 2 RP (KΩ) 3 4 RP (KΩ) tf tr ibusy ai07565B Note: T = 25°C. 45/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A PACKAGE MECHANICAL Figure 39. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline 1 48 e D1 B 24 L1 25 A2 E1 E A A1 DIE α L C CP TSOP-G Note: Drawing is not to scale. Table 22. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data millimeters inches Symbol Typ Min A Typ Min 1.200 Max 0.0472 A1 0.100 0.050 0.150 0.0039 0.0020 0.0059 A2 1.000 0.950 1.050 0.0394 0.0374 0.0413 B 0.220 0.170 0.270 0.0087 0.0067 0.0106 0.100 0.210 0.0039 0.0083 C CP 46/56 Max 0.080 0.0031 D1 12.000 11.900 12.100 0.4724 0.4685 0.4764 E 20.000 19.800 20.200 0.7874 0.7795 0.7953 E1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 – – 0.0197 – – L 0.600 0.500 0.700 0.0236 0.0197 0.0276 L1 0.800 α 3° 0° 5° 0.0315 0° 5° 3° NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 40. WSOP48 – 48 lead Plastic Very Very Thin Small Outline, 12 x 17mm, Package Outline 1 48 e D1 b 24 L1 A2 25 E1 E A1 θ A L DIE c ddd WSOP-A Note: Drawing not to scale. Table 23. WSOP48 lead Plastic Very Very Thin Small Outline, 12 x 17mm, Mechanical Data millimeters inches Symbol Typ Min Max Typ Min Max A 0.65 0.026 A1 0.10 0.004 A2 0.52 0.47 0.57 0.020 0.019 0.022 b 0.16 0.13 0.23 0.006 0.005 0.009 c 0.10 0.08 0.17 0.004 0.003 0.007 D1 12.00 11.90 12.10 0.472 0.469 0.476 ddd 0.06 0.002 E 17.00 16.80 17.20 0.669 0.661 0.677 E1 15.40 15.30 15.50 0.606 0.602 0.610 e 0.50 – – 0.020 – – L 0.55 0.45 0.65 0.022 0.018 0.026 L1 0.25 – – 0.010 – – 0° 5° 0° 5° θ 47/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 41. VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Outline D D2 D1 SD e SE E1 E2 E FE FE1 b FD1 FD ddd A A2 A1 BGA-Z61 Note: Drawing is not to scale Table 24. VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data millimeters inches Symbol Typ Min A Typ Min 1.05 A1 Max 0.041 0.25 A2 0.010 0.70 0.028 b 0.45 0.40 0.50 0.018 0.016 0.020 D 8.00 7.90 8.10 0.315 0.311 0.319 D1 4.00 0.157 D2 5.60 0.220 ddd 48/56 Max 0.10 9.90 E 10.00 E1 5.60 0.220 E2 8.80 0.346 e 0.80 FD 2.00 0.079 FD1 1.20 0.047 FE 2.20 0.087 FE1 0.60 0.024 SD 0.40 0.016 SE 0.40 0.016 – 10.10 0.004 – 0.394 0.031 0.390 0.398 – – NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 42. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline D D2 D1 SD e SE E1 E2 E FE FE1 b FD1 FD ddd A A2 A1 BGA-Z61 Note: Drawing is not to scale Table 25. TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data Symbol millimeters Typ Min A inches Max Typ Min 1.20 A1 Max 0.047 0.25 0.010 A2 0.80 0.031 b 0.45 0.40 0.50 0.018 0.016 0.020 D 8.00 7.90 8.10 0.315 0.311 0.319 D1 4.00 0.157 D2 5.60 0.220 ddd 0.10 9.90 E 10.00 E1 5.60 0.220 E2 8.80 0.346 e 0.80 FD 2.00 0.079 FD1 1.20 0.047 FE 2.20 0.087 FE1 0.60 0.024 SD 0.40 0.016 SE 0.40 0.016 – 10.10 0.004 – 0.394 0.031 0.390 0.398 – – 49/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 43. VFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Outline D D2 D1 FD1 SD FD e e E E2 SE E1 FE FE1 ddd BALL "A1" e A b A2 A1 BGA-Z53 Note: Drawing is not to scale. Table 26. VFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data Symbol millimeters Typ Min A Max Typ Min 1.050 A1 Max 0.0413 0.250 A2 0.0098 0.700 0.0276 b 0.450 0.400 0.500 0.0177 0.0157 0.0197 D 8.500 8.400 8.600 0.3346 0.3307 0.3386 D1 4.000 0.1575 D2 7.200 0.2835 ddd 50/56 inches 0.100 14.900 15.100 0.0039 E 15.000 E1 5.600 0.2205 0.5906 E2 8.800 0.3465 e 0.800 0.0315 FD 2.250 0.0886 FD1 0.650 0.0256 FE 4.700 0.1850 FE1 3.100 0.1220 SD 0.400 0.0157 SE 0.400 0.0157 0.5866 0.5945 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 44. TFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Outline D D2 D1 FD1 SD FD e e E E2 SE E1 FE FE1 ddd BALL "A1" A e b A2 A1 BGA-Z53 Note: Drawing is not to scale Table 27. TFBGA63 8.5 x 15mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data Symbol millimeters Typ Min A inches Max Typ Min 1.200 Max 0.0472 A1 0.250 0.0098 A2 0.600 0.0236 b 0.450 0.400 0.500 0.0177 0.0157 0.0197 D 8.500 8.400 8.600 0.3346 0.3307 0.3386 D1 4.000 0.1575 D2 7.200 0.2835 ddd 0.100 14.900 E 15.000 E1 5.600 0.2205 E2 8.800 0.3465 e 0.800 FD 2.250 0.0886 FD1 0.650 0.0256 FE 4.700 0.1850 FE1 3.100 0.1220 SD 0.400 0.0157 SE 0.400 0.0157 – 15.100 0.0039 – 0.5906 0.0315 0.5866 0.5945 – – 51/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A PART NUMBERING Table 28. Ordering Information Scheme Example: NAND512R3A 0 A ZA 1 T Device Type NAND = NAND Flash Memory Density 128 = 128Mb 256 = 256Mb 512 = 512Mb 01G = 1Gb Operating Voltage R = VDD = 1.7 to 1.95V W = VDD = 2.7 to 3.6V Bus Width 3 = x8 4 = x16 Family Identifier A = 528 Bytes/ 264 Word Page Device Options 0 = No Options 1 = Automatic Page 0 Read at Power-up 2 = Chip Enable Don’t Care Enabled 3 = Chip Enable Don’t Care Enabled and Automatic Page 0 Read at Power-up Product Version A = 120nm process technology (Single Die 128Mb, 256Mb, 512Mb) (Dual Die 512Mb, 1Gb) Package N = TSOP48 12 x 20mm (all devices) V = WSOP48 12 x 17 x 0.65mm (128Mbit, 256Mbit and 512Mbit devices) ZA = VFBGA55 8 x 10 x 1mm, 6x8 ball array, 0.8mm pitch (128Mbit and 256Mbit devices) ZB = TFBGA55 8 x 10 x 1.2mm, 6x8 ball array, 0.8mm pitch (512Mbit Dual Die devices) ZA = VFBGA63 8.5 x 15 x 1mm, 6x8 ball array, 0.8mm pitch (512Mbit devices) ZB = TFBGA63 8.5 x 15 x 1.2mm, 6x8 ball array, 0.8mm pitch (1Gbit Dual Die devices) Temperature Range 1 = 0 to 70 °C 6 = –40 to 85 °C Option blank = Standard Packing T = Tape & Reel Packing E = Lead Free Package, Standard Packing F = Lead Free Package, Tape & Reel Packing Devices are shipped from the factory with the memory content bits, in valid blocks, erased to ’1’. For further information on any aspect of this device, please contact your nearest ST Sales Office. 52/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A APPENDIX A. HARDWARE INTERFACE EXAMPLES Nand Flash devices can be connected to a microcontroller system bus for code and data storage. For microcontrollers that have an embedded NAND controller the NAND Flash can be connected without the addition of glue logic (see Figure 45.). However a minimum of glue logic is required for general purpose microcontrollers that do not have an embedded NAND controller. The glue logic usually consists of a flip-flop to hold the Chip Enable, Address Latch Enable and Command Latch Enable signals stable during command and address latch operations, and some logic gates to simplify the firmware or make the design more robust. Figure 46. gives an example of how to connect a NAND Flash to a general purpose microcontroller. The additional OR gates allow the microcontroller’s Output Enable and Write Enable signals to be used for other peripherals. The OR gate between A3 and CSn maps the flip-flop and NAND I/O in different address spaces inside the same chip select unit, which improves the setup and hold times and simplifies the firmware. The structure uses the microcontroller DMA (Direct Memory Access) engines to optimize the transfer between the NAND Flash and the system RAM. For any interface with glue logic, the extra delay caused by the gates and flip-flop must be taken into account. This delay must be added to the microcontroller’s AC characteristics and register settings to get the NAND Flash setup and hold times. For mass storage applications (hard disk emulations or systems where a huge amount of storage is required) NAND Flash memories can be connected together to build storage modules (see Figure 47.). Figure 45. Connection to Microcontroller, Without Glue Logic AD(24:16) AD17 AL AD16 CL Microcontroller G R W W CSn E DQ NAND Flash I/O PWAITEN RB VDD or VSS or General Purpose I/O VDD WP AI08045b 53/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Figure 46. Connection to Microcontroller, With Glue Logic G R W W CSn A3 CLK D flip-flop Microcontroller NAND Flash A2 D2 Q2 CL A1 D1 Q1 AL A0 D0 Q0 E DQ I/O AI07589 Figure 47. Building Storage Modules E1 CL AL W G NAND Flash Device 1 E2 NAND Flash Device 2 E3 En NAND Flash Device 3 NAND Flash Device n En+1 NAND Flash Device n+1 RB I/O0-I/O7 or I/O0-I/O15 54/56 AI08331 NAND128-A, NAND256-A, NAND512-A, NAND01G-A RELATED DOCUMENTATION STMicroelectronics has published a set of application notes to support the NAND Flash memories. They are available from the ST Website www.st.com. or from your local ST Distributor. REVISION HISTORY Table 29. Document Revision History Date Version Revision Details 06-Jun-2003 1.0 First Issue 07-Aug-2003 2.0 Design Phase 27-Oct-2003 3.0 Engineering Phase 4.0 Document promoted from Target Specification to Preliminary Data status. VCC changed to VDD and ICC to IDD. Title of Table 2.. changed to “Product Description” and Page Program Typical Timing for NANDXXXR3A devices corrected. Table 1., Product List, inserted on page 2. 5.0 WSOP48 and VFBGA55 packages added, VFBGA63 (9 x 11 x 1mm) removed. Figure 19., Cache Program Operation, modified and note 2 modified. Note removed for tWLWH timing in Table 20., AC Characteristics for Command, Address, Data Input. Meaning of tBLBH4 modified, partly replaced by tWHBH1 and tWHRL min for 3V devices modified in Table 21., AC Characteristics for Operations. References removed from RELATED DOCUMENTATION section and reference made to ST Website instead. Figure 6., Figure 7., Figure 31. and Figure 34. modified. Read Electronic Signature paragraph clarified and Figure 30., Read Electronic Signature AC Waveform, modified. Note 2 to Figure 32., Read C Operation, One Page AC Waveform, removed. Note 3 to Table 7., Address Insertion, x16 Devices removed. Only 00h Pointer operations are valid before a Cache Program operation. IDD4 removed from Table 18., DC Characteristics, 1.8V Devices. Note added to Figure 34., Block Erase AC Waveform. Small text changes. 6.0 TFBGA55 package added (mechanical data to be announced). 512Mb Dual Die devices added. Figure 19., Cache Program Operation modified. Package code changed for TFBGA63 8.5 x 15 x 1.2mm, 6x8 ball array, 0.8mm pitch (1Gbit Dual Die devices) in Table 28., Ordering Information Scheme. 7.0 Cache Program removed from document. TFBGA55 package specifications added (Figure 42., TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline and Table 25., TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data). Test conditions modified for VOL and VOH parameters in Table 19., DC Characteristics, 3V Devices. 03-Dec-2003 13-Apr-2004 28-May-2004 02-Jul-2004 55/56 NAND128-A, NAND256-A, NAND512-A, NAND01G-A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 56/56