P-L496G-CELL01

STM32L496xx Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100 DMIPS, up to 1 MB flash, 320 KB SRAM, USB OTG FS, audio, external SMPS Datasheet - production data Features Includes ST state-of-the-art patented technology LQFP64 (10 x 10) LQFP100 (14 x 14) LQFP144 (20 × 20) • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/125 °C temperature range – 320 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – 25 nA Shutdown mode (5 wakeup pins) – 108 nA Standby mode (5 wakeup pins) – 426 nA Standby mode with RTC – 2.57 µA Stop 2 mode, 2.86 µA Stop 2 with RTC – 91 µA/MHz run mode (LDO mode) – 37 μA/MHz run mode (at 3.3 V SMPS mode) – Batch acquisition mode (BAM) – 5 µs wakeup from Stop mode – Brown out reset (BOR) in all modes except shutdown – Interconnect matrix • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from flash memory, frequency up to 80 MHz, MPU, 100 DMIPS and DSP instructions • Performance benchmark – 1.25 DMIPS/MHz (Drystone 2.1) – 273.55 Coremark® (3.42 Coremark/MHz at 80 MHz) • Energy benchmark – 279 ULPMark™ CP score – 80.2 ULPMark™ PP score • 16 timers: 2x 16-bit advanced motor-control, 2x 32-bit and 5x 16-bit general purpose, 2x 16-bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer July 2022 This is information on a product in full production. WLCSP115 (4.63 x 4.15 mm) WLCSP100L UFBGA169 (7 x 7) UFBGA132 (7 × 7) • RTC with HW calendar, alarms and calibration • Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V • Dedicated Chrom-ART Accelerator for enhanced graphic content creation (DMA2D) • 8- to 14-bit camera interface up to 32 MHz (black & white) or 10 MHz (color) • Memories – Up to 1 MB flash, 2 banks read-while-write, proprietary code readout protection – 320 KB of SRAM including 64 KB with hardware parity check – External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories – Dual-flash Quad SPI memory interface • Clock sources – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator for RTC (LSE) – Internal 16 MHz factory-trimmed RC (±1%) – Internal low-power 32 kHz RC (±5%) – Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25% accuracy) – Internal 48 MHz with clock recovery – 3 PLLs for system clock, USB, audio, ADC • LCD 8× 40 or 4× 44 with step-up converter • Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors DS11585 Rev 16 1/284 www.st.com STM32L496xx • 4x digital filters for sigma delta modulator • Rich analog peripherals (independent supply) – 3× 12-bit ADCs 5 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps – 2x 12-bit DAC output channels, low-power sample and hold – 2x operational amplifiers with built-in PGA – 2x ultra-low-power comparators – 5x U(S)ARTs (ISO 7816, LIN, IrDA, modem) – 1x LPUART – 3x SPIs (4x SPIs with the Quad SPI) – 2x CANs (2.0B Active) and SDMMC – SWPMI single wire protocol master I/F – IRTIM (Infrared interface) • 14-channel DMA controller • 20x communication interfaces • True random number generator – USB OTG 2.0 full-speed, LPM and BCD • CRC calculation unit, 96-bit unique ID – 2x SAIs (serial audio interface) • Development support: serial wire debug – 4x I2C FM+(1 Mbit/s), SMBus/PMBus Table 1. Device summary 2/284 Reference Part numbers STM32L496xx STM32L496AG, STM32L496QG, STM32L496RG, STM32L496VG, STM32L496WG, STM32L496ZG, STM32L496AE, STM32L496QE, STM32L496RE, STM32L496VE, STM32L496ZE DS11585 Rev 16 STM32L496xx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 18 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 22 3.10 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.10.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.10.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.10.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.11 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.14 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.15 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.16 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.17 3.16.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 41 3.16.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 41 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.17.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.17.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DS11585 Rev 16 3/284 6 Contents STM32L496xx 3.17.3 4/284 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.18 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.19 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.20 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.21 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.22 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.23 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.24 Digital filter for Sigma-Delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 46 3.25 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.26 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.27 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.27.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.27.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.27.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.27.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 50 3.27.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.27.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.27.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.27.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.28 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 52 3.29 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.30 Universal synchronous/asynchronous receiver transmitter (USART) . . . 54 3.31 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 55 3.32 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.33 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.34 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 57 3.35 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.36 Secure digital input/output and MultiMediaCards interface (SDMMC) . . . 58 3.37 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 58 3.38 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.39 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 59 3.40 Dual-flash Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . 60 3.41 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DS11585 Rev 16 STM32L496xx Contents 3.41.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.41.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 125 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 126 6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.6 Wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.3.12 +Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 181 6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 182 DS11585 Rev 16 5/284 6 Contents 7 STM32L496xx 6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 195 6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 200 6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.3.25 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 6.3.26 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 6.3.27 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 6.3.28 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 212 6.3.29 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 6.3.30 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 241 6.3.31 SWPMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 6.3.32 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 242 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 7.1 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 7.2 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 7.3 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 7.4 WLCSP115 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 7.5 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 7.6 WLCSP100L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 7.7 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 275 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 6/284 DS11585 Rev 16 STM32L496xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32L496xx features and peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 19 STM32L496xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STM32L496xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 STM32L496xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 STM32L496xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 STM32L496xx memory map and peripheral register boundary addresses . . . . . . . . . . . 116 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 126 Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Current consumption in Run and Low-power run modes, code with data processing running from flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 130 Current consumption in Run modes, code with data processing running from flash, (ART enable Cache ON Prefetch OFF) and power supplied (by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Current consumption in Run and Low-power run modes, code with data processing running from flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Current consumption in Run modes, code with data processing running from flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . 133 Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Current consumption in Run, code with data processing running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . 135 Typical current consumption in Run and Low-power run modes, with different codes running from flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 136 Typical current consumption in Run, with different codes running from flash, ART enable (Cache ON Prefetch OFF) and power supplied (by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Typical current consumption in Run, with different codes running from flash, ART enable (Cache ON Prefetch OFF) and power supplied (by external SMPS (VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Typical current consumption in Run and Low-power run modes, with different codes running from flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 DS11585 Rev 16 7/284 10 List of tables Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. 8/284 STM32L496xx Typical current consumption in Run modes, with different codes running from flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . 138 Typical current consumption in Run modes, with different codes running from flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V) . . . . . . . . 138 Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Typical current consumption in Run, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . 139 Typical current consumption in Run, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . 140 Current consumption in Sleep and Low-power sleep modes, flash ON . . . . . . . . . . . . . . 141 Current consumption in Sleep, flash ON and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Current consumption in Low-power sleep modes, flash in power-down. . . . . . . . . . . . . . 143 Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 EMI characteristics for fHSE = 8 MHz and fHCLK = 80 MHz . . . . . . . . . . . . . . . . . . . . . 172 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 EXTI Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 DS11585 Rev 16 STM32L496xx Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. List of tables DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 221 eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 221 USB OTG DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 226 Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 226 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 227 Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 228 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 229 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 231 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 236 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Switching characteristics for NAND flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Switching characteristics for NAND flash write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 243 SD / MMC dynamic characteristics, VDD=1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . 244 UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 246 LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 UFBGA132 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 UFBGA132 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 256 WLCSP115 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 WLCSP115 - recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 WLCSP100L - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 WLCSP100L - Recommended PCB design rules (0.4 mm pitch). . . . . . . . . . . . . . . . . . . 268 LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 DS11585 Rev 16 9/284 10 List of tables STM32L496xx Table 134. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Table 135. STM32L496xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Table 136. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 10/284 DS11585 Rev 16 STM32L496xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. STM32L496xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32L496Ax UFBGA169 pinout(1) (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 STM32L496Ax, external SMPS device, UFBGA169 pinout(1) (2) . . . . . . . . . . . . . . . . . . . . 63 STM32L496Zx LQFP144 pinout(1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 STM32L496Zx, external SMPS device, LQFP144 pinout(1) (2) . . . . . . . . . . . . . . . . . . . . . . 65 STM32L496Qx UFBGA132 ballout(1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 STM32L496Qx, external SMPS device, UFBGA132 ballout(1) (2). . . . . . . . . . . . . . . . . . . . 66 STM32L496Wx, external SMPS device, WLCSP115 ballout(1) (2) . . . . . . . . . . . . . . . . . . . 67 STM32L496Vx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 STM32L496Vx, external SMPS device, LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . 68 STM32L496Vx WLCSP100L pinout(1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 STM32L496Vx, external SMPS device, WLCSP100L pinout(1) (2) . . . . . . . . . . . . . . . . . . . 69 STM32L496Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 STM32L496Rx, external SMPS, LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 STM32L496xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Current consumption measurement scheme with and without external SMPS power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 DS11585 Rev 16 11/284 12 List of figures Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. 12/284 STM32L496xx SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 USB OTG timings – Definition of data signal rise and fall time. . . . . . . . . . . . . . . . . . . . . 223 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 225 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 227 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 228 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 230 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 236 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 239 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 240 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 UFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 UFBGA169 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 UFBGA169 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 UFBGA169 (external SMPS device) marking (package top view) . . . . . . . . . . . . . . . . . . 248 LQFP144 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 LQFP144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 LQFP144 (external SMPS device) marking (package top view). . . . . . . . . . . . . . . . . . . . 254 UFBGA132 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 UFBGA132 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 UFBGA132 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 UFBGA132 (external SMPS device) marking (package top view) . . . . . . . . . . . . . . . . . . 257 WLCSP115 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 WLCSP115 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 WLCSP115 (external SMPS device) marking (package top view) . . . . . . . . . . . . . . . . . . 261 LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 LQFP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 LQFP100 (external SMPS device) marking (package top view). . . . . . . . . . . . . . . . . . . . 265 WLCSP100L - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 WLCSP100L - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 WLCSP100L marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 WLCSP100L (external SMPS device) marking (package top view) . . . . . . . . . . . . . . . . . 269 LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 LQFP64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 LQFP64 (external SMPS device) marking (package top view). . . . . . . . . . . . . . . . . . . . . 273 DS11585 Rev 16 STM32L496xx 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L496xx microcontrollers. This document must be read in conjunction with the STM32L47x, STM32L48x, STM32L49x and STM32L4Ax reference manual (RM0351), available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 Technical Reference Manual, available from the www.arm.com website. For information on the device errata with respect to the datasheet and reference manual, refer to the STM32L496xx errata sheet (ES0335), available on the STMicroelectronics website www.st.com. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. DS11585 Rev 16 13/284 61 Description 2 STM32L496xx Description The STM32L496xx devices are ultra-low-power microcontrollers based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision that supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32L496xx devices embed high-speed memories (up to 1 Mbyte of flash memory, 320 Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. The STM32L496xx devices embed several protection mechanisms for embedded flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall. The devices offer up to three fast 12-bit ADCs (5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four digital filters for external sigma delta modulators (DFSDM). In addition, up to 24 capacitive sensing channels are available. The devices also embed an integrated LCD driver 8x40 or 4x44, with internal step-up converter. They also feature standard and advanced communication interfaces, namely four I2Cs, three SPIs, three USARTs, two UARTs and one Low-Power UART, two SAIs, one SDMMC, two CANs, one USB OTG full-speed, one SWPMI (single wire protocol master interface), a camera interface and a DMA2D controller. The STM32L496xx operates in the -40 to +85 °C (+105 °C junction), -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V VDD power supply when using internal LDO regulator and a 1.05 to 1.32V VDD12 power supply when using external SMPS supply. A comprehensive set of power-saving modes makes possible the design of lowpower applications. Some independent power supplies are supported: analog independent supply input for ADC, DAC, OPAMPs and comparators, 3.3 V dedicated supply input for USB and up to 14 I/Os can be supplied independently down to 1.08 V. A VBAT input makes it possible to backup the RTC and backup registers. Dedicated VDD12 power supplies can be used to bypass the internal LDO regulator when connected to an external SMPS. The STM32L496xx family offers seven packages from 64-pin to 169-pin packages. 14/284 DS11585 Rev 16 STM32L496xx Description Table 2. STM32L496xx features and peripherals Peripheral Flash memory (bytes) STM32 L496Ax 512 K 1M STM32 L496Zx 512 K 1M STM32 L496Qx 512 K 1M SRAM (bytes) External controller for static memories 512 K 1M STM32 L496Vx 512 K 1M STM32 L496Rx 512 K 1M 320 K Yes Yes Yes(1) Yes Quad SPI Timers STM32 L496Wx Yes(1) No Yes Yes(2) Yes Advanced control 2 (16-bit) General purpose 5 (16-bit) 2 (32-bit) Basic 2 (16-bit) Low power 2 (16-bit) SysTick timer 1 Watchdog timers (independent window) 2 SPI 3 2C 4 I USART UART LPUART 3 2 1 Comm. interfaces SAI 2 CAN 2 USB OTG FS Yes SDMMC Yes SWPMI Yes Digital filters for sigma-delta modulators Yes (4 filters) Number of channels 8 RTC Yes Tamper pins Camera interface 3 Yes(2) Yes Chrom-ART Accelerator™ LCD COM x SEG Yes Yes 8x40 or 4x44 Random generator Yes DS11585 Rev 16 15/284 61 Description STM32L496xx Table 2. STM32L496xx features and peripherals (continued) Peripheral STM32 L496Ax STM32 L496Zx STM32 L496Qx STM32 L496Wx STM32 L496Vx STM32 L496Rx GPIOs(3) Wakeup pins Nb of I/Os down to 1.08 V(4) 136 5 14 115 5 14 110 5 14 86 5 13 83 5 0 52 4 0 Capacitive sensing Number of channels 24 24 24 18 21 21 12-bit ADCs Number of channels 3 24 3 24 3 19 3 16 3 16 3 16 12-bit DAC channels 2 Internal voltage reference buffer Yes Analog comparators 2 Operational amplifiers 2 Maximum CPU frequency 80 MHz Operating voltage (VDD) 1.71 to 3.6 V Operating voltage (VDD12) 1.05 to 1.32 V Ambient operating temperature: -40 to 85 °C / -40 to 125 °C Junction temperature: -40 to 105 °C / -40 to 130 °C Operating temperature Packages UFBGA169 LQFP144 UFBGA132 WLCSP115 LQFP100 WLCSP100L LQFP64 1. For LQFP100, WLCSP100L and WLCSP115 packages, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip select. 2. Only up to 13 data bits. 3. If an external SMPS package type is used, two GPIOs are replaced by VDD12 pins to connect the SMPS power supplies, reducing the number of available GPIOs by two. 4. These GPIOs are supplied by VDDIO2. 16/284 DS11585 Rev 16 STM32L496xx Description Figure 1. STM32L496xx block diagram Flexible static memory controller (FSMC): SRAM, PSRAM, NOR flash, NAND flash NJTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO JTAG & SW MPU ETM NVIC TRACECLK TRACED[3:0] CLK, NE[4:1], NL, NBL[1:0], A[25:0], D[15:0], NOE, NWE, NWAIT, NCE3, INT3 as AF D0[3:0], D1[3:0], CLK0, CLK1, CS Quad SPI memory interface D-BUS ARM Cortex-M4 80 MHz FPU I-BUS ART ACCEL/ CACHE FIFO HSYNC, VSYNC, PIXCLK, D[13:0] Camera Interface @ VDDUSB SRAM 256 KB SRAM 64 KB DMA2 Voltage regulator 3.3 to 1.2 V VDD12 VDD = 1.71 to 3.6 V VDD12 = 1.05 to 1.32 V(1) VSS DMA1 @ VDD @ VDD 8 Groups of 4 channels max as AF RC HSI PA[15:0] Supply supervision reset MSI Touch sensing controller VDDIO, VDDUSB Int BOR GPIO PORT A VDDA, VSSA RC LSI GPIO PORT B PC[15:0] GPIO PORT C PD[15:0] GPIO PORT D PE[15:0] GPIO PORT E PF[15:0] GPIO PORT F PG[15:0] GPIO PORT G PH[15:0] GPIO PORT H PI[11:0] GPIO PORT I VDD, VSS, NRST PVD, PVM PLL 1&2&3 AHB1 80 MHz PB[15:0] DP DM SCL, SDA, INTN, ID, VBUS, SOF Power management VDD AHB2 80 MHz USB OTG PHY FIFO FIFO CHROM-ART DMA2D RNG Flash up to 1 MB AHB bus-matrix S-BUS @VDD HSI48 OSC_IN OSC_OUT XTAL OSC 4- 48MHz IWDG Standby interface Reset & clock M AN AGT control @VBAT XTAL 32 kHz OSC32_IN OSC32_OUT PCLKx FCLK HCLKx RTC RTC_TS RTC_TAMPx RTC_OUT AWU Backup register VBAT = 1.55 to 3.6 V @ VDD U STemperature AR T 2 M B ps sensor TIM2 32b 4 channels, ETR as AF TIM3 16b 4 channels, ETR as AF TIM4 16b 4 channels, ETR as AF TIM5 32b CRC @ VDDA ADC1 8 analog inputs common to the 3 ADCs 8 analog inputs common to the ADC1 & 2 ADC2 IF ITF ADC3 8 analog inputs for ADC3 @ VDDA smcard IrDA RX, TX, CK, CTS, RTS as AF USART3 smcard IrDA RX, TX, CK, CTS, RTS as AF VREF+ VREF Buffer AHB/APB2 114 AF SDIO / MMC 3 compl. channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF TIM1 / PWM 3 compl. Channels (TIM1_CH[1:3]N), 4 channels (TIM1_CH[1:4]), ETR, BKIN, BKIN2 as AF 2 channels, 1 compl. channel, BKIN as AF 1 channel, 1 compl. channel, BKIN as AF TIM8 / PWM FIFO EXT IT. WKUP D[7:0] CMD, CK as AF 16b UART4 RX, TX, CTS, RTS as AF UART5 RX, TX, CTS, RTS as AF SP2 MOSI, MISO, SCK, NSS as AF SP3 MOSI, MISO, SCK, NSS as AF I2C1/SMBUS 16b SCL, SDA, SMBA as AF WWDG MOSI, MISO, SCK, NSS as AF MCLK_A, SD_A, FS_A, SCK_A, EXTCLK MCLK_B, SD_B, FS_B, SCK_B as AF 16b TIM17 16b USART1 TIM6 16b TIM7 16b MCLK_A, SD_A, FS_A, SCK_A, EXTCLK MCLK_B, SD_B, FS_B, SCK_B as AF SAI2 SDCKIN[7:0], SDDATIN[7:0], SDCKOUT,SDTRIG as AF A 60PM B Hz 2 SPI1 SAI1 SCL, SDA, SMBA as AF I2C3/SMBUS SCL, SDA, SMBA as AF I2C4/SMBUS SCL, SDA, SMBA as AF bxCAN1 bxCAN1 TX, RX as AF TX, RX as AF @VDDA VLCD DFSDM @ VDDA FIFO TIM16 P B (max) 1 3 0 M Hz APB1 80 A MHz smcard IrDA I2C2/SMBUS 16b APB2 80MHz TIM15 1 channel, 1 compl. channel, BKIN as AF RX, TX, CK,CTS, RTS as AF AHB/APB1 4 channels, ETR as AF USART2 OpAmp1 OUT, INN, INP OpAmp2 OUT, INN, INP LCD Booster VLCD = 2.5V to 3.6V SEGx, COMx as AF INP, INN, OUT COMP1 LCD 8x40 INP, INN, OUT COMP2 LPUART1 RX, TX, CTS, RTS as AF @ VDDA SWPMI SWP LPTIM1 IN1, IN2, OUT, ETR as AF LPTIM2 IN1, OUT, ETR as AF Firewall ITF DAC1 CRS DAC1_OUT1 1. Only available when using external SMPS supply mode Note: DAC1_OUT2 CRS_SYNC MS50053V1 AF: alternate function on I/O pins. DS11585 Rev 16 17/284 61 Functional overview STM32L496xx 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems, developed to provide a low-cost platform that meets the needs of MCU implementation with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm® core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions enabling efficient signal processing and complex algorithm execution. Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation. With its embedded Arm® core, the STM32L496xx family is compatible with all Arm® tools and software. Figure 1 shows the general block diagram of the STM32L496xx family devices. 3.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies. To release the processor near 100 DMIPS performance at 80 MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from flash memory at a CPU frequency up to 80 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 Gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 18/284 DS11585 Rev 16 STM32L496xx 3.4 Functional overview Embedded flash memory STM32L496xx devices feature up to 1 Mbyte of embedded flash memory available for storing programs and data. The flash memory is divided into two banks allowing read-whilewrite operations. This feature permits to perform a read operation from one bank while an erase or program operation is performed to the other bank. The dual bank boot is also supported. Each bank contains 256 pages of 2 Kbyte. Flexible protections can be configured thanks to option bytes: • Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: memory readout protection: the flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected – Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible. Table 3. Access status versus readout protection level and execution modes Area Debug, boot from RAM or boot from system memory (loader) User execution Protection level Read Write Erase Read Write Erase Main memory 1 Yes Yes Yes No No No 2 Yes Yes Yes N/A N/A N/A System memory 1 Yes No No Yes No No 2 Yes No No N/A N/A N/A Option bytes 1 Yes Yes Yes Yes Yes Yes 2 Yes No No N/A N/A N/A No No N/A(1) Backup registers SRAM2 (1) 1 Yes Yes N/A 2 Yes Yes N/A N/A N/A N/A 1 Yes Yes Yes(1) No No No(1) 2 Yes Yes Yes N/A N/A N/A 1. Erased when RDP change from Level 1 to Level 0. • Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity. • Proprietary code readout protection (PCROP): a part of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. One area per bank can be selected, with 64-bit granularity. An additional option bit (PCROP_RDP) allows the user to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. DS11585 Rev 16 19/284 61 Functional overview STM32L496xx The whole non-volatile memory embeds the error correction code (ECC) feature supporting: • single error detection and correction • double error detection. The address of the ECC fail can be read in the ECC register. 3.5 Embedded SRAM STM32L496xx devices feature 320 Kbyte of embedded SRAM, split into two blocks: • 256 Kbyte mapped at address 0x2000 0000 (SRAM1) • 64 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2). This memory is also mapped at address 0x2004 0000, offering a contiguous address space with the SRAM1. This block is accessed through the ICode/DCode buses for maximum performance. These 64 Kbyte SRAM can also be retained in Standby mode. The SRAM2 can be write-protected with 1 Kbyte granularity. The memory can be accessed in read/write at CPU clock speed with 0 wait states. 20/284 DS11585 Rev 16 STM32L496xx 3.6 Functional overview Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs and the DMA2D) and the slaves (flash memory, RAM, FMC, QUADSPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high speed peripherals work simultaneously. Figure 2. Multi-AHB bus matrix ARM® CORTEX®-M4 with FPU S0 S1 S2 DMA1 DMA2 DMA2D S3 S4 S5 M1 DCode ACCEL M0 ICode FLASH 1 MB SRAM1 128KB M2 128KB M3 SRAM2 M4 AHB1 peripherals M5 AHB2 peripherals M6 FMC M7 QUADSPI BusMatrix-S MSv38030V3 3.7 Firewall The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas. Each illegal access generates a reset which kills immediately the detected intrusion. DS11585 Rev 16 21/284 61 Functional overview STM32L496xx The Firewall main features are the following: • Three segments can be protected and defined thanks to the Firewall registers: – Code segment (located in flash or SRAM1 if defined as executable protected area) – Non-volatile data segment (located in flash) – Volatile data segment (located in SRAM1) • The start address and the length of each segments are configurable: – Code segment: up to 1024 Kbyte with granularity of 256 bytes – Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes – Volatile data segment: up to 256 Kbyte of SRAM1 with a granularity of 64 bytes • Specific mechanism implemented to open the Firewall to get access to the protected areas (call gate entry sequence) • Volatile data segment can be shared or not with the non-protected code • Volatile data segment can be executed or not depending on the Firewall configuration The flash readout protection must be set to level 2 in order to reach the expected level of protection. 3.8 Boot modes At startup, BOOT0 pin and nBOOT1 option bit are used to select one of three boot options: • Boot from user flash memory • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the flash memory by using USART, I2C, SPI, CAN or USB OTG FS in Device mode through DFU (device firmware upgrade). BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed. An empty check mechanism is implemented to force the boot from system flash if the first memory location is not programmed and if the boot selection is configured to boot from main flash. If the boot selection uses BOOT0 pin to boot from the main flash memory, but the first flash memory location is found empty, the flash empty check mechanism forces boot from the system memory (containing embedded bootloader). Then due to bootloader activation, some of the GPIOs are reconfigured from the High-Z state. Please refer to AN2606 for more details concerning the bootloader and GPIOs configuration in system memory boot mode. It is possible to disable this feature by configuring the option bytes (instead of BOOT0 pin) to force boot from the main flash memory (nSWBOOT0 = 0, nBOOT0 = 1). 3.9 Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity. The CRC calculation unit helps compute a signature of 22/284 DS11585 Rev 16 STM32L496xx Functional overview the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.10 Power supply management 3.10.1 Power supply schemes • VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins. • VDD12 = 1.05 to 1.32 V: external power supply bypassing internal regulator when connected to an external SMPS. It is provided externally through VDD12 pins and only available on packages with the external SMPS supply option. VDD12 does not require any external decoupling capacitance and cannot support any external load. • VDDA = 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMPs) to 3.6 V: external analog power supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The VDDA voltage level is independent from the VDD voltage. • VDDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers. The VDDUSB voltage level is independent from the VDD voltage. • VDDIO2 = 1.08 to 3.6 V: external power supply for 14 I/Os (PG[15:2]). The VDDIO2 voltage level is independent from the VDD voltage. • VLCD = 2.5 to 3.6 V: the LCD controller can be powered either externally through VLCD pin, or internally from an internal voltage generated by the embedded step-up converter. • VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Note: When the functions supplied by VDDA, VDDUSB or VDDIO2 are not used, these supplies should preferably be shorted to VDD. Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V tolerant (refer to Table 19: Voltage characteristics). Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1 or VDDIO2, with VDDIO1 = VDD. VDDIO2 supply voltage level is independent from VDDIO1. DS11585 Rev 16 23/284 61 Functional overview STM32L496xx Figure 3. Power supply overview VDDA domain VDDA VSSA A/D converters comparators D/A converters operational amplifiers Voltage reference buffer VLCD LCD VDDUSB VSS USB transceivers VDDIO2 domain VDDIO2 VDDIO2 VSS I/O ring PG[15:2] VDD domain VDDIO1 I/O ring VCORE domain Reset block Temp. sensor PLL, HSI, MSI VSS VDD Standby circuitry (Wakeup logic, IWDG) Core Memories Digital peripherals VCORE Voltage regulator VDD12 Low voltage detector Backup domain VBAT LSE crystal 32 K osc BKP registers RCC BDCR register RTC MSv43899V1 During power-up and power-down phases, the following power sequence requirements must be respected: • When VDD is below 1 V, other power supplies (VDDA, VDDUSB, VDDIO2, VLCD) must remain below VDD + 300 mV. • When VDD is above 1 V, all power supplies are independent. During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ; this allows external decoupling capacitors to be discharged with different time constants during the power-down transient phase. 24/284 DS11585 Rev 16 STM32L496xx Functional overview Figure 4. Power-up/down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down time VDDX independent from VDD MSv47490V1 1. VDDX refers to any power supply among VDDA, VDDUSB, VDDIO2, VLCD. 3.10.2 Power supply supervisor The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down. The device remains in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. In addition, the device embeds a Peripheral Voltage Monitor which compares the independent supply voltages VDDA, VDDUSB, VDDIO2 with a fixed threshold in order to ensure that the peripheral is in its functional supply range. DS11585 Rev 16 25/284 61 Functional overview 3.10.3 STM32L496xx Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR). • The MR is used in the Run and Sleep modes and in the Stop 0 mode. • The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is also used to supply the 64 Kbyte SRAM2 in Standby with SRAM2 retention. • Both regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. The ultralow-power STM32L496xx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the Main Regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency. There are two power consumption ranges: • Range 1 with the CPU running at up to 80 MHz. • Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also limited to 26 MHz. The VCORE can be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode. • Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by HSI16. When the MR is in use, the STM32L496xx with the external SMPS option permits to force an external VCORE supply on the VDD12 supply pins. When VDD12 is forced by an external source and is higher than the output of the internal LDO, the current is taken from this external supply and the overall power efficiency is significantly improved if using an external step down DC/DC converter. 3.10.4 Low-power modes The ultra-low-power STM32L496xx supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources. 26/284 DS11585 Rev 16 Mode Regulator(1) CPU Flash SRAM Clocks MR range 1 Run SMPS range 2 High MR range 2 LPR Yes ON(4) ON Any Yes ON(4) ON Any except PLL SMPS range 2 High MR range 2 No ON(4) ON(7) DS11585 Rev 16 LPR No ON(4) ON(7) No ON 93 µA/MHz N/A 129 µA/MHz to Range 1: 4 µs to Range 2: 64 µs 11.5 µA/MHz(5) 30 µA/MHz 6 cycles 13 µA/MHz(6) Any except PLL All except OTG_FS, RNG Any interrupt or event LSE LSI BOR, PVD, PVM RTC,LCD, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1,2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...4)(10) LPTIMx (x=1,2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...4)(10) LPTIMx (x=1,2) OTG_FS(11) SWPMI1(12) 51 µA/MHz 6 cycles TBD 2.7 µs in SRAM 6.2 µs in flash 127 µA 27/284 Functional overview MR Range 2(8) OFF 40 µA/MHz(5) 32 µA/MHz All except OTG_FS, RNG MR Range 1(8) Stop 0 N/A Any interrupt or event Any Wakeup time 39 µA/MHz(6) All SMPS range 2 Low LPSleep N/A All except OTG_FS, RNG Consumption(3) 108 µA/MHz All except OTG_FS, RNG MR range 1 Sleep Wakeup source All SMPS range 2 Low LPRun DMA and peripherals(2) STM32L496xx Table 4. STM32L496xx modes overview Mode Stop 1 DS11585 Rev 16 Stop 2 Regulator LPR LPR CPU No No DMA and peripherals(2) Wakeup source Consumption(3) Wakeup time LSE LSI BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1,2) DAC1 OPAMPx (x=1,2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...4)(10) LPTIMx (x=1,2) *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) USARTx (x=1...5)(9) LPUART1(9) I2Cx (x=1...4)(10) LPTIMx (x=1,2) OTG_FS(11) SWPMI1(12) 11.2 µA w/o RTC 11.8 µA w RTC 6.6 µs in SRAM 7.8 µs in flash LSE LSI BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) I2C3(10) LPUART1(9) LPTIM1 *** All other peripherals are frozen. Reset pin, all I/Os BOR, PVD, PVM RTC, LCD, IWDG COMPx (x=1..2) I2C3(10) LPUART1(9) LPTIM1 2.57 µA w/o RTC 2.86 µA w/RTC Flash SRAM Clocks Off Off ON ON Functional overview 28/284 Table 4. STM32L496xx modes overview (continued) (1) 6.8 µs in SRAM 8.2 µs in flash STM32L496xx Mode Regulator CPU Flash SRAM Clocks Standby OFF Shutdown OFF Power ed Off Power ed Off Off Off Power ed Off Power ed Off Wakeup source Consumption(3) Wakeup time 0.48 µA w/o RTC 0.78 µA w/ RTC DS11585 Rev 16 LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pull-down Reset pin 5 I/Os (WKUPx)(13) BOR, RTC, IWDG LSE RTC *** All other peripherals are powered off. *** I/O configuration can be floating, pull-up or pulldown(14) Reset pin 5 I/Os (WKUPx)(14) RTC SRAM 2 ON LPR DMA and peripherals(2) 0.11 µA w/o RTC 0.42 µA w/ RTC 0.03 µA w/o RTC 0.23 µA w/ RTC STM32L496xx Table 4. STM32L496xx modes overview (continued) (1) 15.3 µs 306 µs 1. LPR means Main regulator is OFF and Low-power regulator is ON. 2. All peripherals can be active or clock gated to save power consumption. 3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in LPRun/LPSleep. 4. The flash memory can be put in power-down and its clock can be gated off when executing from SRAM. 5. Theoretical value based on VDD = 3.3 V, DC/DC Efficiency of 85%, VCORE = 1.10 V 6. Theoretical value based on VDD = 3.3 V, DC/DC Efficiency of 85%, VCORE = 1.05 V 7. The SRAM1 and SRAM2 clocks can be gated on or off independently. 8. SMPS mode can be used in STOP0 Mode, but no significant power gain can be expected. 9. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 11. OTG_FS wakeup by resume from suspend and attach detection protocol event. 12. SWPMI1 wakeup by resume from suspend. 13. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. 29/284 Functional overview 10. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. Functional overview STM32L496xx By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. • Low-power sleep mode This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the lowpower run mode. • Stop 0, Stop 1 and Stop 2 modes Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition. Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode. Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption. The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration. • Standby mode The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The brown-out reset (BOR) always remains active in Standby mode. The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating. After entering Standby mode, SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention mode). The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE). The system clock after wakeup is MSI up to 8 MHz. 30/284 DS11585 Rev 16 STM32L496xx • Functional overview Shutdown mode The Shutdown mode permits to achieve the lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported. SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain. The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper). The system clock after wakeup is MSI at 4 MHz. DS11585 Rev 16 31/284 61 Functional overview STM32L496xx Table 5. Functionalities depending on the working mode(1) - - Y - Y - - - - - - - - - - O(2) O(2) O(2) O(2) - - - - - - - - - SRAM1 (256 KB) Y Y(3) Y Y(3) Y - Y - - - - - - SRAM2 (64 KB) Y Y(3) Y Y(3) Y - Y - O(4) - - - - FSMC O O O O - - - - - - - - - Quad SPI O O O O - - - - - - - - - Backup registers Y Y Y Y Y - Y - Y - Y - Y Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - - Programmable voltage detector (PVD) O O O O O O O O - - - - - Peripheral voltage monitor (PVMx; x=1,2,3,4) O O O O O O O O - - - - - DMA O O O O - - - - - - - - - DMA2D O O O O - - - - - - - - - High speed Internal (HSI16) O O O O (5) - (5) - - - - - - Oscillator HSI48 O O - - - - - - - - - - - High speed external (HSE) O O O O - - - - - - - - - Low speed internal (LSI) O O O O O - O - O - - - - Low speed external (LSE) O O O O O - O - O - O - O Multi-Speed internal (MSI) O O O O - - - - - - - - - Clock security system (CSS) O O O O - - - - - - - - - Clock security system on LSE O O O O O O O O O O - - - RTC / Auto wakeup O O O O O O O O O O O O O Peripheral CPU Flash memory (up to 1 MB) 32/284 Run Sleep Lowpower run Lowpower sleep - DS11585 Rev 16 Wakeup capability - Wakeup capability Standby Shutdown Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT STM32L496xx Functional overview Table 5. Functionalities depending on the working mode(1) (continued) - - Number of RTC Tamper pins 3 3 3 3 3 O 3 O 3 O 3 O 3 Camera interface O O O O - - - - - - - - - LCD O O O O O O O O - - - - - - - - O - - - - - - - - - - - - - - Peripheral USB OTG FS Run O (8) Sleep O (8) Lowpower run Lowpower sleep - Wakeup capability - Wakeup capability Standby Shutdown Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT USARTx (x=1,2,3,4,5) O O O O O(6) O(6) Low-power UART (LPUART) O O O O O(6) O(6) O(6) O(6) - - - - - I2Cx (x=1,2,4) O O O O O(7) O(7) - - - - - I2C3 O O O O O(7) O(7) O(7) O(7) - - - - - SPIx (x=1,2,3) O O O O - - - - - - - - - CAN(x=1,2) O O O O - - - - - - - - - SDMMC1 O O O O - - - - - - - - - SWPMI1 O O O O - O - - - - - - - SAIx (x=1,2) O O O O - - - - - - - - - DFSDM1 O O O O - - - - - - - - - ADCx (x=1,2,3) O O O O - - - - - - - - - DAC1 O O O O O - - - - - - - - VREFBUF O O O O O - - - - - - - - OPAMPx (x=1,2) O O O O O - - - - - - - - COMPx (x=1,2) O O O O O O O O - - - - - Temperature sensor O O O O - - - - - - - - - Timers (TIMx) O O O O - - - - - - - - - Low-power timer 1 (LPTIM1) O O O O O O O O - - - - - Low-power timer 2 (LPTIM2) O O O O O O - - - - - - - Independent watchdog (IWDG) O O O O O O O O O O - - - Window watchdog (WWDG) O O O O - - - - - - - - - DS11585 Rev 16 - - 33/284 61 Functional overview STM32L496xx Table 5. Functionalities depending on the working mode(1) (continued) - - SysTick timer O O O O - - - - - - - - - Touch sensing controller (TSC) O O O O - - - - - - - - - Random number generator (RNG) O(8) O(8) - - - - - - - - - - - CRC calculation unit O O O O - - - - - - - - - GPIOs O O O O O O O O (9) 5 pins (11) 5 pins - Peripheral Run Sleep Lowpower run Lowpower sleep - (10) Wakeup capability - Wakeup capability Standby Shutdown Wakeup capability Stop 2 Wakeup capability Stop 0/1 VBAT (10) 1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. 2. The flash can be configured in power-down mode. By default, it is not in power-down mode. 3. The SRAM clock can be gated on or off. 4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register. 5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore. 6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 8. Voltage scaling Range 1 only. 9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. 3.10.5 Reset mode In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal. 3.10.6 VBAT operation The VBAT pin permits to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. The VBAT pin supplies the RTC with LSE and the backup registers. Three anti-tamper detection pins are available in VBAT mode. VBAT operation is automatically activated when VDD is not present. 34/284 DS11585 Rev 16 STM32L496xx Functional overview An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 3.11 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes. Run Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Table 6. STM32L496xx peripherals interconnect matrix TIMx Timers synchronization or chaining Y Y Y Y - - ADCx DAC1 DFSDM1 Conversion triggers Y Y Y Y - - DMA Memory to memory transfer trigger Y Y Y Y - - COMPx Comparator output blanking Y Y Y Y - - IRTIM Infrared interface output generation Y Y Y Y - - TIM1, 8 TIM2, 3 Timer input channel, trigger, break from analog signals comparison Y Y Y Y - - LPTIMERx Low-power timer triggered by analog signals comparison Y Y Y Y Y (1) TIM1, 8 Timer triggered by analog watchdog Y Y Y Y - - TIM16 Timer input channel from RTC events Y Y Y Y - - LPTIMERx Low-power timer triggered by RTC alarms or tampers Y Y Y Y Y (1) All clocks sources (internal TIM2 and external) TIM15, 16, 17 Clock source used as input channel for RC measurement and trimming Y Y Y Y - - USB Timer triggered by USB SOF Y Y - - - - Interconnect source TIMx TIM16/TIM17 COMPx ADCx RTC Interconnect destination TIM2 Interconnect action DS11585 Rev 16 Y Y 35/284 61 Functional overview STM32L496xx Sleep Low-power run Low-power sleep Stop 0 / Stop 1 Stop 2 Interconnect source Run Table 6. STM32L496xx peripherals interconnect matrix (continued) Timer break Y Y Y Y - - TIMx External trigger Y Y Y Y - - LPTIMERx External trigger Y Y Y Y Y (1) ADCx DAC1 DFSDM1 Conversion external trigger Y Y Y Y - - Interconnect destination CSS CPU (hard fault) RAM (parity error) Flash memory (ECC error) TIM1,8 COMPx TIM15,16,17 PVD DFSDM1 (analog watchdog, short circuit detection) GPIO Interconnect action 1. LPTIM1 only. 36/284 DS11585 Rev 16 Y STM32L496xx 3.12 Functional overview Clocks and startup The clock controller (see Figure 5) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler • Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. • Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. • System clock source: four different clock sources can be used to drive the master clock SYSCLK: – 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply a PLL. The HSE can also be configured in bypass mode for an external clock. – 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL – Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the USB device, saving the need of an external high-speed crystal (HSE). The MSI can supply a PLL. – System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency at 80 MHz. • RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48)can be used to drive the USB, the SDMMC or the RNG peripherals. This clock can be output on the MCO. • Auxiliary clock source: two ultralow-power clock sources that can be used to drive the LCD controller and the real-time clock: – 32.768 kHz low-speed external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for an external clock. – 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock accuracy is ±5% accuracy. • Peripheral clock sources: Several peripherals (USB, SDMMC, RNG, SAI, USARTs, I2Cs, LPTimers, ADC, SWPMI) have their own independent clock whatever the system clock. Three PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, the USB/SDMMC/RNG and the two SAIs. • Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software DS11585 Rev 16 37/284 61 Functional overview STM32L496xx interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt. • Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application. Low frequency clocks (LSI, LSE) are available down to Stop 1 low power state. – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes down to Standby mode. LSE can also be output on LSCO in Shutdown mode. LSCO is not available in VBAT mode. Several prescalers permit to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 80 MHz. 38/284 DS11585 Rev 16 STM32L496xx Functional overview Figure 5. Clock tree to IWDG LSI RC 32 kHz LSCO to RTC and LCD OSC32_OUT LSE OSC 32.768 kHz /32 OSC32_IN MCO to PWR LSE LSI MSI HSI16 HSE SYSCLK ĺ to AHB bus, core, memory and DMA AHB PRESC / 1,2,..512 HCLK PLLCLK HSI48 to Cortex system timer /8 Clock source control OSC_OUT HSE OSC 4-48 MHz OSC_IN Clock detector FCLK Cortex free running clock APB1 PRESC / 1,2,4,8,16 PCLK1 to APB1 peripherals HSE x1 or x2 MSI HSI16 SYSCLK LSE HSI16 SYSCLK HSI RC 16 MHz to USARTx x=2..5 to LPUART1 HSI16 SYSCLK to I2Cx x=1,2,3,4 LSI LSE HSI16 MSI RC 100 kHz – 48 MHz to TIMx x=2..7 to LPTIMx x=1,2 HSI16 to SWPMI MSI PLL /M VCO FVCO / P APB2 PRESC / 1,2,4,8,16 HSE PLLSAI3CLK /Q PLL48M1CLK /R PLLCLK PLLSAI1 VCO FVCO / P PCLK2 HSI16 x1 or x2 to TIMx x=1,8,15,16,17 LSE HSI16 SYSCLK PLLSAI1CLK /Q PLL48M2CLK /R PLLADC1CLK MSI to USART1 48 MHz clock to USB, RNG, SDMMC SYSCLK HSI RC 48MHz SYSCLK to DFSDM1 PLLSAI2CLK /Q /R to ADC HSI48 CRS PLLSAI2 VCO FVCO / P to APB2 peripherals to SAI1 PLLADC2CLK SAI1_EXTCLK to SAI2 SAI2_EXTCLK MS50063V1 DS11585 Rev 16 39/284 61 Functional overview 3.13 STM32L496xx General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 3.14 Direct memory access controller (DMA) The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features implementation. Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The two DMA controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests. The DMA supports: • 14 independently configurable channels (requests) • Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (example: request 1 has priority over request 2) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. • Support for circular buffer management • 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers • Access to flash, SRAM, APB and AHB peripherals as source and destination • Programmable number of data to be transferred: up to 65536. Table 7. DMA implementation 40/284 DMA features DMA1 DMA2 Number of regular channels 7 7 DS11585 Rev 16 STM32L496xx 3.15 Functional overview Chrom-ART Accelerator™ (DMA2D) The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions: • Rectangle filling with a fixed color • Rectangle copy • Rectangle copy with pixel format conversion • Rectangle composition with blending and pixel format conversion. Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables. An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automatized and are running independently from the CPU or the DMAs. 3.16 Interrupts and events 3.16.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 90 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4. The NVIC benefits are the following: • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail chaining • Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.16.2 Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 41 edge detector lines used to generate interrupt/event requests and wake-up the system from Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 136 GPIOs can be connected to the 16 external interrupt lines. DS11585 Rev 16 41/284 61 Functional overview 3.17 STM32L496xx Analog to digital converter (ADC) The device embeds 3 successive approximation analog-to-digital converters with the following features: • 12-bit native resolution, with built-in calibration • 5.33 Msps maximum conversion rate with full resolution Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit resolution) • Up to 24 external channels, some of them shared between ADC1 and ADC2, or ADC1, ADC2 and ADC3. • 5 internal channels: internal reference voltage, temperature sensor, VBAT/3, DAC1_OUT1 and DAC1_OUT2. • One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply • Single-ended and differential mode inputs • Low-power design • 3.17.1 – – Capable of low-current operation at low conversion rate (consumption decreases linearly with speed) – Dual clock domain architecture: ADC speed independent from CPU frequency Highly versatile digital interface – Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions – Handles two ADC converters for dual mode operation (simultaneous or interleaved sampling modes) – Each ADC support multiple trigger inputs for synchronization with on-chip timers and external signals – Results stored into 3 data register or in RAM with DMA controller support – Data pre-processing: left/right alignment and per channel offset compensation – Built-in oversampling unit for enhanced SNR – Channel-wise programmable sampling time – Three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers – Hardware assistant to prepare the context of the injected channels to allow fast context switching Temperature sensor The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN17 and ADC3_IN17 input channels which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. 42/284 DS11585 Rev 16 STM32L496xx Functional overview To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 8. Temperature sensor calibration values 3.17.2 Calibration value name Description Memory address TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75A8 - 0x1FFF 75A9 TS_CAL2 TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75CA - 0x1FFF 75CB Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 9. Internal voltage reference calibration values 3.17.3 Calibration value name Description Memory address VREFINT Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV) 0x1FFF 75AA - 0x1FFF 75AB VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN18 or ADC3_IN18. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third the VBAT voltage. 3.18 Digital to analog converter (DAC) Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. DS11585 Rev 16 43/284 61 Functional overview STM32L496xx This digital interface supports the following features: • Up to two DAC output channels • 8-bit or 12-bit output mode • Buffer offset calibration (factory and user trimming) • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Sample and hold low-power mode, with internal or external capacitor The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.19 Voltage reference buffer (VREFBUF) The STM32L496xx devices embed an voltage reference buffer which can be used as voltage reference for ADCs, DAC and also as voltage reference for external components through the VREF+ pin. The internal voltage reference buffer supports two voltages: • 2.048 V • 2.5 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available. Figure 6. Voltage reference buffer VREFBUF VDDA Bandgap + DAC, ADC VREF+ Low frequency cut-off capacitor 100 nF MSv40197V1 44/284 DS11585 Rev 16 STM32L496xx 3.20 Functional overview Comparators (COMP) The STM32L496xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity. The reference voltage can be one of the following: • External I/O • DAC output channels • Internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. 3.21 Operational amplifier (OPAMP) The STM32L496xx embeds two operational amplifiers with external or internal follower routing and PGA capability. The operational amplifier features: 3.22 • Low input bias current • Low offset voltage • Low-power mode • Rail-to-rail input Touch sensing controller (TSC) The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (such as glass or plastic). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application. DS11585 Rev 16 45/284 61 Functional overview STM32L496xx The main features of the touch sensing controller are the following: • Proven and robust surface charge transfer acquisition principle • Supports up to 24 capacitive sensing channels • Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time • Spread spectrum feature to improve system robustness in noisy environments • Full hardware management of the charge transfer acquisition sequence • Programmable charge transfer frequency • Programmable sampling capacitor I/O pin • Programmable channel I/O pin • Programmable max count value to avoid long acquisition when a channel is faulty • Dedicated end of acquisition and max count error flags with interrupt capability • One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components • Compatible with proximity, touchkey, linear and rotary touch sensor implementation • Designed to operate with STMTouch touch sensing firmware library Note: The number of capacitive sensing channels is dependent on the size of the packages and subject to I/O availability. 3.23 Liquid crystal display controller (LCD) The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels. 3.24 • Internal step-up converter to guarantee functionality and contrast control irrespective of VDD. This converter can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD • Supports static, 1/2, 1/3, 1/4 and 1/8 duty • Supports static, 1/2, 1/3 and 1/4 bias • Phase inversion to reduce power consumption and EMI • Integrated voltage output buffers for higher LCD driving capability • Up to 8 pixels can be programmed to blink • Unneeded segments and common pins can be used as general I/O pins • LCD RAM can be updated at any time owing to a double-buffer • The LCD controller can operate in Stop mode Digital filter for Sigma-Delta modulators (DFSDM) The device embeds one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in 46/284 DS11585 Rev 16 STM32L496xx Functional overview hardware. DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM or from internal ADCs). DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution. The DFSDM peripheral supports: • • 8 multiplexed input digital serial channels: – configurable SPI interface to connect various SD modulator(s) – configurable Manchester coded 1 wire interface support – PDM (Pulse Density Modulation) microphone input support – maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) – clock output for SD modulator(s): 0..20 MHz alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution): – • internal sources: ADCs data or device memory data streams (DMA) 4 digital filter modules with adjustable digital signal processing: – Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024) – integrator: oversampling ratio (1..256) • up to 24-bit output data resolution, signed output data format • automatic data offset correction (offset stored in register by user) • continuous or single conversion • start-of-conversion triggered by: • • – software trigger – internal timers – external events – start-of-conversion synchronously with first digital filter module (DFSDM1_FLT0) analog watchdog feature: – low value and high value data threshold registers – dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) – input from final output data or from selected input digital serial channels – continuous monitoring independently from standard conversion short circuit detector to detect saturated analog input values (bottom and top range): – up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream – monitoring continuously each input serial channel • break signal generation on analog watchdog event or on short circuit detector event • extremes detector: – storage of minimum and maximum values of final conversion data – refreshed by software • DMA capability to read the final conversion data • interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence • “regular” or “injected” conversions: – “regular” conversions can be requested at any time or even in continuous mode DS11585 Rev 16 47/284 61 Functional overview STM32L496xx without having any impact on the timing of “injected” conversions – 3.25 “injected” conversions for precise timing and with high conversion priority True random number generator (RNG) The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component. 3.26 Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features: 3.27 • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8-, 10-, 12- or 14-bit • Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode • Capability to automatically crop the image Timers and watchdogs The STM32L496xx includes two advanced control timers, up to nine general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers. Table 10. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Advanced control TIM1, TIM8 16-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 3 Generalpurpose TIM2, TIM5 32-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM3, TIM4 16-bit Up, down, Up/down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 1 48/284 DS11585 Rev 16 STM32L496xx Functional overview Table 10. Timer feature comparison (continued) Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Generalpurpose TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.27.1 Advanced-control timer (TIM1, TIM8) The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge or center-aligned modes) with full modulation capability (0100%) • One-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIMx timers (described in Section 3.27.2) using the same architecture, so the advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. DS11585 Rev 16 49/284 61 Functional overview 3.27.2 STM32L496xx General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17) There are up to seven synchronizable general-purpose timers embedded in the STM32L496xx (see Table 10 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. • TIM2, TIM3, TIM4 and TIM5 They are full-featured general-purpose timers: – TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler – TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler. These timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining. The counters can be frozen in debug mode. All have independent DMA request generation and support quadrature encoders. • TIM15, 16 and 17 They are general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. – TIM15 has 2 channels and 1 complementary channel – TIM16 and TIM17 have 1 channel and 1 complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode. 3.27.3 Basic timers (TIM6 and TIM7) The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases. 3.27.4 Low-power timer (LPTIM1 and LPTIM2) The devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode. LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes. LPTIM2 is active in Stop 0 and Stop 1 mode. 50/284 DS11585 Rev 16 STM32L496xx Functional overview This low-power timer supports the following features: 3.27.5 • 16-bit up counter with 16-bit autoreload register • 16-bit compare register • Configurable output: pulse, PWM • Continuous/ one shot mode • Selectable software/hardware input trigger • Selectable clock source – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application). • Programmable digital glitch filter • Encoder mode (LPTIM1 only) Infrared interface (IRTIM) The STM32L496xx includes one infrared interface (IRTIM), which can be used with an infrared LED to perform remote control functions. It uses TIM16 and TIM17 output channels to generate output signal waveforms on IR_OUT pin. 3.27.6 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.27.7 System window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.27.8 SysTick timer This timer is dedicated to real-time operating systems, but can also be used as a standard down counter. It features: • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source DS11585 Rev 16 51/284 61 Functional overview 3.28 STM32L496xx Real-time clock (RTC) and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. • Three anti-tamper detection pins with programmable filter. • Timestamp feature, which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. • 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode. The RTC clock sources can be: • A 32.768 kHz external crystal (LSE) • An external resonator or oscillator (LSE) • The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) • The high-speed external clock (HSE) divided by 32. The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode. All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 52/284 DS11585 Rev 16 STM32L496xx 3.29 Functional overview Inter-integrated circuit interface (I2C) The device embeds four I2C. Refer to Table 11 for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. Refer to Figure 5: Clock tree. • Wakeup from Stop mode on address match • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 11. I2C implementation I2C features(1) I2C1 I2C2 I2C3 I2C4 Standard-mode (up to 100 kbit/s) X X X X Fast-mode (up to 400 kbit/s) X X X X Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X X Programmable analog and digital noise filters X X X X SMBus/PMBus hardware support X X X X Independent clock X X X X Wakeup from Stop0, Stop 1 mode on address match X X X X Wakeup from Stop 2 mode on address match - - X - 1. X: supported DS11585 Rev 16 53/284 61 Functional overview 3.30 STM32L496xx Universal synchronous/asynchronous receiver transmitter (USART) The STM32L496xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4, UART5). These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable, and are able to communicate at speeds of up to 10 Mbit/s. USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All USART have a clock domain independent from the CPU clock, allowing the USARTx (x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame All USART interfaces can be served by the DMA controller. Table 12. STM32L496xx USART/UART/LPUART features USART modes/features(1) USART1 USART2 USART3 UART4 UART5 LPUART1 Hardware flow control for modem X X X X X X Continuous communication using DMA X X X X X X Multiprocessor communication X X X X X X Synchronous mode X X X - - - Smartcard mode X X X - - - Single-wire half-duplex communication X X X X X X IrDA SIR ENDEC block X X X X X - LIN mode X X X X X - Dual clock domain X X X X X X Wakeup from Stop 0 / Stop 1 modes X X X X X X Wakeup from Stop 2 mode - - - - - X Receiver timeout interrupt X X X X X - Modbus communication X X X X X - Auto baud rate detection Driver Enable X (4 modes) X X LPUART/USART data length X 7, 8 and 9 bits 1. X = supported. 54/284 X - DS11585 Rev 16 X X STM32L496xx 3.31 Functional overview Low-power universal asynchronous receiver transmitter (LPUART) The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication. The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop mode are programmable and can be: • Start bit detection • Any received data frame • A specific programmed data frame Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. LPUART interface can be served by the DMA controller. DS11585 Rev 16 55/284 61 Functional overview 3.32 STM32L496xx Serial peripheral interface (SPI) Three SPI interfaces allow communication up to 40 Mbits/s in master and slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation. All SPI interfaces can be served by the DMA controller. 3.33 Serial audio interfaces (SAI) The device embeds 2 SAI. Refer to Table 13 for the features implementation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol. The SAI peripheral supports: • Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. • 8-word integrated FIFOs for each audio sub-block. • Synchronous or asynchronous mode between the audio sub-blocks. • Master or slave configuration independent for both audio sub-blocks. • Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode. • Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit. • Peripheral with large configurability and flexibility permitting to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out. • Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame. • Number of bits by frame may be configurable. • Frame synchronization active level configurable (offset, bit length, level). • First active bit position in the slot is configurable. • LSB first or MSB first for data transfer. • Mute mode. • Stereo/Mono audio frame capability. • Communication clock strobing edge configurable (SCK). • Error flags with associated interrupts if enabled respectively. • • 56/284 – Overrun and underrun detection. – Anticipated frame synchronization signal detection in slave mode. – Late frame synchronization signal detection in slave mode. – Codec not ready for the AC’97 mode in reception. Interruption sources when enabled: – Errors. – FIFO requests. DMA interface with 2 dedicated channels to handle access to the dedicated integrated FIFO of each SAI audio sub-block. DS11585 Rev 16 STM32L496xx Functional overview Table 13. SAI implementation SAI features(1) SAI1 SAI2 I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X Mute mode X X Stereo/Mono audio frame capability. X X 16 slots X X Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X X (8 words) X (8 words) X X FIFO size SPDIF 1. X: supported 3.34 Single wire protocol master interface (SWPMI) The Single wire protocol master interface (SWPMI) is the master interface corresponding to the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are: • full-duplex communication mode • automatic SWP bus state management (active, suspend, resume) • configurable bitrate up to 2 Mbit/s • automatic SOF, EOF and CRC handling SWPMI can be served by the DMA controller. 3.35 Controller area network (CAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN. DS11585 Rev 16 57/284 61 Functional overview STM32L496xx Dual CAN peripheral configuration is available. The CAN peripheral supports: • Supports CAN protocol version 2.0 A, B Active • Bit rates up to 1 Mbit/s • Transmission • • • 3.36 – Three transmit mailboxes – Configurable transmit priority Reception – Two receive FIFOs with three stages – Scalable filter banks: 28 filter banks shared between CAN1 and CAN2 – Identifier list feature – Configurable FIFO overrun Time-triggered communication option – Disable automatic retransmission mode – 16-bit free running timer – Time Stamp sent in last two data bytes Management – Maskable interrupts – Software-efficient mailbox mapping at a unique address space Secure digital input/output and MultiMediaCards interface (SDMMC) The card host interface (SDMMC) provides an interface between the APB peripheral bus and MultiMediaCards (MMCs), SD memory cards and SDIO cards. The SDMMC features include the following: 3.37 • Full compliance with MultiMediaCard System Specification Version 4.2. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit • Full compatibility with previous versions of MultiMediaCards (forward compatibility) • Full compliance with SD Memory Card Specifications Version 2.0 • Full compliance with SD I/O Card Specification Version 2.0: card support for two different databus modes: 1-bit (default) and 4-bit • Data transfer up to 48 MHz for the 8 bit mode • Data write and read with DMA capability Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz external oscillator (LSE).This permits to use the USB device without external high speed crystal (HSE). 58/284 DS11585 Rev 16 STM32L496xx Functional overview The synchronization for this oscillator can also be taken from the USB data stream itself (SOF signalization) which allows crystal less operation. The major features are: • Combined Rx and Tx FIFO size of 1.25 KB with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints • 12 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • USB 2.0 LPM (Link Power Management) support • Battery Charging Specification Revision 1.2 support • Internal FS OTG PHY support For OTG/Host modes, a power switch is needed in case bus-powered devices are connected. 3.38 Clock recovery system (CRS) The STM32L496xx devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action. 3.39 Flexible static memory controller (FSMC) The Flexible static memory controller (FSMC) includes two memory controllers: • The NOR/PSRAM memory controller • The NAND/memory controller This memory controller is also named Flexible memory controller (FMC). The main features of the FMC controller are the following: • Interface with static-memory mapped devices including: – Static random access memory (SRAM) – NOR flash memory/OneNAND flash memory – PSRAM (4 memory banks) – NAND flash memory with ECC hardware to check up to 8 Kbyte of data • 8-,16- bit data bus width • Independent Chip Select control for each memory bank • Independent configuration for each memory bank • Write FIFO • The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2. DS11585 Rev 16 59/284 61 Functional overview STM32L496xx LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. For WLCSP100L package, address lines [A18:A16] are missing versus other 100 pin packages, thus FMC provides only 2MB of addressable space, split into 64K blocks. The main usage of the FMC in this case is to drive external LCD interface. 3.40 Dual-flash Quad SPI memory interface (QUADSPI) The Dual-flash Quad SPI is a specialized communication interface targeting single, dual or quad SPI flash memories. It can operate in any of the three following modes: • Indirect mode: all the operations are performed using the QUADSPI registers • Status polling mode: the external flash memory status register is periodically read and an interrupt can be generated in case of flag setting • Memory-mapped mode: the external flash is memory mapped and is seen by the system as if it were an internal memory Both throughput and capacity can be increased two-fold using dual-flash mode, where two Quad SPI flash memories are accessed simultaneously. The Dual-flash Quad SPI interface supports: 60/284 • Three functional modes: indirect, status-polling, and memory-mapped • Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two flash memories in parallel. • SDR and DDR support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode • Each of the five following phases can be configured independently (enable, length, single/dual/quad communication) – Instruction phase – Address phase – Alternate bytes phase – Dummy cycles phase – Data phase • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • DMA channel for indirect mode operations • Programmable masking for external flash flag management • Timeout management • Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error DS11585 Rev 16 STM32L496xx Functional overview 3.41 Development support 3.41.1 Serial wire JTAG debug port (SWJ-DP) The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins can be reused as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.41.2 Embedded Trace Macrocell™ The Arm® Embedded Trace Macrocell™ provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L496xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell™ operates with third party debugger software tools. DS11585 Rev 16 61/284 61 Pinouts and pin description 4 STM32L496xx Pinouts and pin description Figure 7. STM32L496Ax UFBGA169 pinout(1)(2) 1 2 3 4 5 6 7 8 9 10 11 12 13 A PI10 PH2 VDD PE0 PB4 PB3 VSS VDD PA15 PA14 PA13 PI0 PH14 B PI9 PI7 VSS PE1 PB5 VDDIO2 PG9 PD0 PI6 PI2 PI1 PH15 PH12 C VDD VSS PI11 PB8 PB6 PG15 PD4 PD1 PH13 PI3 PI8 VSS VDD D PE4 PE3 PE2 PB9 PB7 PG10 PD5 PD2 PC10 PI4 PH9 PH7 PA12 E PC13 VBAT PE6 PE5 PH3-BOOT0 PG11 PD6 PD3 PC11 PI5 PH6 VDDUSB PA11 F PC14OSC32_IN VSS PF2 PF1 PF0 PG12 PD7 PC12 PA10 PA9 PC6 VDDIO2 VSS G PC15OSC32_OUT VDD PF3 PF4 PF5 PG14 PG13 PA8 PC9 PC8 PG6 PC7 VDD H PH0-OSC_IN VSS NRST PF10 PC4 PG1 PE10 PB11 PG8 PG7 PD15 VSS VDD J PH1OSC_OUT PC0 PC1 PC2 PC5 PG0 PE9 PE15 PG5 PG4 PG3 PG2 PD10 K PC3 VSSA/VREF- PA0 PA5 PB0 PF15 PE8 PE14 PH4 PD14 PD12 PD11 PD13 L VREF+ VDDA PA4 PA7 PB1 PF14 PE7 PE13 PH5 PD9 PD8 VDD VSS M OPAMP1_VI NM PA3 VSS PA6 PF11 PF13 VSS PE12 PH10 PH11 VSS PB15 PB14 N PA2 PA1 VDD OPAMP2_VI NM PB2 PF12 VDD PE11 PB10 PH8 VDD PB12 PB13 MSv38036V5 1. The above figure shows the package top view. 2. The I/O pins supplied by VDDIO2 are shown in gray. 62/284 DS11585 Rev 16 STM32L496xx Pinouts and pin description Figure 8. STM32L496Ax, external SMPS device, UFBGA169 pinout(1)(2) 1 2 3 4 5 6 7 8 9 10 11 12 13 A PI10 PH2 VDD PE0 PB4 PB3 VSS VDD PA15 PA14 PA13 PI0 PH14 B PI9 PI7 VSS PE1 PB5 VDDIO2 PG9 PD0 PI6 PI2 PI1 PH15 PH12 C VDD VSS PI11 PB8 PB6 VDD12 PD4 PD1 PH13 PI3 PI8 VSS VDD D PE4 PE3 PE2 PB9 PB7 PG10 PD5 PD2 PC10 PI4 PH9 PH7 PA12 E PC13 VBAT PE6 PE5 PH3-BOOT0 PG11 PD6 PD3 PC11 PI5 PH6 VDDUSB PA11 F PC14OSC32_IN VSS PF2 PF1 PF0 PG12 PD7 PC12 PA10 PA9 PC6 VDDIO2 VSS G PC15OSC32_OUT VDD PF3 PF4 PF5 PG14 PG13 PA8 PC9 PC8 PG6 PC7 VDD H PH0-OSC_IN VSS NRST PF10 PC4 PG1 PE10 PB11 PG8 PG7 PD15 VSS VDD J PH1OSC_OUT PC0 PC1 PC2 PC5 PG0 PE9 PE15 PG5 PG4 PG3 PG2 PD10 K PC3 VSSA/VREF- PA0 PA5 PB0 PF15 PE8 PE14 PH4 PD14 PD12 PD11 PD13 L VREF+ VDDA PA4 PA7 PB1 PF14 PE7 PE13 PH5 PD9 PD8 VDD VSS M OPAMP1_VI NM PA3 VSS PA6 PF11 PF13 VSS PE12 PH10 VDD12 VSS PB15 PB14 N PA2 PA1 VDD OPAMP2_VI NM PB2 PF12 VDD PE11 PB10 PH8 VDD PB12 PB13 MSv42235V2 1. The above figure shows the package top view. 2. The I/O pins supplied by VDDIO2 are shown in gray. DS11585 Rev 16 63/284 119 Pinouts and pin description STM32L496xx VDD VSS PE1 PE0 PB9 PB8 PH3-BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDDIO2 VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 Figure 9. STM32L496Zx LQFP144 pinout(1)(2) PE2 PE3 PE4 PE5 1 2 3 4 108 VDD 107 VSS 106 VDDUSB 105 PA13 PE6 5 104 PA12 VBAT 6 103 PA11 PC13 7 PC14-OSC32_IN 8 102 101 PA10 PA9 PC15-OSC32_OUT 9 100 PA8 PF0 10 99 PC9 PF1 11 PF2 12 98 97 PC8 PC7 PF3 13 96 PC6 PF4 14 95 VDDIO2 PF5 15 94 VSS VSS 16 93 PG8 VDD 17 92 PG7 PF6 18 91 PG6 PF7 19 90 PG5 PF8 20 89 PG4 PF9 21 88 PG3 PF10 22 87 PG2 PH0-OSC_IN 23 86 PD15 PH1-OSC_OUT 24 85 PD14 NRST 25 84 VDD PC0 26 83 VSS PC1 27 82 PD13 PC2 28 81 PD12 PC3 29 80 PD11 VSSA 30 79 PD10 VREF- 31 78 PD9 VREF+ 32 77 PD8 VDDA 33 76 PB15 PA0 34 75 PB14 PA1 35 74 PB13 PA2 36 73 PB12 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS VDD LQFP144 MSv38033V5 1. The above figure shows the package top view. 2. The I/O pins supplied by VDDIO2 are shown in gray. 64/284 DS11585 Rev 16 STM32L496xx Pinouts and pin description VDD VSS VDD12 PE1 PE0 PB9 PB8 PH3-BOOT0 PB7 PB6 PB5 PB4 PB3 VDDIO2 VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 Figure 10. STM32L496Zx, external SMPS device, LQFP144 pinout(1)(2) PE2 PE3 PE4 PE5 1 2 3 4 108 VDD 107 VSS 106 VDDUSB 105 PA13 PE6 5 104 PA12 VBAT 6 103 PA11 PC13 7 PC14-OSC32_IN 8 102 101 PA10 PA9 PC15-OSC32_OUT 9 100 PA8 PF0 10 99 PC9 PF1 11 PF2 12 98 97 PC8 PC7 PF3 13 96 PC6 PF4 14 95 VDDIO2 PF5 15 94 VSS VSS 16 93 PG8 VDD 17 92 PG7 PF6 18 91 PG6 PF7 19 90 PG5 PF8 20 89 PG4 PF9 21 88 PG3 PF10 22 87 PG2 PH0-OSC_IN 23 86 PD15 PH1-OSC_OUT 24 85 PD14 NRST 25 84 VDD PC0 26 83 VSS PC1 27 82 PD13 PC2 28 81 PD12 PC3 29 80 PD11 VSSA 30 79 PD10 VREF- 31 78 PD9 VREF+ 32 77 PD8 VDDA 33 76 PB15 PA0 34 75 PB14 PA1 35 74 PB13 PA2 36 73 PB12 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 VDD12 VSS VDD LQFP144 MSv42236V2 1. The above figure shows the package top view. 2. The I/O pins supplied by VDDIO2 are shown in gray. DS11585 Rev 16 65/284 119 Pinouts and pin description STM32L496xx Figure 11. STM32L496Qx UFBGA132 ballout(1)(2) 1 2 3 4 5 6 7 8 9 10 11 12 A PE3 PE1 PB8 PH3-BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12 B PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11 C PC13 PE5 PE0 VDD PB5 PG14 PG13 PD2 PD0 PC11 VDDUSB PA10 D PC14OSC32_IN PE6 VSS PF2 PF1 PF0 PG12 PG10 PG9 PA9 PA8 PC9 E PC15OSC32_OUT VBAT VSS PF3 PG5 PC8 PC7 PC6 F PH0-OSC_IN VSS PF4 PF5 VSS VSS PG3 PG4 VSS VSS G PH1OSC_OUT VDD PG11 PG6 VDD VDDIO2 PG1 PG2 VDD VDD H PC0 NRST VDD PG7 PG0 PD15 PD14 PD13 J VSSA/VREF- PC1 PC2 PA4 PA7 PG8 PF12 PF14 PF15 PD12 PD11 PD10 K PG15 PC3 PA2 PA5 PC4 PF11 PF13 PD9 PD8 PB15 PB14 PB13 L VREF+ PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 PB11 PB12 M VDDA PA1 OPAMP1_ VINM OPAMP2_ VINM PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15 MSv38035V3 1. The above figure shows the package top view. 2. The I/O pins supplied by VDDIO2 are shown in gray. Figure 12. STM32L496Qx, external SMPS device, UFBGA132 ballout(1)(2) 1 2 3 4 5 6 7 8 9 10 11 12 A PE3 PE1 PB8 PH3-BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12 B PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11 C PC13 PE5 PE0 VDD PB5 VDD12 PG13 PD2 PD0 PC11 VDDUSB PA10 D PC14OSC32_IN PE6 VSS PF2 PF1 PF0 PG12 PG10 PG9 PA9 PA8 PC9 E PC15OSC32_OUT VBAT VSS PF3 PG5 PC8 PC7 PC6 F PH0-OSC_IN VSS PF4 PF5 VSS VSS PG3 PG4 VSS VSS G PH1OSC_OUT VDD PG11 PG6 VDD VDDIO2 PG1 PG2 VDD VDD H PC0 NRST VDD PG7 PG0 PD15 PD14 PD13 J VSSA/VREF- PC1 PC2 PA4 PA7 PG8 PF12 PF14 PF15 PD12 PD11 PD10 K PG15 PC3 PA2 PA5 PC4 PF11 PF13 PD9 PD8 PB15 PB14 PB13 L VREF+ PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 VDD12 PB12 PA1 OPAMP1_ VINM OPAMP2_ VINM PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15 M VDDA MS46960V2 1. The above figure shows the package top view. 2. The I/O pins supplied by VDDIO2 are shown in gray. 66/284 DS11585 Rev 16 STM32L496xx Pinouts and pin description Figure 13. STM32L496Wx, external SMPS device, WLCSP115 ballout(1)(2) 1 A B PA22 C D L 5 PD15 PD8 VDD VDD 12 PD9 PB14 PB13 PB10 PB12 PE12 PE14 PB11 PE15 PE11 PE8 PA0 PC3 VDD PB1 PH0 PH1 PA7 PC1 V REFP VSSA PC4 VDD VDD PA5 VSS PC14 VSS PC2 PA6 PB0 PE7 PE5 VBAT PE6 PC0 PA1 21 VDD VSS PA2 PB2 20 PE3 PC13 NRST PC5 19 PE4 PH3 PG0 PE10 VDD 12 PB6 PB3 18 VSS PE2 PG13 PE9 17 PB9 PB7 PG1 PE13 16 PB4 PD6 PG6 15 PB5 PG9 PC6 PG2 14 VDD IO2 PD7 PD4 PG7 13 PG12 PC12 PG3 12 PG14 PG11 PA10 PD10 11 PD5 PA14 PG8 VSS 10 PG10 PD0 PC9 PG4 PD14 9 VSS PA15 PA13 VSS 8 VDD PD1 PC8 PG5 7 PC10 PA8 VDD IO2 6 PD2 VDD USB PC7 J K 4 PC11 VSS PA9 G H 3 PA11 E F 2 VDD VSS PA4 VDDA PA0 MSv53553V2 1. The above figure shows the package top view. 2. The I/O pins supplied by VDDIO2 are shown in gray. VDD VSS PE1 PE0 PB9 PB8 PH3-BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Figure 14. STM32L496Vx LQFP100 pinout(1) PE2 1 75 VDD PE3 2 74 VSS PE4 3 73 VDDUSB PE5 4 72 PA13 PE6 5 71 PA12 VBAT 6 70 PA11 PC13 7 69 PA10 PC14-OSC32_IN 8 68 PA9 PC15-OSC32_OUT 9 67 PA8 VSS 10 66 PC9 VDD 11 65 PC8 PH0-OSC_IN 12 64 PC7 PH1-OSC_OUT 13 63 PC6 NRST 14 62 PD15 PC0 15 61 PD14 PC1 16 60 PD13 PC2 17 59 PD12 PC3 18 58 PD11 VSSA 19 57 PD10 VREF- 20 56 PD9 VREF+ 21 55 PD8 VDDA 22 54 PB15 PA0 23 53 PB14 PA1 24 52 PB13 PA2 25 51 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS VDD LQFP100 MSv38034V2 1. The above figure shows the package top view. DS11585 Rev 16 67/284 119 Pinouts and pin description STM32L496xx VDD VSS VDD12 PE0 PB9 PB8 PH3-BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Figure 15. STM32L496Vx, external SMPS device, LQFP100 pinout(1) PE2 1 75 VDD PE3 2 74 VSS PE4 3 73 VDDUSB PE5 4 72 PA13 PE6 5 71 PA12 VBAT 6 70 PA11 PC13 7 69 PA10 PC14-OSC32_IN 8 68 PA9 PC15-OSC32_OUT 9 67 PA8 VSS 10 66 PC9 VDD 11 65 PC8 PH0-OSC_IN 12 64 PC7 PH1-OSC_OUT 13 63 PC6 NRST 14 62 PD15 PC0 15 61 PD14 PC1 16 60 PD13 PC2 17 59 PD12 PC3 18 58 PD11 VSSA 19 57 PD10 VREF- 20 56 PD9 VREF+ 21 55 PD8 VDDA 22 54 PB15 PA0 23 53 PB14 PA1 24 52 PB13 PA2 25 51 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 VDD12 VSS VDD LQFP100 1. The above figure shows the package top view. 68/284 DS11585 Rev 16 MS51413V1 STM32L496xx Pinouts and pin description Figure 16. STM32L496Vx WLCSP100L pinout(1)(2) 1 2 3 4 5 6 7 8 9 10 A VDDUSB PA15 PD1 VDD PG10 VDDIO2 PB6 PB9 VSS VDD B VSS PA14 PD0 PD4 PG9 PG12 PB5 PB8 PE2 PE3 C PA12 PA13 PC11 PC12 PD7 PB3 PB4 PE4 PC13 VBAT D PA11 PA10 PA9 PC10 PD6 PG11 PB7 PE5 VSS PC14OSC32_IN E PC8 PC9 PA8 PD2 PD5 PH3-BOOT0 PE6 NRST VDD PC15OSC32_OUT F VDD PC6 PC7 PD15 PB2 PA4 PC3 PC1 PC0 PH0-OSC_IN G PD10 PD9 PD14 PE13 PE12 PA5 VREF+ VREF- PA0 PH1OSC_OUT H PB15 PB14 PD8 PE15 PE10 PC4 PA2 PA1 VSSA PC2 J PB12 PB13 PB11 PE14 PE9 PB0 PA7 VDD PA3 VDDA K VDD VSS PB10 PE11 PE8 PE7 PB1 PC5 PA6 VSS MS50090V2 1. The above figure shows the package top view. 2. The I/O pins supplied by VDDIO2 are shown in gray. Figure 17. STM32L496Vx, external SMPS device, WLCSP100L pinout(1)(2) 1 2 3 4 5 6 7 8 9 10 A VDDUSB PA15 PD1 VDD PG10 VDDIO2 PB6 PB9 VDD12 VDD B VSS PA14 PD0 PD5 PD6 PG12 PB7 PB8 VSS PE3 C PA12 PA13 PC10 PC12 PD4 PD7 PB5 PE2 PC13 VBAT PC14OSC32_IN D PA11 PA10 PA9 PC11 PD2 PG9 PH3-BOOT0 PE6 PC15OSC32_OUT E PC8 PC9 PA8 PC7 PG11 PB4 PE4 PE5 VDD VSS F VDD PD15 PD14 PC6 PB3 PC3 PC1 NRST PH1OSC_OUT PH0-OSC_IN G PD10 PD9 PD8 PE14 PE13 PA7 PA1 PA0 PC2 PC0 H PB14 PB13 PB15 PE15 PE10 PB0 PA4 PA2 VSSA/VREF- VREF+ J PB12 VDD PB11 PE12 PE9 PB2 PA5 VDD PA3 VDDA K VDD12 VSS PB10 PE11 PE8 PE7 PB1 PC4 PA6 VSS MS50091V2 1. The above figure shows the package top view. 2. The I/O pins supplied by VDDIO2 are shown in gray. DS11585 Rev 16 69/284 119 Pinouts and pin description STM32L496xx VDD VSS PB9 PB8 PH3-BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Figure 18. STM32L496Rx LQFP64 pinout(1) VBAT 1 48 VDDUSB PC13 2 47 VSS PC14-OSC32_IN 3 46 PA13 PC15-OSC32_OUT 4 45 PA12 PH0-OSC_IN 5 44 PA11 PH1-OSC_OUT 6 43 PA10 NRST 7 42 PA9 PC0 8 41 PA8 PC1 9 40 PC9 PC2 10 39 PC8 PC3 11 38 PC7 VSSA/VREF- 12 37 PC6 VDDA/VREF+ 13 36 PB15 PA0 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS VDD LQFP64 MS38433V2 1. The above figure shows the package top view. VDD VSS VDD12 PB9 PB8 PH3-BOOT0 PB7 PB6 PB5 PB4 PB3 PC12 PC11 PC10 PA15 PA14 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Figure 19. STM32L496Rx, external SMPS, LQFP64 pinout(1) VBAT 1 48 VDDUSB PC13 2 47 VSS PC14-OSC32_IN 3 46 PA13 PC15-OSC32_OUT 4 45 PA12 PH0-OSC_IN 5 44 PA11 PH1-OSC_OUT 6 43 PA10 NRST 7 42 PA9 PC0 8 41 PA8 PC1 9 40 PC9 PC2 10 39 PC8 PC3 11 38 PC7 VSSA/VREF- 12 37 PC6 VDDA/VREF+ 13 36 PB15 PA0 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 25 26 27 28 29 30 31 32 PB1 PB2 PB10 PB11 VDD12 VSS VDD 22 PA6 PB0 21 PA5 24 20 PA4 23 19 VDD PA7 18 PC4 17 PA3 VSS QFx64 1. The above figure shows the package top view. 70/284 DS11585 Rev 16 MS51414V1 STM32L496xx Pinouts and pin description Table 14. Legend/abbreviations used in the pinout table Name Pin name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin Pin type I/O Input / output pin FT 5 V tolerant I/O TT 3.6 V tolerant I/O RST Bidirectional reset pin with embedded weak pull-up resistor Option for TT or FT I/Os I/O structure _f (1) I/O, Fm+ capable _l (2) I/O, with LCD function supplied by VLCD _u (3) I/O, with USB function supplied by VDDUSB _a (4) I/O, with Analog switch function supplied by VDDA _s (5) Notes I/O supplied only by VDDIO2 Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset. Alternate Functions selected through GPIOx_AFR registers functions Pin functions Additional Functions directly selected/enabled through peripheral registers functions 1. The related I/O structures in Table 15 are: FT_f, FT_fa, FT_fl, FT_fla. 2. The related I/O structures in Table 15 are: FT_l, FT_fl, FT_lu. 3. The related I/O structures in Table 15 are: FT_u, FT_lu. 4. The related I/O structures in Table 15 are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la. 5. The related I/O structures in Table 15 are: FT_s, FT_fs. Note: FT_a and FT_fa pins can be connected to analog peripherals inputs. When analog peripheral is not connected to this FT_a or FT_fa pins (analog switch from GPIO to peripheral is not closed, for example ADC not uses given pin as ADC input), then GPIO can accept VDD + 3.6 V (5 V tolerant I/O). However, once the I/O input is connected to the analog peripheral (for example ADC selects as input channel from this pin), the parasitic diode from this I/O pin to VDDA and/or VREF+ does not allow to use higher voltage on given I/O pin than VDDA or VREF+ and pin is no more 5 V-tolerant I/O. DS11585 Rev 16 71/284 119 Pin number Pin functions WLCSP100L_SMPS LQFP100 LQFP100_SMPS WLCSP115_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS - - - - - - - - C3 C3 - DS11585 Rev 16 - - - - - B9 B10 C8 C8 B10 E7 1 2 3 1 2 3 C16 B19 C18 B2 A1 B1 B2 A1 B1 1 2 3 1 2 3 D3 D2 D1 D3 D2 D1 PI11 I/O FT PE2 PE3 PE4 I/O I/O I/O Notes WLCSP100L - I/O structure LQFP64_SMPS - Pin type LQFP64 - Pin name (function after reset) Alternate functions Additional functions - EVENTOUT - FT_l TRACECK, TIM3_ETR, TSC_G7_IO1, - LCD_SEG38, FMC_A23, SAI1_MCLK_A, EVENTOUT - FT_l TRACED0, TIM3_CH1, TSC_G7_IO2, LCD_SEG39, FMC_A19, SAI1_SD_B, EVENTOUT FT TRACED1, TIM3_CH2, DFSDM1_DATIN3, - TSC_G7_IO3, DCMI_D4, FMC_A20, SAI1_FS_A, EVENTOUT - D8 E8 4 4 B21 C2 C2 4 4 E4 E4 PE5 I/O FT - - E7 D8 5 5 D19 D2 D2 5 5 E3 E3 PE6 I/O FT TRACED3, TIM3_CH4, - DCMI_D7, FMC_A22, RTC_TAMP3/WKUP3 SAI1_SD_A, EVENTOUT 1 1 C10 C10 6 6 C20 E2 E2 6 6 E2 E2 VBAT S - 2 2 C9 C9 7 7 D17 C1 C1 7 7 E1 E1 PC13 I/O FT - (1) (2) EVENTOUT RTC_TAMP1/RTC_TS/RT C_OUT/WKUP2 STM32L496xx - TRACED2, TIM3_CH3, DFSDM1_CKIN3, - TSC_G7_IO4, DCMI_D6, FMC_A21, SAI1_SCK_A, EVENTOUT Pinouts and pin description 72/284 Table 15. STM32L496xx pin definitions Pin number Pin functions WLCSP100L WLCSP100L_SMPS LQFP100 LQFP100_SMPS WLCSP115_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure D10 D10 8 8 D21 D1 D1 8 8 F1 F1 PC14OSC32_IN (PC14) I/O FT 4 4 E10 D9 9 9 E20 E1 E1 9 9 G1 G1 PC15OSC32_OUT (PC15) I/O FT - - - - - - - D6 D6 10 10 F5 F5 PF0 I/O FT_f - - - - - - - D5 D5 11 11 F4 F4 PF1 I/O - - - - - - D4 D4 12 12 F3 F3 PF2 - - - - - - - E4 E4 13 13 G3 G3 - - - - - - - F3 F3 14 14 G4 - - - - - - - F4 F4 15 15 - - D9 E10 10 10 - F2 F2 16 - - E9 E9 11 11 F19 G2 G2 - - - - - - - - - (1) Alternate functions Additional functions EVENTOUT OSC32_IN EVENTOUT OSC32_OUT - I2C2_SDA, FMC_A0, EVENTOUT - FT_f - I2C2_SCL, FMC_A1, EVENTOUT - I/O FT - I2C2_SMBA, FMC_A2, EVENTOUT - PF3 I/O FT_a - FMC_A3, EVENTOUT ADC3_IN6 G4 PF4 I/O FT_a - FMC_A4, EVENTOUT ADC3_IN7 G5 G5 PF5 I/O FT_a - FMC_A5, EVENTOUT ADC3_IN8 16 F2 F2 VSS S - - - - 17 17 G2 G2 VDD S - - - - 18 18 - - PF6 I/O FT_a (2) (1) (2) TIM5_ETR, TIM5_CH1, - QUADSPI_BK1_IO3, ADC3_IN9 SAI1_SD_B, EVENTOUT 73/284 Pinouts and pin description LQFP64_SMPS 3 Notes LQFP64 DS11585 Rev 16 3 Pin name (function after reset) STM32L496xx Table 15. STM32L496xx pin definitions (continued) Pin number Pin functions Notes I/O structure Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 UFBGA132_SMPS UFBGA132 WLCSP115_SMPS LQFP100_SMPS LQFP100 WLCSP100L_SMPS WLCSP100L LQFP64_SMPS LQFP64 Pin name (function after reset) Alternate functions Additional functions DS11585 Rev 16 - - - - - - - - - 19 19 - - PF7 I/O FT_a TIM5_CH2, QUADSPI_BK1_IO2, SAI1_MCLK_B, EVENTOUT - - - - - - - - - 20 20 - - PF8 I/O FT_a TIM5_CH3, - QUADSPI_BK1_IO0, ADC3_IN11 SAI1_SCK_B, EVENTOUT ADC3_IN10 - - - - - - - - - 21 21 - - PF9 I/O FT_a TIM5_CH4, QUADSPI_BK1_IO1, ADC3_IN12 SAI1_FS_B, TIM15_CH1, EVENTOUT - - - - - - - - - 22 22 H4 H4 PF10 I/O FT_a QUADSPI_CLK, - DCMI_D11, TIM15_CH2, EVENTOUT ADC3_IN13 5 5 F10 F10 12 12 F21 F1 F1 23 23 H1 H1 PH0-OSC_IN (PH0) I/O FT - EVENTOUT OSC_IN 6 6 G10 F9 13 13 G20 G1 G1 24 24 J1 J1 PH1OSC_OUT (PH1) I/O FT - EVENTOUT OSC_OUT 7 7 E8 F8 14 14 E16 H2 H2 25 25 H3 H3 NRST I/O RST - - - 8 F9 G10 15 15 F17 H1 H1 26 26 J2 J2 PC0 I/O FT_fla LPTIM1_IN1, I2C4_SCL, I2C3_SCL, DFSDM1_DATIN4, ADC123_IN1 LPUART1_RX, LCD_SEG18, LPTIM2_IN1, EVENTOUT STM32L496xx 8 Pinouts and pin description 74/284 Table 15. STM32L496xx pin definitions (continued) Pin number PC2 I/O I/O Notes J4 PC1 I/O structure J4 J3 Pin name (function after reset) Pin type 28 J3 UFBGA169_SMPS 28 27 UFBGA169 J3 27 LQFP144_SMPS J3 J2 LQFP144 G18 J2 UFBGA132_SMPS 17 H21 UFBGA132 17 16 WLCSP115_SMPS G9 16 LQFP100_SMPS H10 F7 LQFP100 10 F8 WLCSP100L_SMPS 9 WLCSP100L DS11585 Rev 16 10 LQFP64_SMPS LQFP64 9 Pin functions Alternate functions STM32L496xx Table 15. STM32L496xx pin definitions (continued) Additional functions FT_fla TRACED0, LPTIM1_OUT, I2C4_SDA, SPI2_MOSI, I2C3_SDA, DFSDM1_CKIN4, ADC123_IN2 LPUART1_TX, QUADSPI_BK2_IO0, LCD_SEG19, SAI1_SD_A, EVENTOUT FT_la LPTIM1_IN2, SPI2_MISO, DFSDM1_CKOUT, ADC123_IN3 QUADSPI_BK2_IO1, LCD_SEG20, EVENTOUT LPTIM1_ETR, SPI2_MOSI, QUADSPI_BK2_IO2, ADC123_IN4 LCD_VLCD, SAI1_SD_A, LPTIM2_ETR, EVENTOUT 11 F7 F6 18 18 H19 K2 K2 29 29 K1 K1 PC3 I/O FT_la - - H9 - 19 19 J18 - - 30 30 - - VSSA S - - - - - - G8 - 20 20 - - - 31 31 - - VREF- S - - - - 12 12 - H9 - - - J1 J1 - - K2 K2 VSSA/VREF- S - - - - - - G7 H10 21 21 J20 L1 L1 32 32 L1 L1 VREF+ S - - - VREFBUF_OUT - - J10 J10 22 22 K21 M1 M1 33 33 L2 L2 VDDA S - - - - 13 13 - - - - - - - - - - - VDDA/VREF+ - - - - - Pinouts and pin description 75/284 11 Pin number Pin functions DS11585 Rev 16 14 14 G9 G8 23 23 H17 L2 L2 34 34 K3 K3 PA0 I/O FT_a - - - - - - - M3 M3 - - M1 M1 OPAMP1_ VINM I TT 15 16 15 16 H8 H7 G7 H8 24 25 24 25 G16 F15 M2 K3 M2 K3 35 36 35 36 N2 N1 N2 N1 PA1 PA2 I/O I/O FT_la Notes I/O structure Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 UFBGA132_SMPS UFBGA132 WLCSP115_SMPS LQFP100_SMPS LQFP100 WLCSP100L_SMPS WLCSP100L LQFP64_SMPS LQFP64 Pin name (function after reset) Alternate functions Additional functions TIM2_CH1, TIM5_CH1, TIM8_ETR, USART2_CTS, OPAMP1_VINP, ADC12_IN5, - UART4_TX, RTC_TAMP2/WKUP1 SAI1_EXTCLK, TIM2_ETR, EVENTOUT - - (3) Pinouts and pin description 76/284 Table 15. STM32L496xx pin definitions (continued) - TIM2_CH2, TIM5_CH2, I2C1_SMBA, SPI1_SCK, OPAMP1_VINM, USART2_RTS_DE, ADC12_IN6 UART4_RX, LCD_SEG0, TIM15_CH1N, EVENTOUT TIM2_CH4, TIM5_CH4, USART2_RX, LPUART1_RX, OPAMP1_VOUT, - QUADSPI_CLK, ADC12_IN8 LCD_SEG2, SAI1_MCLK_A, TIM15_CH2, EVENTOUT 17 17 J9 J9 26 26 L20 L3 L3 37 37 M2 M2 PA3 I/O TT_la 18 18 K10 K10 27 27 - E3 E3 38 38 H2 H2 VSS S - - - - 19 19 J8 J8 28 28 K17 H3 H3 39 39 G13 G13 VDD S - - - - STM32L496xx FT_la TIM2_CH3, TIM5_CH3, USART2_TX, LPUART1_TX, ADC12_IN7, - QUADSPI_BK1_NCS, WKUP4/LSCO LCD_SEG1, SAI2_EXTCLK, TIM15_CH1, EVENTOUT Pin number Pin functions Notes I/O structure Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 UFBGA132_SMPS UFBGA132 WLCSP115_SMPS LQFP100_SMPS LQFP100 WLCSP100L_SMPS WLCSP100L LQFP64_SMPS LQFP64 Pin name (function after reset) Alternate functions Additional functions DS11585 Rev 16 20 20 F6 H7 29 29 L18 J4 J4 40 40 L3 L3 PA4 I/O TT_a SPI1_NSS, SPI3_NSS, USART2_CK, ADC12_IN9, DAC1_OUT1 - DCMI_HSYNC, SAI1_FS_B, LPTIM2_OUT, EVENTOUT 21 21 G6 J7 30 30 J16 K4 K4 41 41 K4 K4 PA5 I/O TT_a TIM2_CH1, TIM2_ETR, ADC12_IN10, - TIM8_CH1N, SPI1_SCK, DAC1_OUT2 LPTIM2_ETR, EVENTOUT TIM1_BKIN, TIM3_CH1, TIM8_BKIN, DCMI_PIXCLK, SPI1_MISO, USART3_CTS, OPAMP2_VINP, - LPUART1_CTS, ADC12_IN11 QUADSPI_BK1_IO3, LCD_SEG3, TIM1_BKIN_COMP2, TIM8_BKIN_COMP2, TIM16_CH1, EVENTOUT 22 K9 K9 31 31 H15 L4 L4 42 42 M4 M4 PA6 I/O FT_la - - - - - - - M4 M4 - - N4 N4 OPAMP2_ VINM I TT 77/284 23 23 J7 G6 32 32 L16 J5 J5 43 43 L4 L4 PA7 I/O FT_fla 24 24 H6 K8 33 33 K15 K5 K5 44 44 H5 H5 PC4 I/O FT_la - - (3) - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, I2C3_SCL, OPAMP2_VINM, SPI1_MOSI, ADC12_IN12 QUADSPI_BK1_IO2, LCD_SEG4, TIM17_CH1, EVENTOUT USART3_TX, COMP1_INM, - QUADSPI_BK2_IO3, ADC12_IN13 LCD_SEG22, EVENTOUT Pinouts and pin description 22 STM32L496xx Table 15. STM32L496xx pin definitions (continued) Pin number Pin functions WLCSP100L_SMPS LQFP100 LQFP100_SMPS WLCSP115_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS - 34 34 G14 L5 L5 45 45 J5 J5 26 DS11585 Rev 16 27 25 26 J6 K7 H6 K7 35 36 35 36 J14 L14 M5 M6 M5 M6 46 47 46 47 K5 L5 K5 L5 PC5 PB0 PB1 Notes WLCSP100L K8 I/O structure LQFP64_SMPS - Pin type LQFP64 25 Pin name (function after reset) I/O FT_la - TT_la TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI1_NSS, USART3_CK, OPAMP2_VOUT, - QUADSPI_BK1_IO1, ADC12_IN15 LCD_SEG5, COMP1_OUT, SAI1_EXTCLK, EVENTOUT FT_la TIM1_CH3N, TIM3_CH4, TIM8_CH3N, DFSDM1_DATIN0, COMP1_INM, USART3_RTS_DE, ADC12_IN16 LPUART1_RTS_DE, QUADSPI_BK1_IO0, LCD_SEG6, LPTIM2_IN1, EVENTOUT RTC_OUT, LPTIM1_OUT, I2C3_SMBA, COMP1_INP DFSDM1_CKIN0, LCD_VLCD, EVENTOUT I/O I/O Alternate functions Additional functions USART3_RX, COMP1_INP, LCD_SEG23, EVENTOUT ADC12_IN14, WKUP5 27 F5 J6 37 37 H13 L6 L6 48 48 N5 N5 PB2 I/O FT_la - - - - - - - K6 K6 49 49 M5 M5 PF11 I/O FT - DCMI_D12, EVENTOUT - - - - - - - - J7 J7 50 50 N6 N6 PF12 I/O FT - FMC_A6, EVENTOUT - - - - - - - K13 - - 51 51 - - VSS S - - - - - - - - - - K1 - - 52 52 A8 A8 VDD S - - - - STM32L496xx 28 Pinouts and pin description 78/284 Table 15. STM32L496xx pin definitions (continued) Pin number Pin functions LQFP64_SMPS WLCSP100L WLCSP100L_SMPS LQFP100 LQFP100_SMPS WLCSP115_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure - - - - - - K7 K7 53 53 M6 M6 PF13 I/O FT - - - - - - - J8 J8 54 54 L6 L6 PF14 I/O FT_fa - I2C4_SCL, DFSDM1_CKIN6, TSC_G8_IO1, FMC_A8, EVENTOUT - - - - - - - J9 J9 55 55 K6 K6 PF15 I/O FT_fa - I2C4_SDA, TSC_G8_IO2, FMC_A9, EVENTOUT - - - - - - J12 H9 H9 56 56 J6 J6 PG0 I/O FT - TSC_G8_IO3, FMC_A10, EVENTOUT - - - - - - G12 G9 G9 57 57 H6 H6 PG1 I/O FT - TSC_G8_IO4, FMC_A11, EVENTOUT - - K6 K6 38 38 K11 M7 M7 58 58 L7 L7 PE7 I/O FT - TIM1_ETR, DFSDM1_DATIN2, FMC_D4, SAI1_SD_B, EVENTOUT - FT TIM1_CH1N, DFSDM1_CKIN2, FMC_D5, SAI1_SCK_B, EVENTOUT - TIM1_CH1, DFSDM1_CKOUT, FMC_D6, SAI1_FS_B, EVENTOUT - - - - - K5 K5 39 39 L10 L7 L7 59 59 K7 K7 PE8 I/O - - J5 J5 40 40 H11 M8 M8 60 60 J7 J7 PE9 I/O FT - - - - - - - F6 F6 61 61 M7 M7 VSS S - Alternate functions I2C4_SMBA, - DFSDM1_DATIN6, FMC_A7, EVENTOUT Additional functions - - 79/284 Pinouts and pin description - Notes LQFP64 DS11585 Rev 16 - Pin name (function after reset) STM32L496xx Table 15. STM32L496xx pin definitions (continued) Pin number Pin functions WLCSP100L_SMPS LQFP100 LQFP100_SMPS WLCSP115_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS - - - - G6 G6 62 62 N7 N7 - DS11585 Rev 16 - - - - - - - H5 K4 G5 G4 J4 H5 K4 J4 G5 G4 41 42 43 44 45 41 42 43 44 45 K9 L8 J10 H9 K7 L8 M9 L9 M10 M11 L8 M9 L9 M10 M11 63 64 65 66 67 63 64 65 66 67 H7 N8 M8 L8 K8 H7 N8 M8 L8 K8 S - PE10 PE11 PE12 PE13 PE14 I/O I/O I/O I/O I/O Alternate functions - - Additional functions - FT TIM1_CH2N, DFSDM1_DATIN4, TSC_G5_IO1, QUADSPI_CLK, FMC_D7, SAI1_MCLK_B, EVENTOUT FT TIM1_CH2, DFSDM1_CKIN4, - TSC_G5_IO2, QUADSPI_BK1_NCS, FMC_D8, EVENTOUT FT TIM1_CH3N, SPI1_NSS, DFSDM1_DATIN5, - TSC_G5_IO3, QUADSPI_BK1_IO0, FMC_D9, EVENTOUT FT TIM1_CH3, SPI1_SCK, DFSDM1_CKIN5, - TSC_G5_IO4, QUADSPI_BK1_IO1, FMC_D10, EVENTOUT FT TIM1_CH4, TIM1_BKIN2, TIM1_BKIN2_COMP2, - SPI1_MISO, QUADSPI_BK1_IO2, FMC_D11, EVENTOUT - - STM32L496xx - - VDD Notes WLCSP100L - I/O structure LQFP64_SMPS - Pin type LQFP64 - Pin name (function after reset) Pinouts and pin description 80/284 Table 15. STM32L496xx pin definitions (continued) Pin number PB10 I/O I/O FT Notes N9 PE15 I/O structure N9 J8 Pin name (function after reset) Pin type 69 J8 UFBGA169_SMPS 69 68 UFBGA169 L10 68 LQFP144_SMPS L10 M12 LQFP144 J8 M12 UFBGA132_SMPS 47 L6 UFBGA132 47 46 WLCSP115_SMPS K3 46 LQFP100_SMPS K3 H4 LQFP100 28 H4 WLCSP100L_SMPS - WLCSP100L DS11585 Rev 16 29 LQFP64_SMPS LQFP64 - Pin functions Alternate functions TIM1_BKIN, TIM1_BKIN_COMP1, - SPI1_MOSI, QUADSPI_BK1_IO3, FMC_D12, EVENTOUT Additional functions - TIM2_CH4, I2C4_SDA, I2C2_SDA, DFSDM1_CKIN7, USART3_RX, LPUART1_TX, QUADSPI_BK1_NCS, LCD_SEG11, COMP2_OUT, EVENTOUT 81/284 29 J3 J3 48 - L4 L11 - 70 - H8 H8 PB11 I/O FT_fl - 30 - K1 - 48 - - L11 - 70 - M10 VDD12 S - - - - - - - - - - - - K9 K9 PH4 I/O - - - - - - - - - - - L9 L9 PH5 I/O - - - FT_f - I2C2_SCL, EVENTOUT - FT_f I2C2_SDA, - DCMI_PIXCLK, EVENTOUT - Pinouts and pin description FT_fl TIM2_CH3, I2C4_SCL, I2C2_SCL, SPI2_SCK, DFSDM1_DATIN7, USART3_TX, LPUART1_RX, TSC_SYNC, QUADSPI_CLK, LCD_SEG10, COMP1_OUT, SAI1_SCK_A, EVENTOUT 30 STM32L496xx Table 15. STM32L496xx pin definitions (continued) Pin number Pin functions LQFP64 LQFP64_SMPS WLCSP100L WLCSP100L_SMPS LQFP100 LQFP100_SMPS WLCSP115_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure Notes DS11585 Rev 16 - - - - - - - - - - - N10 N10 PH8 I/O FT_f - I2C3_SDA, DCMI_HSYNC, EVENTOUT - - - - - - - - - - - M9 M9 PH10 I/O FT - TIM5_CH1, DCMI_D1, EVENTOUT - - - - - - - - - - - - M10 - PH11 I/O FT - TIM5_CH2, DCMI_D2, EVENTOUT - - - - - - - - - - - - M3 M3 VSS S - - - - - - - - - - - - - - - N3 N3 VDD S - - - - - - - - - - - - - - - M11 M11 VSS S - - - - 31 31 K2 K2 49 49 - F12 F12 71 71 L13 L13 VSS S - - - - 32 32 K1 J2 50 50 - G12 G12 72 72 L12 L12 VDD S - - - - - - - - - - - - - - - N11 N11 VDD S - - - - 33 J1 J1 51 51 K5 L12 L12 73 73 N12 N12 PB12 I/O FT_l Alternate functions Additional functions TIM1_BKIN, TIM1_BKIN_COMP2, I2C2_SMBA, SPI2_NSS, DFSDM1_DATIN1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, CAN2_RX, LCD_SEG12, SWPMI1_IO, SAI2_FS_A, TIM15_BKIN, EVENTOUT STM32L496xx 33 Pin name (function after reset) Pinouts and pin description 82/284 Table 15. STM32L496xx pin definitions (continued) Pin number I/O FT_fl FT_fl TIM1_CH2N, TIM8_CH2N, I2C2_SDA, SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE, - TSC_G1_IO3, LCD_SEG14, SWPMI1_RX, SAI2_MCLK_A, TIM15_CH1, EVENTOUT - 36 - H2 H1 H3 H1 H3 G3 53 54 55 53 54 55 J4 - J2 K11 K10 K9 K11 K10 K9 75 76 77 75 76 77 M13 M12 L11 M13 M12 L11 PB14 PB15 PD8 I/O FT_l RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI, DFSDM1_CKIN2, TSC_G1_IO4, LCD_SEG15, SWPMI1_SUSPEND, SAI2_SD_A, TIM15_CH2, EVENTOUT I/O FT_l USART3_TX, DCMI_HSYNC, LCD_SEG28, FMC_D13, EVENTOUT I/O Additional functions 83/284 Pinouts and pin description 36 35 Alternate functions TIM1_CH1N, I2C2_SCL, SPI2_SCK, DFSDM1_CKIN1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, CAN2_TX, LCD_SEG13, SWPMI1_TX, SAI2_SCK_A, TIM15_CH1N, EVENTOUT DS11585 Rev 16 35 Notes PB13 I/O structure N13 Pin name (function after reset) Pin type N13 UFBGA169_SMPS 74 UFBGA169 74 LQFP144_SMPS K12 LQFP144 K12 UFBGA132_SMPS J6 UFBGA132 52 WLCSP115_SMPS 52 LQFP100_SMPS H2 LQFP100 J2 WLCSP100L_SMPS 34 WLCSP100L LQFP64_SMPS LQFP64 34 Pin functions STM32L496xx Table 15. STM32L496xx pin definitions (continued) Pin number Pin functions Notes I/O structure Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 UFBGA132_SMPS UFBGA132 WLCSP115_SMPS LQFP100_SMPS LQFP100 WLCSP100L_SMPS WLCSP100L LQFP64_SMPS LQFP64 Pin name (function after reset) Alternate functions Additional functions DS11585 Rev 16 - - G2 G2 56 56 H7 K8 K8 78 78 L10 L10 PD9 I/O FT_l USART3_RX, DCMI_PIXCLK, - LCD_SEG29, FMC_D14, SAI2_MCLK_A, EVENTOUT - - G1 G1 57 57 H5 J12 J12 79 79 J13 J13 PD10 I/O FT_l - FT_l I2C4_SMBA, USART3_CTS, TSC_G6_IO2, LCD_SEG31, FMC_A16, SAI2_SD_A, LPTIM2_ETR, EVENTOUT FT_fl TIM4_CH1, I2C4_SCL, USART3_RTS_DE, TSC_G6_IO3, LCD_SEG32, FMC_A17, SAI2_FS_A, LPTIM2_IN1, EVENTOUT TIM4_CH2, I2C4_SDA, TSC_G6_IO4, LCD_SEG33, FMC_A18, LPTIM2_OUT, EVENTOUT - - - - - - - - 58 59 58 59 - - J11 J10 J11 J10 80 81 80 81 K12 K11 K12 K11 PD11 PD12 I/O I/O Pinouts and pin description 84/284 Table 15. STM32L496xx pin definitions (continued) USART3_CK, TSC_G6_IO1, LCD_SEG30, FMC_D15, SAI2_SCK_A, EVENTOUT - - - 60 60 - H12 H12 82 82 K13 K13 PD13 I/O FT_fl - - - - - - - - - 83 83 H12 H12 VSS S - - - - - - F1 F1 - - - - - 84 84 H13 H13 VDD S - - - - STM32L496xx - Pin number Pin functions LQFP64_SMPS WLCSP100L WLCSP100L_SMPS LQFP100 LQFP100_SMPS WLCSP115_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure Notes - G3 F3 61 61 H3 H11 H11 85 85 K10 K10 PD14 I/O FT_l - TIM4_CH3, LCD_SEG34, FMC_D0, EVENTOUT - - F4 F2 62 62 H1 H10 H10 86 86 H11 H11 PD15 I/O FT_l - TIM4_CH4, LCD_SEG35, FMC_D1, EVENTOUT - - - - - - G8 G10 G10 87 87 J12 J12 PG2 I/O FT_s - SPI1_SCK, FMC_A12, SAI2_SCK_B, EVENTOUT - - - - - - G6 F9 F9 88 88 J11 J11 PG3 I/O FT_s - SPI1_MISO, FMC_A13, SAI2_FS_B, EVENTOUT - - - - - - G4 F10 F10 89 89 J10 J10 PG4 I/O FT_s SPI1_MOSI, FMC_A14, - SAI2_MCLK_B, EVENTOUT - - - - - - - G2 E9 E9 90 90 J9 J9 PG5 I/O FT_s - SPI1_NSS, LPUART1_CTS, FMC_A15, SAI2_SD_B, EVENTOUT - - - - - - - G10 G4 G4 91 91 G11 G11 PG6 I/O FT_s I2C3_SMBA, - LPUART1_RTS_DE, EVENTOUT - - - - - - F7 H4 H4 92 92 H10 H10 PG7 I/O FT_fs I2C3_SCL, LPUART1_TX, - FMC_INT, SAI1_MCLK_A, EVENTOUT - - - - - - F5 J6 J6 93 93 H9 H9 PG8 I/O FT_fs - - - - - - - F3 - - 94 94 F13 F13 VSS S - - - - - - - - - - F1 - - 95 95 F12 F12 VDDIO2 S - - - - Alternate functions Additional functions - I2C3_SDA, LPUART1_RX, EVENTOUT Pinouts and pin description 85/284 LQFP64 DS11585 Rev 16 - Pin name (function after reset) STM32L496xx Table 15. STM32L496xx pin definitions (continued) Pin number G9 G10 G9 PC7 PC8 PC9 I/O I/O I/O I/O Notes 99 G10 G12 PC6 I/O structure 99 98 G12 F11 Pin name (function after reset) Pin type D12 98 97 F11 UFBGA169_SMPS D12 E10 97 96 UFBGA169 E6 E10 E11 96 LQFP144_SMPS 66 E4 E11 E12 LQFP144 66 65 E2 E12 UFBGA132_SMPS E2 65 64 F9 UFBGA132 E2 E1 64 63 WLCSP115_SMPS 40 E1 E4 63 LQFP100_SMPS 39 F3 F4 LQFP100 40 38 F2 WLCSP100L_SMPS 39 37 WLCSP100L DS11585 Rev 16 38 LQFP64_SMPS LQFP64 37 Pin functions Alternate functions FT_l TIM3_CH2, TIM8_CH2, DFSDM1_DATIN3, TSC_G4_IO2, DCMI_D1, - LCD_SEG25, SDMMC1_D7, SAI2_MCLK_B, EVENTOUT FT_l TIM3_CH3, TIM8_CH3, TSC_G4_IO3, DCMI_D2, LCD_SEG26, SDMMC1_D0, EVENTOUT FT_fl TIM8_BKIN2, TIM3_CH4, TIM8_CH4, DCMI_D3, I2C3_SDA, TSC_G4_IO4, OTG_FS_NOE, - LCD_SEG27, SDMMC1_D1, SAI2_EXTCLK, TIM8_BKIN2_COMP1, EVENTOUT STM32L496xx FT_l TIM3_CH1, TIM8_CH1, DFSDM1_CKIN3, TSC_G4_IO1, DCMI_D0, - LCD_SEG24, SDMMC1_D6, SAI2_MCLK_A, EVENTOUT Additional functions Pinouts and pin description 86/284 Table 15. STM32L496xx pin definitions (continued) Pin number E13 F9 E13 PA9 PA10 PA11 I/O I/O I/O I/O Notes 103 F9 F10 PA8 I/O structure 103 102 F10 G8 Pin name (function after reset) Pin type B12 102 101 G8 UFBGA169_SMPS B12 C12 101 100 UFBGA169 C2 C12 D10 100 LQFP144_SMPS 70 E8 D10 D11 LQFP144 70 69 D1 D11 UFBGA132_SMPS D1 69 68 D3 UFBGA132 D1 D2 68 67 WLCSP115_SMPS 44 D2 D3 67 LQFP100_SMPS 43 D3 E3 LQFP100 44 42 E3 WLCSP100L_SMPS 43 41 WLCSP100L DS11585 Rev 16 42 LQFP64_SMPS LQFP64 41 Pin functions Alternate functions Additional functions FT_lu TIM1_CH2, SPI2_SCK, DCMI_D0, USART1_TX, OTG_FS_VBUS LCD_COM1, SAI1_FS_A, TIM15_BKIN, EVENTOUT FT_lu TIM1_CH3, DCMI_D1, USART1_RX, - OTG_FS_ID, LCD_COM2, SAI1_SD_A, TIM17_BKIN, EVENTOUT FT_u TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS, CAN1_RX, OTG_FS_DM, TIM1_BKIN2_COMP1, EVENTOUT TIM1_ETR, SPI1_MOSI, USART1_RTS_DE, CAN1_TX, OTG_FS_DP, EVENTOUT 45 C1 C1 71 71 B1 A12 A12 104 104 D13 D13 PA12 I/O FT_u 46 46 C2 C2 72 72 D5 A11 A11 105 105 A11 A11 PA13 (JTMS/ SWDIO) I/O FT (4) - 87/284 JTMS/SWDIO, IR_OUT, OTG_FS_NOE, SWPMI1_TX, SAI1_SD_B, EVENTOUT Pinouts and pin description FT_l MCO, TIM1_CH1, USART1_CK, OTG_FS_SOF, LCD_COM0, SWPMI1_IO, SAI1_SCK_A, LPTIM2_OUT, EVENTOUT 45 STM32L496xx Table 15. STM32L496xx pin definitions (continued) Pin number Pin functions WLCSP100L WLCSP100L_SMPS LQFP100 LQFP100_SMPS WLCSP115_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure B1 B1 - - B3 - - - - - - VSS S - - - - 48 48 A1 A1 73 73 C4 C11 C11 106 106 E12 E12 VDDUSB S - - - - - - - - 74 74 E18 F11 F11 107 107 C12 C12 VSS S - - - - - - - - 75 75 A2 G11 G11 108 108 C13 C13 VDD S - - - - - - - - - - - - - - - E11 E11 PH6 I/O FT - I2C2_SMBA, DCMI_D8, EVENTOUT - - - - - - - - - - - - D12 D12 PH7 I/O FT_f - I2C3_SCL, DCMI_D9, EVENTOUT - - - - - - - - - - - - D11 D11 PH9 I/O FT - I2C3_SMBA, DCMI_D0, EVENTOUT - - - - - - - - - - - - B13 B13 PH12 I/O FT - TIM5_CH3, DCMI_D3, EVENTOUT - - - - - - - - - - - - A13 A13 PH14 I/O FT - TIM8_CH2N, DCMI_D4, EVENTOUT - - - - - - - - - - - - B12 B12 PH15 I/O FT - TIM8_CH3N, DCMI_D11, EVENTOUT - - - - - - - - - - - A12 A12 PI0 I/O FT - TIM5_CH4, SPI2_NSS, DCMI_D13, EVENTOUT - - - - - - - - - - - - C11 C11 PI8 I/O FT - DCMI_D12, EVENTOUT - - - - - - - - - - - - B11 B11 PI1 I/O FT - SPI2_SCK, DCMI_D8, EVENTOUT - Alternate functions Additional functions STM32L496xx LQFP64_SMPS 47 Notes LQFP64 DS11585 Rev 16 47 Pin name (function after reset) Pinouts and pin description 88/284 Table 15. STM32L496xx pin definitions (continued) Pin number Pin functions LQFP64 LQFP64_SMPS WLCSP100L WLCSP100L_SMPS LQFP100 LQFP100_SMPS WLCSP115_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure Notes DS11585 Rev 16 - - - - - - - - - - - B10 B10 PI2 I/O FT - TIM8_CH4, SPI2_MISO, DCMI_D9, EVENTOUT - - - - - - - - - - - - C10 C10 PI3 I/O FT - TIM8_ETR, SPI2_MOSI, DCMI_D10, EVENTOUT - - - - - - - - - - - - D10 D10 PI4 I/O FT - TIM8_BKIN, DCMI_D5, EVENTOUT - - - - - - - - - - - - E10 E10 PI5 I/O FT TIM8_CH1, - DCMI_VSYNC, EVENTOUT - - - - - - - - - - - C9 C9 PH13 I/O FT - TIM8_CH1N, CAN1_TX, EVENTOUT - - - - - - - - - - - - B9 B9 PI6 I/O FT - TIM8_CH2, DCMI_D6, EVENTOUT - 49 50 B2 A2 B2 A2 76 77 76 77 D7 C6 A10 A9 A10 A9 109 110 109 110 A10 A9 A10 A9 PA14 (JTCK/ SWCLK) PA15 (JTDI) I/O I/O FT FT_l Alternate functions Additional functions - 89/284 (4) JTCK/SWCLK, LPTIM1_OUT, I2C1_SMBA, I2C4_SMBA, OTG_FS_SOF, SWPMI1_RX, SAI1_FS_B, EVENTOUT (4) JTDI, TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, UART4_RTS_DE, TSC_G3_IO1, LCD_SEG17, SWPMI1_SUSPEND, SAI2_FS_B, EVENTOUT Pinouts and pin description 50 49 Pin name (function after reset) STM32L496xx Table 15. STM32L496xx pin definitions (continued) Pin number C8 B8 C8 PC12 PD0 PD1 I/O I/O I/O I/O Alternate functions Additional functions FT_l TRACED1, SPI3_SCK, USART3_TX, UART4_TX, TSC_G3_IO2, DCMI_D8, - LCD_COM4/LCD_SEG28/ LCD_SEG40, SDMMC1_D2, SAI2_SCK_B, EVENTOUT FT_l QUADSPI_BK2_NCS, SPI3_MISO, USART3_RX, UART4_RX, TSC_G3_IO3, DCMI_D4, - LCD_COM5/LCD_SEG29/ LCD_SEG41, SDMMC1_D3, SAI2_MCLK_B, EVENTOUT FT_l TRACED3, SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, DCMI_D9, - LCD_COM6/LCD_SEG30/ LCD_SEG42, SDMMC1_CK, SAI2_SD_B, EVENTOUT FT SPI2_NSS, DFSDM1_DATIN7, CAN1_RX, FMC_D2, EVENTOUT - FT SPI2_SCK, DFSDM1_CKIN7, CAN1_TX, FMC_D3, EVENTOUT - STM32L496xx 115 B8 F8 PC11 I/O Notes 115 114 F8 E9 PC10 I/O structure B9 114 113 E9 D9 Pin name (function after reset) Pin type B9 C9 113 112 D9 UFBGA169_SMPS B7 C9 B10 112 111 UFBGA169 82 C8 B10 C10 111 LQFP144_SMPS 82 81 D9 C10 B11 LQFP144 A3 81 80 A4 B11 UFBGA132_SMPS A3 B3 80 79 B5 UFBGA132 - B3 C4 79 78 WLCSP115_SMPS - C4 D4 78 LQFP100_SMPS - 53 C3 C3 LQFP100 - 52 D4 WLCSP100L_SMPS 53 51 WLCSP100L DS11585 Rev 16 52 LQFP64_SMPS LQFP64 51 Pin functions Pinouts and pin description 90/284 Table 15. STM32L496xx pin definitions (continued) Pin number PD3 I/O I/O FT_l Notes E8 PD2 I/O structure E8 D8 Pin name (function after reset) Pin type 117 D8 UFBGA169_SMPS 117 116 UFBGA169 B8 116 LQFP144_SMPS B8 C8 LQFP144 - C8 UFBGA132_SMPS 84 A6 UFBGA132 84 83 WLCSP115_SMPS - 83 LQFP100_SMPS - D5 LQFP100 - E4 WLCSP100L_SMPS - WLCSP100L DS11585 Rev 16 - LQFP64_SMPS LQFP64 54 Pin functions Alternate functions STM32L496xx Table 15. STM32L496xx pin definitions (continued) Additional functions TRACED2, TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, DCMI_D11, LCD_COM7/LCD_SEG31/ LCD_SEG43, SDMMC1_CMD, EVENTOUT FT SPI2_SCK, DCMI_D5, SPI2_MISO, DFSDM1_DATIN0, USART2_CTS, QUADSPI_BK2_NCS, FMC_CLK, EVENTOUT - - - B4 C5 85 85 E10 B7 B7 118 118 C7 C7 PD4 I/O FT - - E5 B4 86 86 C10 A6 A6 119 119 D7 D7 PD5 I/O FT USART2_TX, - QUADSPI_BK2_IO1, FMC_NWE, EVENTOUT - - - - - - - A18 - - 120 120 - - VSS S - - - - - - A4 A4 - - A8 - - 121 121 - - VDD S - - - - 91/284 Pinouts and pin description - SPI2_MOSI, DFSDM1_CKIN0, - USART2_RTS_DE, QUADSPI_BK2_IO0, FMC_NOE, EVENTOUT Pin number Pin functions Notes I/O structure Pin type UFBGA169_SMPS UFBGA169 LQFP144_SMPS LQFP144 UFBGA132_SMPS UFBGA132 WLCSP115_SMPS LQFP100_SMPS LQFP100 WLCSP100L_SMPS WLCSP100L LQFP64_SMPS LQFP64 Pin name (function after reset) Alternate functions Additional functions DS11585 Rev 16 - - D5 B5 87 87 F11 B6 B6 122 122 E7 E7 PD6 I/O FT DCMI_D10, QUADSPI_BK2_IO1, DFSDM1_DATIN1, - USART2_RX, QUADSPI_BK2_IO2, FMC_NWAIT, SAI1_SD_A, EVENTOUT - - C5 C6 88 88 D11 A5 A5 123 123 F7 F7 PD7 I/O FT - - - - - B5 A5 D6 A5 - - - - E12 A10 D9 D8 D9 D8 124 125 124 125 B7 D6 B7 D6 PG9 PG10 I/O I/O DFSDM1_CKIN1, USART2_CK, QUADSPI_BK2_IO3, FMC_NE1, EVENTOUT Pinouts and pin description 92/284 Table 15. STM32L496xx pin definitions (continued) - FT_s SPI3_SCK, USART1_TX, FMC_NCE/FMC_NE2, SAI2_SCK_A, TIM15_CH1N, EVENTOUT FT_s LPTIM1_IN1, SPI3_MISO, USART1_RX, FMC_NE3, SAI2_FS_A, TIM15_CH1, EVENTOUT - D6 E5 - - B11 G3 G3 126 126 E6 E6 PG11 I/O FT_s - - B6 B6 - - C12 D7 D7 127 127 F6 F6 PG12 I/O FT_s - LPTIM1_ETR, SPI3_NSS, USART1_RTS_DE, FMC_NE4, SAI2_SD_A, EVENTOUT - - - - - - D13 C7 C7 128 128 G7 G7 PG13 I/O FT_fs - I2C1_SDA, USART1_CK, FMC_A24, EVENTOUT STM32L496xx - LPTIM1_IN2, SPI3_MOSI, USART1_CTS, SAI2_MCLK_A, TIM15_CH2, EVENTOUT Pin number Pin functions LQFP64 LQFP64_SMPS WLCSP100L WLCSP100L_SMPS LQFP100 LQFP100_SMPS WLCSP115_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure Notes DS11585 Rev 16 - - - - - - A12 C6 - 129 129 G6 G6 PG14 I/O FT_fs - - - - - - - B9 F7 F7 130 130 A7 A7 VSS S - - - - - - A6 A6 - - B13 G7 G7 131 131 B6 B6 VDDIO2 S - - - - - - - - - - - K1 K1 132 - C6 - PG15 I/O FT_s 55 55 C6 C7 F5 E6 89 90 89 90 F13 C14 A8 A7 A8 A7 133 134 132 133 A6 A5 A6 A5 PB3 (JTDO/TRACE SWO) PB4 (NJTRST) I/O I/O FT_la FT_fla Alternate functions I2C1_SCL, FMC_A25, EVENTOUT Additional functions - LPTIM1_OUT, - I2C1_SMBA, DCMI_D13, EVENTOUT (4) JTDO/TRACESWO, TIM2_CH2, SPI1_SCK, SPI3_SCK, COMP2_INM USART1_RTS_DE, OTG_FS_CRS_SYNC, LCD_SEG7, SAI1_SCK_B, EVENTOUT (4) NJTRST, TIM3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS, COMP2_INP UART5_RTS_DE, TSC_G2_IO1, DCMI_D12, LCD_SEG8, SAI1_MCLK_B, TIM17_BKIN, EVENTOUT 93/284 Pinouts and pin description 56 54 Pin name (function after reset) STM32L496xx Table 15. STM32L496xx pin definitions (continued) Pin number PB6 I/O I/O Notes C5 PB5 I/O structure C5 B5 Pin name (function after reset) Pin type 135 B5 UFBGA169_SMPS 136 134 UFBGA169 B5 135 LQFP144_SMPS B5 C5 LQFP144 E14 C5 UFBGA132_SMPS 92 A14 UFBGA132 92 91 WLCSP115_SMPS A7 91 LQFP100_SMPS A7 C7 LQFP100 57 B7 WLCSP100L_SMPS 56 WLCSP100L DS11585 Rev 16 58 LQFP64_SMPS LQFP64 57 Pin functions Alternate functions Additional functions FT_fa LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL, I2C4_SCL, DFSDM1_DATIN5, - USART1_TX, CAN2_TX, COMP2_INP TSC_G2_IO3, DCMI_D5, TIM8_BKIN2_COMP2, SAI1_FS_B, TIM16_CH1N, EVENTOUT LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA, I2C4_SDA, DFSDM1_CKIN5, USART1_RX, COMP2_INM, PVD_IN - UART4_CTS, TSC_G2_IO4, DCMI_VSYNC, LCD_SEG21, FMC_NL, TIM8_BKIN_COMP1, TIM17_CH1N, EVENTOUT 59 58 D7 B7 93 93 B15 B4 B4 137 136 D5 D5 PB7 I/O FT_fla 60 59 E6 D7 94 94 D15 A4 A4 138 137 E5 E5 PH3-BOOT0 I/O FT - EVENTOUT - STM32L496xx FT_la LPTIM1_IN1, TIM3_CH2, CAN2_RX, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI, USART1_CK, - UART5_CTS, TSC_G2_IO2, DCMI_D10, LCD_SEG9, COMP2_OUT, SAI1_SD_B, TIM16_BKIN, EVENTOUT Pinouts and pin description 94/284 Table 15. STM32L496xx pin definitions (continued) Pin number I/O Notes PB8 I/O structure C4 Pin name (function after reset) Pin type C4 UFBGA169_SMPS 138 UFBGA169 139 LQFP144_SMPS A3 LQFP144 A3 UFBGA132_SMPS - UFBGA132 95 WLCSP115_SMPS 95 LQFP100_SMPS B8 LQFP100 B8 WLCSP100L_SMPS 60 WLCSP100L LQFP64_SMPS LQFP64 61 Pin functions Alternate functions Additional functions DS11585 Rev 16 FT_fl TIM4_CH3, I2C1_SCL, DFSDM1_DATIN6, CAN1_RX, DCMI_D6, - LCD_SEG16, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1, EVENTOUT IR_OUT, TIM4_CH4, I2C1_SDA, SPI2_NSS, DFSDM1_CKIN6, CAN1_TX, DCMI_D7, LCD_COM3, SDMMC1_D5, SAI1_FS_A, TIM17_CH1, EVENTOUT 61 A8 A8 96 96 A16 B3 B3 140 139 D4 D4 PB9 I/O FT_fl - 62 - - - - B17 - C6 - - - C6 VDD12 S - - - - - 97 97 - C3 C3 141 140 A4 A4 PE0 I/O FT_l TIM4_ETR, DCMI_D2, - LCD_SEG36, FMC_NBL0, TIM16_CH1, EVENTOUT - - - - 98 - - A2 A2 142 141 B4 B4 PE1 I/O FT_l DCMI_D3, LCD_SEG37, - FMC_NBL1, TIM17_CH1, EVENTOUT - - - A9 - 98 L2 - - - 142 - - VDD12 S - - - - 63 63 A9 B9 99 99 K19 D3 D3 143 143 B3 B3 VSS S - - - - 64 64 A10 A10 100 100 L12 C4 C4 144 144 A3 A3 VDD S - - - - - Pinouts and pin description 95/284 62 - - STM32L496xx Table 15. STM32L496xx pin definitions (continued) Pin number Pin functions LQFP64_SMPS WLCSP100L WLCSP100L_SMPS LQFP100 LQFP100_SMPS WLCSP115_SMPS UFBGA132 UFBGA132_SMPS LQFP144 LQFP144_SMPS UFBGA169 UFBGA169_SMPS Pin type I/O structure - - - - - K3 - - - - C2 C2 VSS S - - - - - - - - - - A20 - - - - C1 C1 VDD S - - - - - - - - - - - - - - - A2 A2 PH2 I/O FT - QUADSPI_BK2_IO0, EVENTOUT - - - - - - - - - - - - B2 B2 PI7 I/O FT - TIM8_CH3, DCMI_D7, EVENTOUT - - - - - - - - - - - - B1 B1 PI9 I/O FT - - - - - - - - - - - - A1 A1 PI10 I/O FT - Notes LQFP64 DS11585 Rev 16 - Pin name (function after reset) Alternate functions CAN1_RX, EVENTOUT EVENTOUT Additional functions Pinouts and pin description 96/284 Table 15. STM32L496xx pin definitions (continued) - 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These GPIOs must not be used as current sources (e.g. to drive an LED). 2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0351 reference manual. 3. OPAMPx_VINM pins are not available as additional functions on pins PA1 and PA7 on UFBGA packages. On UFBGA packages, use the OPAMPx_VINM dedicated pins available on M3 and M4 balls. 4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated. STM32L496xx AF0 AF1 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR - - - USART2_CTS PA1 - TIM2_CH2 TIM5_CH2 - I2C1_SMBA SPI1_SCK - USART2_RTS_ DE PA2 - TIM2_CH3 TIM5_CH3 - - - - USART2_TX PA3 - TIM2_CH4 TIM5_CH4 - - - - USART2_RX PA4 - - - - - SPI1_NSS SPI3_NSS USART2_CK PA5 - TIM2_CH1 TIM2_ETR TIM8_CH1N - SPI1_SCK - - PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN DCMI_PIXCLK SPI1_MISO - USART3_CTS PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N I2C3_SCL SPI1_MOSI - - PA8 MCO TIM1_CH1 - - - - - USART1_CK PA9 - TIM1_CH2 - SPI2_SCK - DCMI_D0 - USART1_TX PA10 - TIM1_CH3 - - - DCMI_D1 - USART1_RX PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO - USART1_CTS PA12 - TIM1_ETR - - - SPI1_MOSI - USART1_RTS_ DE PA13 JTMS/SWDIO IR_OUT - - - - - - PA14 JTCK/SWCLK LPTIM1_OUT - - I2C1_SMBA I2C4_SMBA - - PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX - SPI1_NSS SPI3_NSS USART3_RTS_ DE Port DS11585 Rev 16 Port A 97/284 Pinouts and pin description AF2 STM32L496xx Table 16. Alternate function AF0 to AF7(1) AF0 AF1 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - SPI1_NSS - USART3_CK PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - DFSDM1_ DATIN0 USART3_RTS_ DE PB2 RTC_OUT LPTIM1_OUT - - I2C3_SMBA - DFSDM1_CKIN0 - PB3 JTDO/ TRACESWO TIM2_CH2 - - - SPI1_SCK SPI3_SCK USART1_RTS_ DE PB4 NJTRST - TIM3_CH1 - I2C3_SDA SPI1_MISO SPI3_MISO USART1_CTS PB5 - LPTIM1_IN1 TIM3_CH2 CAN2_RX I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK PB6 - LPTIM1_ETR TIM4_CH1 TIM8_BKIN2 I2C1_SCL I2C4_SCL DFSDM1_ DATIN5 USART1_TX PB7 - LPTIM1_IN2 TIM4_CH2 TIM8_BKIN I2C1_SDA I2C4_SDA DFSDM1_CKIN5 USART1_RX PB8 - - TIM4_CH3 - I2C1_SCL - DFSDM1_ DATIN6 - PB9 - IR_OUT TIM4_CH4 - I2C1_SDA SPI2_NSS DFSDM1_CKIN6 - PB10 - TIM2_CH3 - I2C4_SCL I2C2_SCL SPI2_SCK DFSDM1_ DATIN7 USART3_TX PB11 - TIM2_CH4 - I2C4_SDA I2C2_SDA - DFSDM1_CKIN7 USART3_RX PB12 - TIM1_BKIN - TIM1_BKIN_ COMP2 I2C2_SMBA SPI2_NSS DFSDM1_ DATIN1 USART3_CK PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK DFSDM1_CKIN1 USART3_CTS PB14 - TIM1_CH2N - TIM8_CH2N I2C2_SDA SPI2_MISO DFSDM1_ DATIN2 USART3_RTS_ DE PB15 RTC_REFIN TIM1_CH3N - TIM8_CH3N - SPI2_MOSI DFSDM1_CKIN2 - Port DS11585 Rev 16 Port B STM32L496xx AF2 Pinouts and pin description 98/284 Table 16. Alternate function AF0 to AF7(1) (continued) AF0 AF1 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PC0 - LPTIM1_IN1 I2C4_SCL - I2C3_SCL - DFSDM1_ DATIN4 - PC1 TRACED0 LPTIM1_OUT I2C4_SDA SPI2_MOSI I2C3_SDA - DFSDM1_CKIN4 - PC2 - LPTIM1_IN2 - - - SPI2_MISO DFSDM1_ CKOUT - PC3 - LPTIM1_ETR - - - SPI2_MOSI - - PC4 - - - - - - - USART3_TX PC5 - - - - - - - USART3_RX PC6 - - TIM3_CH1 TIM8_CH1 - - DFSDM1_CKIN3 - PC7 - - TIM3_CH2 TIM8_CH2 - - DFSDM1_ DATIN3 - PC8 - - TIM3_CH3 TIM8_CH3 - - - - PC9 - TIM8_BKIN2 TIM3_CH4 TIM8_CH4 DCMI_D3 - I2C3_SDA - PC10 TRACED1 - - - - - SPI3_SCK USART3_TX PC11 - - - - - QUADSPI_ BK2_NCS SPI3_MISO USART3_RX PC12 TRACED3 - - - - - SPI3_MOSI USART3_CK PC13 - - - - - - - - PC14 - - - - - - - - PC15 - - - - - - - - Port DS11585 Rev 16 Port C 99/284 Pinouts and pin description AF2 STM32L496xx Table 16. Alternate function AF0 to AF7(1) (continued) AF0 AF1 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PD0 - - - - - SPI2_NSS DFSDM1_ DATIN7 - PD1 - - - - - SPI2_SCK DFSDM1_CKIN7 - PD2 TRACED2 - TIM3_ETR - - - - USART3_RTS_ DE PD3 - - - SPI2_SCK DCMI_D5 SPI2_MISO DFSDM1_ DATIN0 USART2_CTS PD4 - - - - - SPI2_MOSI DFSDM1_CKIN0 USART2_RTS_ DE PD5 - - - - - - - USART2_TX PD6 - - - - DCMI_D10 QUADSPI_ BK2_IO1 DFSDM1_ DATIN1 USART2_RX PD7 - - - - - - DFSDM1_CKIN1 USART2_CK PD8 - - - - - - - USART3_TX PD9 - - - - - - - USART3_RX PD10 - - - - - - - USART3_CK PD11 - - - - I2C4_SMBA - - USART3_CTS PD12 - - TIM4_CH1 - I2C4_SCL - - USART3_RTS_ DE PD13 - - TIM4_CH2 - I2C4_SDA - - - PD14 - - TIM4_CH3 - - - - - PD15 - - TIM4_CH4 - - - - - Port DS11585 Rev 16 Port D STM32L496xx AF2 Pinouts and pin description 100/284 Table 16. Alternate function AF0 to AF7(1) (continued) AF0 AF1 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PE0 - - TIM4_ETR - - - - - PE1 - - - - - - - - PE2 TRACECK - TIM3_ETR - - - - - PE3 TRACED0 - TIM3_CH1 - - - - - PE4 TRACED1 - TIM3_CH2 - - - DFSDM1_ DATIN3 - PE5 TRACED2 - TIM3_CH3 - - - DFSDM1_CKIN3 - PE6 TRACED3 - TIM3_CH4 - - - - - PE7 - TIM1_ETR - - - - DFSDM1_ DATIN2 - PE8 - TIM1_CH1N - - - - DFSDM1_CKIN2 - PE9 - TIM1_CH1 - - - - DFSDM1_ CKOUT - PE10 - TIM1_CH2N - - - - DFSDM1_ DATIN4 - PE11 - TIM1_CH2 - - - - DFSDM1_CKIN4 - PE12 - TIM1_CH3N - - - SPI1_NSS DFSDM1_ DATIN5 - PE13 - TIM1_CH3 - - - SPI1_SCK DFSDM1_CKIN5 - PE14 - TIM1_CH4 TIM1_BKIN2 TIM1_BKIN2_ COMP2 - SPI1_MISO - - PE15 - TIM1_BKIN - TIM1_BKIN_ COMP1 - SPI1_MOSI - - Port DS11585 Rev 16 Port E 101/284 Pinouts and pin description AF2 STM32L496xx Table 16. Alternate function AF0 to AF7(1) (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PF0 - - - - I2C2_SDA - - - PF1 - - - - I2C2_SCL - - - PF2 - - - - I2C2_SMBA - - - PF3 - - - - - - - - PF4 - - - - - - - - PF5 - - - - - - - - PF6 - TIM5_ETR TIM5_CH1 - - - - - PF7 - - TIM5_CH2 - - - - - PF8 - - TIM5_CH3 - - - - - PF9 - - TIM5_CH4 - - - - - PF10 - - - QUADSPI_CLK - - - - PF11 - - - - - - - - PF12 - - - - - - - - PF13 - - - - I2C4_SMBA - DFSDM1_ DATIN6 - PF14 - - - - I2C4_SCL - DFSDM1_CKIN6 - PF15 - - - - I2C4_SDA - - - Port DS11585 Rev 16 Port F Pinouts and pin description 102/284 Table 16. Alternate function AF0 to AF7(1) (continued) STM32L496xx AF0 AF1 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PG0 - - - - - - - - PG1 - - - - - - - - PG2 - - - - - SPI1_SCK - - PG3 - - - - - SPI1_MISO - - PG4 - - - - - SPI1_MOSI - - PG5 - - - - - SPI1_NSS - - PG6 - - - - I2C3_SMBA - - - PG7 - - - - I2C3_SCL - - - PG8 - - - - I2C3_SDA - - - PG9 - - - - - - SPI3_SCK USART1_TX PG10 - LPTIM1_IN1 - - - - SPI3_MISO USART1_RX PG11 - LPTIM1_IN2 - - - - SPI3_MOSI USART1_CTS PG12 - LPTIM1_ETR - - - - SPI3_NSS USART1_RTS_ DE PG13 - - - - I2C1_SDA - - USART1_CK PG14 - - - - I2C1_SCL - - - PG15 - LPTIM1_OUT - - I2C1_SMBA - - - Port DS11585 Rev 16 Port G 103/284 Pinouts and pin description AF2 STM32L496xx Table 16. Alternate function AF0 to AF7(1) (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PH0 - - - - - - - - PH1 - - - - - - - - PH2 - - - QUADSPI_ BK2_IO0 - - - - PH3 - - - - - - - - PH4 - - - - I2C2_SCL - - - PH5 - - - - I2C2_SDA - - - PH6 - - - - I2C2_SMBA - - - PH7 - - - - I2C3_SCL - - - PH8 - - - - I2C3_SDA - - - PH9 - - - - I2C3_SMBA - - - PH10 - - TIM5_CH1 - - - - - PH11 - - TIM5_CH2 - - - - - PH12 - - TIM5_CH3 - - - - - PH13 - - - TIM8_CH1N - - - - PH14 - - - TIM8_CH2N - - - - PH15 - - - TIM8_CH3N - - - - Port DS11585 Rev 16 Port H Pinouts and pin description 104/284 Table 16. Alternate function AF0 to AF7(1) (continued) STM32L496xx AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 SYS_AF TIM1/2/5/8/ LPTIM1 TIM1/2/3/4/5 SPI2/USART2/ CAN2/TIM8/ QUADSPI I2C1/2/3/4/ DCMI SPI1/2/DCMI/ QUADSPI SPI3/I2C3/ DFSDM/ COMP1/ QUADSPI USART1/2/3 PI0 - - TIM5_CH4 - - SPI2_NSS - - PI1 - - - - - SPI2_SCK - - PI2 - - - TIM8_CH4 - SPI2_MISO - - PI3 - - - TIM8_ETR - SPI2_MOSI - - PI4 - - - TIM8_BKIN - - - - PI5 - - - TIM8_CH1 - - - - PI6 - - - TIM8_CH2 - - - - PI7 - - - TIM8_CH3 - - - - PI8 - - - - - - - - PI9 - - - - - - - - PI10 - - - - - - - - PI11 - - - - - - - - Port DS11585 Rev 16 Port I STM32L496xx Table 16. Alternate function AF0 to AF7(1) (continued) 1. Refer to Table 17 for AF8 to AF15. Pinouts and pin description 105/284 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/ FMC/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENTOUT PA0 UART4_TX - - - - SAI1_EXTCLK TIM2_ETR EVENTOUT PA1 UART4_RX - - LCD_SEG0 - - TIM15_CH1N EVENTOUT PA2 LPUART1_TX - QUADSPI_BK1_NCS LCD_SEG1 - SAI2_EXTCLK TIM15_CH1 EVENTOUT PA3 LPUART1_RX - QUADSPI_CLK LCD_SEG2 - SAI1_MCLK_A TIM15_CH2 EVENTOUT PA4 - - DCMI_HSYNC - - SAI1_FS_B LPTIM2_OUT EVENTOUT PA5 - - - - - - LPTIM2_ETR EVENTOUT PA6 LPUART1_ CTS - QUADSPI_BK1_IO3 LCD_SEG3 TIM1_BKIN_ COMP2 TIM8_BKIN_C OMP2 TIM16_CH1 EVENTOUT PA7 - - QUADSPI_BK1_IO2 LCD_SEG4 - - TIM17_CH1 EVENTOUT PA8 - - OTG_FS_SOF LCD_COM0 SWPMI1_IO SAI1_SCK_A LPTIM2_OUT EVENTOUT PA9 - - - LCD_COM1 - SAI1_FS_A TIM15_BKIN EVENTOUT PA10 - - OTG_FS_ID LCD_COM2 - SAI1_SD_A TIM17_BKIN EVENTOUT PA11 - CAN1_RX OTG_FS_DM - TIM1_BKIN2_ COMP1 - - EVENTOUT PA12 - CAN1_TX OTG_FS_DP - - - - EVENTOUT PA13 - - OTG_FS_NOE - SWPMI1_TX SAI1_SD_B - EVENTOUT PA14 - - OTG_FS_SOF - SWPMI1_RX SAI1_FS_B - EVENTOUT - LCD_SEG17 SWPMI1_ SUSPEND SAI2_FS_B - EVENTOUT Port DS11585 Rev 16 Port A PA15 UART4_RTS_ TSC_G3_IO1 DE STM32L496xx AF8 Pinouts and pin description 106/284 Table 17. Alternate function AF8 to AF15(1) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/ FMC/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENTOUT PB0 - - QUADSPI_BK1_IO1 LCD_SEG5 COMP1_OUT SAI1_EXTCLK - EVENTOUT PB1 LPUART1_ RTS_DE - QUADSPI_BK1_IO0 LCD_SEG6 - - LPTIM2_IN1 EVENTOUT PB2 - - - LCD_VLCD - - - EVENTOUT PB3 - - OTG_FS_CRS_SYNC LCD_SEG7 - SAI1_SCK_B - EVENTOUT PB4 UART5_ RTS_DE TSC_G2_IO1 DCMI_D12 LCD_SEG8 - SAI1_MCLK_B TIM17_BKIN EVENTOUT PB5 UART5_CTS TSC_G2_IO2 DCMI_D10 LCD_SEG9 COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT PB6 CAN2_TX TSC_G2_IO3 DCMI_D5 - TIM8_BKIN2_ COMP2 SAI1_FS_B TIM16_CH1N EVENTOUT PB7 UART4_CTS TSC_G2_IO4 DCMI_VSYNC LCD_SEG21 FMC_NL TIM8_BKIN_C OMP1 TIM17_CH1N EVENTOUT PB8 - CAN1_RX DCMI_D6 LCD_SEG16 SDMMC1_D4 SAI1_MCLK_A TIM16_CH1 EVENTOUT PB9 - CAN1_TX DCMI_D7 LCD_COM3 SDMMC1_D5 SAI1_FS_A TIM17_CH1 EVENTOUT PB10 LPUART1_RX TSC_SYNC QUADSPI_CLK LCD_SEG10 COMP1_OUT SAI1_SCK_A - EVENTOUT PB11 LPUART1_TX - QUADSPI_BK1_NCS LCD_SEG11 COMP2_OUT - - EVENTOUT PB12 LPUART1_ RTS_DE TSC_G1_IO1 CAN2_RX LCD_SEG12 SWPMI1_IO SAI2_FS_A TIM15_BKIN EVENTOUT PB13 LPUART1_ CTS TSC_G1_IO2 CAN2_TX LCD_SEG13 SWPMI1_TX SAI2_SCK_A TIM15_CH1N EVENTOUT PB14 - TSC_G1_IO3 - LCD_SEG14 SWPMI1_RX SAI2_MCLK_A TIM15_CH1 EVENTOUT PB15 - TSC_G1_IO4 - LCD_SEG15 SWPMI1_ SUSPEND SAI2_SD_A TIM15_CH2 EVENTOUT Port DS11585 Rev 16 Port B 107/284 Pinouts and pin description AF8 STM32L496xx Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/ FMC/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENTOUT PC0 LPUART1_RX - - LCD_SEG18 - - LPTIM2_IN1 EVENTOUT PC1 LPUART1_TX - QUADSPI_BK2_IO0 LCD_SEG19 - SAI1_SD_A - EVENTOUT PC2 - - QUADSPI_BK2_IO1 LCD_SEG20 - - - EVENTOUT PC3 - - QUADSPI_BK2_IO2 LCD_VLCD - SAI1_SD_A LPTIM2_ETR EVENTOUT PC4 - - QUADSPI_BK2_IO3 LCD_SEG22 - - - EVENTOUT PC5 - - - LCD_SEG23 - - - EVENTOUT PC6 - TSC_G4_IO1 DCMI_D0 LCD_SEG24 SDMMC1_D6 SAI2_MCLK_A - EVENTOUT PC7 - TSC_G4_IO2 DCMI_D1 LCD_SEG25 SDMMC1_D7 SAI2_MCLK_B - EVENTOUT PC8 - TSC_G4_IO3 DCMI_D2 LCD_SEG26 SDMMC1_D0 - - EVENTOUT PC9 - TSC_G4_IO4 OTG_FS_NOE LCD_SEG27 SDMMC1_D1 SAI2_EXTCLK TIM8_BKIN2_ COMP1 EVENTOUT PC10 UART4_TX TSC_G3_IO2 DCMI_D8 LCD_COM4/ LCD_SEG28/ LCD_SEG40 SDMMC1_D2 SAI2_SCK_B - EVENTOUT PC11 UART4_RX TSC_G3_IO3 DCMI_D4 LCD_COM5/ LCD_SEG29/ LCD_SEG41 SDMMC1_D3 SAI2_MCLK_B - EVENTOUT PC12 UART5_TX TSC_G3_IO4 DCMI_D9 LCD_COM6/ LCD_SEG30/ LCD_SEG42 SDMMC1_CK SAI2_SD_B - EVENTOUT PC13 - - - - - - - EVENTOUT PC14 - - - - - - - EVENTOUT PC15 - - - - - - - EVENTOUT Port DS11585 Rev 16 Port C STM32L496xx AF8 Pinouts and pin description 108/284 Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/ FMC/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENTOUT PD0 - CAN1_RX - - FMC_D2 - - EVENTOUT PD1 - CAN1_TX - - FMC_D3 - - EVENTOUT PD2 UART5_RX TSC_SYNC DCMI_D11 LCD_COM7/ LCD_SEG31/ LCD_SEG43 SDMMC1_ CMD - - EVENTOUT PD3 - - QUADSPI_BK2_NCS - FMC_CLK - - EVENTOUT PD4 - - QUADSPI_BK2_IO0 - FMC_NOE - - EVENTOUT PD5 - - QUADSPI_BK2_IO1 - FMC_NWE - - EVENTOUT PD6 - - QUADSPI_BK2_IO2 - FMC_NWAIT SAI1_SD_A - EVENTOUT PD7 - - QUADSPI_BK2_IO3 - FMC_NE1 - - EVENTOUT PD8 - - DCMI_HSYNC LCD_SEG28 FMC_D13 - - EVENTOUT PD9 - - DCMI_PIXCLK LCD_SEG29 FMC_D14 SAI2_MCLK_A - EVENTOUT PD10 - TSC_G6_IO1 - LCD_SEG30 FMC_D15 SAI2_SCK_A - EVENTOUT PD11 - TSC_G6_IO2 - LCD_SEG31 FMC_A16 SAI2_SD_A LPTIM2_ETR EVENTOUT PD12 - TSC_G6_IO3 - LCD_SEG32 FMC_A17 SAI2_FS_A LPTIM2_IN1 EVENTOUT PD13 - TSC_G6_IO4 - LCD_SEG33 FMC_A18 - LPTIM2_OUT EVENTOUT PD14 - - - LCD_SEG34 FMC_D0 - - EVENTOUT PD15 - - - LCD_SEG35 FMC_D1 - - EVENTOUT Port DS11585 Rev 16 Port D 109/284 Pinouts and pin description AF8 STM32L496xx Table 17. Alternate function AF8 to AF15(1) (continued) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/ FMC/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENTOUT PE0 - - DCMI_D2 LCD_SEG36 FMC_NBL0 - TIM16_CH1 EVENTOUT PE1 - - DCMI_D3 LCD_SEG37 FMC_NBL1 - TIM17_CH1 EVENTOUT PE2 - TSC_G7_IO1 - LCD_SEG38 FMC_A23 SAI1_MCLK_A - EVENTOUT PE3 - TSC_G7_IO2 - LCD_SEG39 FMC_A19 SAI1_SD_B - EVENTOUT PE4 - TSC_G7_IO3 DCMI_D4 - FMC_A20 SAI1_FS_A - EVENTOUT PE5 - TSC_G7_IO4 DCMI_D6 - FMC_A21 SAI1_SCK_A - EVENTOUT PE6 - - DCMI_D7 - FMC_A22 SAI1_SD_A - EVENTOUT PE7 - - - - FMC_D4 SAI1_SD_B - EVENTOUT PE8 - - - - FMC_D5 SAI1_SCK_B - EVENTOUT PE9 - - - - FMC_D6 SAI1_FS_B - EVENTOUT PE10 - TSC_G5_IO1 QUADSPI_CLK - FMC_D7 SAI1_MCLK_B - EVENTOUT PE11 - TSC_G5_IO2 QUADSPI_BK1_NCS - FMC_D8 - - EVENTOUT PE12 - TSC_G5_IO3 QUADSPI_BK1_IO0 - FMC_D9 - - EVENTOUT PE13 - TSC_G5_IO4 QUADSPI_BK1_IO1 - FMC_D10 - - EVENTOUT PE14 - - QUADSPI_BK1_IO2 - FMC_D11 - - EVENTOUT PE15 - - QUADSPI_BK1_IO3 - FMC_D12 - - EVENTOUT Port DS11585 Rev 16 Port E Pinouts and pin description 110/284 Table 17. Alternate function AF8 to AF15(1) (continued) STM32L496xx AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/ FMC/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENTOUT PF0 - - - - FMC_A0 - - EVENTOUT PF1 - - - - FMC_A1 - - EVENTOUT PF2 - - - - FMC_A2 - - EVENTOUT PF3 - - - - FMC_A3 - - EVENTOUT PF4 - - - - FMC_A4 - - EVENTOUT PF5 - - - - FMC_A5 - - EVENTOUT PF6 - - QUADSPI_BK1_IO3 - - SAI1_SD_B - EVENTOUT PF7 - - QUADSPI_BK1_IO2 - - SAI1_MCLK_B - EVENTOUT PF8 - - QUADSPI_BK1_IO0 - - SAI1_SCK_B - EVENTOUT PF9 - - QUADSPI_BK1_IO1 - - SAI1_FS_B TIM15_CH1 EVENTOUT PF10 - - DCMI_D11 - - - TIM15_CH2 EVENTOUT PF11 - - DCMI_D12 - - - - EVENTOUT PF12 - - - - FMC_A6 - - EVENTOUT PF13 - - - - FMC_A7 - - EVENTOUT PF14 - TSC_G8_IO1 - - FMC_A8 - - EVENTOUT PF15 - TSC_G8_IO2 - - FMC_A9 - - EVENTOUT Port DS11585 Rev 16 Port F 111/284 Pinouts and pin description AF8 STM32L496xx Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/ FMC/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENTOUT PG0 - TSC_G8_IO3 - - FMC_A10 - - EVENTOUT PG1 - TSC_G8_IO4 - - FMC_A11 - - EVENTOUT PG2 - - - - FMC_A12 SAI2_SCK_B - EVENTOUT PG3 - - - - FMC_A13 SAI2_FS_B - EVENTOUT PG4 - - - - FMC_A14 SAI2_MCLK_B - EVENTOUT PG5 LPUART1_ CTS - - - FMC_A15 SAI2_SD_B - EVENTOUT PG6 LPUART1_ RTS_DE - - - - - - EVENTOUT PG7 LPUART1_TX - - - FMC_INT SAI1_MCLK_A - EVENTOUT PG8 LPUART1_RX - - - - - - EVENTOUT PG9 - - - - FMC_NCE/ FMC_NE2 SAI2_SCK_A TIM15_CH1N EVENTOUT PG10 - - - - FMC_NE3 SAI2_FS_A TIM15_CH1 EVENTOUT PG11 - - - - - SAI2_MCLK_A TIM15_CH2 EVENTOUT PG12 - - - - FMC_NE4 SAI2_SD_A - EVENTOUT PG13 - - - - FMC_A24 - - EVENTOUT PG14 - - - - FMC_A25 - - EVENTOUT PG15 - - DCMI_D13 - - - - EVENTOUT Port DS11585 Rev 16 Port G STM32L496xx AF8 Pinouts and pin description 112/284 Table 17. Alternate function AF8 to AF15(1) (continued) AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/ FMC/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENTOUT PH0 - - - - - - - EVENTOUT PH1 - - - - - - - EVENTOUT PH2 - - - - - - - EVENTOUT PH3 - - - - - - - EVENTOUT PH4 - - - - - - - EVENTOUT PH5 - - DCMI_PIXCLK - - - - EVENTOUT PH6 - - DCMI_D8 - - - - EVENTOUT PH7 - - DCMI_D9 - - - - EVENTOUT PH8 - - DCMI_HSYNC - - - - EVENTOUT PH9 - - DCMI_D0 - - - - EVENTOUT PH10 - - DCMI_D1 - - - - EVENTOUT PH11 - - DCMI_D2 - - - - EVENTOUT PH12 - - DCMI_D3 - - - - EVENTOUT PH13 - CAN1_TX - - - - - EVENTOUT PH14 - - DCMI_D4 - - - - EVENTOUT PH15 - - DCMI_D11 - - - - EVENTOUT Port DS11585 Rev 16 Port H 113/284 Pinouts and pin description AF8 STM32L496xx Table 17. Alternate function AF8 to AF15(1) (continued) AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 UART4/5/ LPUART1/ CAN2 CAN1/TSC CAN2/ OTG_FS/DCMI/ QUADSPI LCD SDMMC/ COMP1/2/ FMC/SWPMI1 SAI1/2 TIM2/15/16/17/ LPTIM2 EVENTOUT PI0 - - DCMI_D13 - - - - EVENTOUT PI1 - - DCMI_D8 - - - - EVENTOUT PI2 - - DCMI_D9 - - - - EVENTOUT PI3 - - DCMI_D10 - - - - EVENTOUT PI4 - - DCMI_D5 - - - - EVENTOUT PI5 - - DCMI_VSYNC - - - - EVENTOUT PI6 - - DCMI_D6 - - - - EVENTOUT PI7 - - DCMI_D7 - - - - EVENTOUT PI8 - - DCMI_D12 - - - - EVENTOUT PI9 - CAN1_RX - - - - - EVENTOUT PI10 - - - - - - - EVENTOUT PI11 - - - - - - - EVENTOUT Port Port I Pinouts and pin description 114/284 Table 17. Alternate function AF8 to AF15(1) (continued) DS11585 Rev 16 1. Refer to Table 16 for AF0 to AF7. STM32L496xx STM32L496xx 5 Memory mapping Memory mapping Figure 20. STM32L496xx memory map 0xFFFF FFFF 0xBFFF FFFF Reserved Cortex™-M4 with FPU Internal Peripherals 7 0xA000 1400 QUADSPI registers 0xA000 1000 FMC registers 0xA000 0000 0xE000 0000 0x5FFF FFFF Reserved 6 0x5006 0C00 AHB2 0x4800 0000 Reserved 0xC000 0000 0x4002 4400 AHB1 FMC and QUADSPI registers 5 0x4002 0000 0x4001 6400 0xA000 0000 4 QUADSPI flash bank 0x4001 0000 FMC bank3 0x4000 0000 Reserved APB2 Reserved 0x4000 9800 0x9000 0000 APB1 0x1FFF FFFF 0x8000 0000 Reserved 0x1FFF F810 Option Bytes 3 0x1FFF F800 Reserved FMC bank1 0x1FFF F000 System memory 0x6000 0000 0x1FFF 8000 Reserved 0x1FFF 7810 Options Bytes 2 0x1FFF 7800 Reserved 0x1FFF 7400 Peripherals OTP area 0x4000 0000 0x1FFF 7000 System memory 1 0x2004 0000 0x1FFF 0000 SRAM2 Reserved 0x1001 0000 SRAM1 SRAM2 0x2000 0000 0x1000 0000 Reserved 0 0x0810 0000 CODE Flash memory 0x0800 0000 0x0000 0000 0x0010 0000 0x0000 0000 Reserved Reserved Flash, system memory or SRAM, depending on BOOT configuration MSv38032V1 DS11585 Rev 16 115/284 119 Memory mapping STM32L496xx Table 18. STM32L496xx memory map and peripheral register boundary addresses(1) Bus AHB4 AHB3 - AHB2 - AHB1 116/284 Boundary address Size (bytes) Peripheral 0xA000 1000 - 0xA000 13FF 1K QUADSPI 0xA000 0400 - 0xA000 0FFF 3K Reserved 0xA000 0000 - 0xA000 03FF 1K FMC 0x5006 0C00 - 0x5FFF FFFF ~260 M 0x5006 0800 - 0x5006 0BFF 1K RNG 0x5005 0400 - 0x5005 FFFF 62 K Reserved 0x5005 0000 - 0x5005 03FF 1K DCMI 0x5004 0400 - 0x5004 FFFF 62 K Reserved 0x5004 0000 - 0x5004 03FF 1K ADC 0x5000 0000 - 0x5003 FFFF 16 K OTG_FS 0x4800 2400 - 0x4FFF FFFF ~127 M Reserved 0x4800 2000 - 0x4800 23FF 1K GPIOI 0x4800 1C00 - 0x4800 1FFF 1K GPIOH 0x4800 1800 - 0x4800 1BFF 1K GPIOG 0x4800 1400 - 0x4800 17FF 1K GPIOF 0x4800 1000 - 0x4800 13FF 1K GPIOE 0x4800 0C00 - 0x4800 0FFF 1K GPIOD 0x4800 0800 - 0x4800 0BFF 1K GPIOC 0x4800 0400 - 0x4800 07FF 1K GPIOB 0x4800 0000 - 0x4800 03FF 1K GPIOA 0x4002 BC00 - 0x47FF FFFF ~127 M 0x4002 B000 - 0x4002 BBFF 3K DMA2D 0x4002 4400 - 0x4002 AFFF 26 K Reserved 0x4002 4000 - 0x4002 43FF 1K TSC 0x4002 3400 - 0x4002 3FFF 1K Reserved 0x4002 3000 - 0x4002 33FF 1K CRC 0x4002 2400 - 0x4002 2FFF 3K Reserved 0x4002 2000 - 0x4002 23FF 1K FLASH registers 0x4002 1400 - 0x4002 1FFF 3K Reserved 0x4002 1000 - 0x4002 13FF 1K RCC 0x4002 0800 - 0x4002 0FFF 2K Reserved 0x4002 0400 - 0x4002 07FF 1K DMA2 0x4002 0000 - 0x4002 03FF 1K DMA1 DS11585 Rev 16 Reserved Reserved STM32L496xx Memory mapping Table 18. STM32L496xx memory map and peripheral register boundary addresses(1) (continued) Bus APB2 Boundary address Size (bytes) Peripheral 0x4001 6400 - 0x4001 FFFF 39 K Reserved 0x4001 6000 - 0x4001 63FF 1K DFSDM1 0x4001 5C00 - 0x4001 5FFF 1K Reserved 0x4001 5800 - 0x4001 5BFF 1K SAI2 0x4001 5400 - 0x4001 57FF 1K SAI1 0x4001 4C00 - 0x4001 53FF 2K Reserved 0x4001 4800 - 0x4001 4BFF 1K TIM17 0x4001 4400 - 0x4001 47FF 1K TIM16 0x4001 4000 - 0x4001 43FF 1K TIM15 0x4001 3C00 - 0x4001 3FFF 1K Reserved 0x4001 3800 - 0x4001 3BFF 1K USART1 0x4001 3400 - 0x4001 37FF 1K TIM8 0x4001 3000 - 0x4001 33FF 1K SPI1 0x4001 2C00 - 0x4001 2FFF 1K TIM1 0x4001 2800 - 0x4001 2BFF 1K SDMMC1 0x4001 2000 - 0x4001 27FF 2K Reserved 0x4001 1C00 - 0x4001 1FFF 1K FIREWALL 0x4001 0800- 0x4001 1BFF 5K Reserved 0x4001 0400 - 0x4001 07FF 1K EXTI 0x4001 0200 - 0x4001 03FF 0x4001 0030 - 0x4001 01FF 0x4001 0000 - 0x4001 002F DS11585 Rev 16 COMP 1K VREFBUF SYSCFG 117/284 119 Memory mapping STM32L496xx Table 18. STM32L496xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 118/284 Boundary address Size (bytes) Peripheral 0x4000 9800 - 0x4000 FFFF 26 K Reserved 0x4000 9400 - 0x4000 97FF 1K LPTIM2 0x4000 8C00 - 0x4000 93FF 2K Reserved 0x4000 8800 - 0x4000 8BFF 1K SWPMI1 0x4000 8400 - 0x4000 87FF 1K I2C4 0x4000 8000 - 0x4000 83FF 1K LPUART1 0x4000 7C00 - 0x4000 7FFF 1K LPTIM1 0x4000 7800 - 0x4000 7BFF 1K OPAMP 0x4000 7400 - 0x4000 77FF 1K DAC1 0x4000 7000 - 0x4000 73FF 1K PWR 0x4000 6800 - 0x4000 6FFF 1K Reserved 0x4000 6800 - 0x4000 6BFF 1K CAN2 0x4000 6400 - 0x4000 67FF 1K CAN1 0x4000 6000 - 0x4000 63FF 1K CRS 0x4000 5C00- 0x4000 5FFF 1K I2C3 0x4000 5800 - 0x4000 5BFF 1K I2C2 0x4000 5400 - 0x4000 57FF 1K I2C1 0x4000 5000 - 0x4000 53FF 1K UART5 0x4000 4C00 - 0x4000 4FFF 1K UART4 DS11585 Rev 16 STM32L496xx Memory mapping Table 18. STM32L496xx memory map and peripheral register boundary addresses(1) (continued) Bus APB1 Boundary address Size (bytes) Peripheral 0x4000 4800 - 0x4000 4BFF 1K USART3 0x4000 4400 - 0x4000 47FF 1K USART2 0x4000 4000 - 0x4000 43FF 1K Reserved 0x4000 3C00 - 0x4000 3FFF 1K SPI3 0x4000 3800 - 0x4000 3BFF 1K SPI2 0x4000 3400 - 0x4000 37FF 1K Reserved 0x4000 3000 - 0x4000 33FF 1K IWDG 0x4000 2C00 - 0x4000 2FFF 1K WWDG 0x4000 2800 - 0x4000 2BFF 1K RTC 0x4000 2400 - 0x4000 27FF 1K LCD 0x4000 1800 - 0x4000 23FF 3K Reserved 0x4000 1400 - 0x4000 17FF 1K TIM7 0x4000 1000 - 0x4000 13FF 1K TIM6 0x4000 0C00- 0x4000 0FFF 1K TIM5 0x4000 0800 - 0x4000 0BFF 1K TIM4 0x4000 0400 - 0x4000 07FF 1K TIM3 0x4000 0000 - 0x4000 03FF 1K TIM2 1. The gray color is used for reserved boundary addresses. DS11585 Rev 16 119/284 119 Electrical characteristics STM32L496xx 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 21. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 22. Figure 21. Pin loading conditions Figure 22. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19210V1 120/284 DS11585 Rev 16 MS19211V1 STM32L496xx 6.1.6 Electrical characteristics Power supply scheme Figure 23. Power supply scheme VBAT Backup circuitry (LSE, RTC, Backup registers) 1.55 – 3.6 V Power switch 2 x VDD12 1.05 – 1.32 V VDD VCORE n x VDD Regulator GPIOs IN +1 x 4.7 μF Level shifter OUT n x 100 nF IO logic Level shifter VDDIO1 IO logic Kernel logic (CPU, Digital & Memories) n x VSS VDDIO2 m x VDDIO2 VDDIO2 OUT m x100 nF +4.7 μF GPIOs IN m x VSS VDDA VDDA VREF 10 nF +1 μF 100 nF +1 μF VREF+ VREF- ADCs/ DACs/ OPAMPs/ COMPs/ VREFBUF VSSA MSv45701V1 Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DS11585 Rev 16 121/284 244 Electrical characteristics 6.1.7 STM32L496xx Current consumption measurement Figure 24. Current consumption measurement scheme with and without external SMPS power supply IDD_USB IDD_USB VDDUSB VDDUSB IDD_VBAT IDD_VBAT VBAT VBAT IDD IDD IDDA VDD12 SMPS VDD VDD VDDIO2 VDDIO2 IDDA VDDA VDDA MSv45730V1 The IDD_ALL parameters given in Table 26 to Table 48 represent the total MCU consumption including the current supplying VDD, VDDIO2, VDDA, VDDUSB and VBAT. 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 19, Table 20 and Table 21 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand. Table 19. Voltage characteristics(1) Symbol Ratings VDDX - VSS External main supply voltage (including VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT, VREF+) VDD12 - VSS External SMPS supply voltage VIN(2) Max -0.3 4.0 Range 1 -0.3 Range 2 -0.3 VSS-0.3 min (VDD, VDDA, VDDIO2, VDDUSB, VLCD) + 4.0(3)(4) Input voltage on TT_xx pins VSS-0.3 4.0 Input voltage on BOOT0 pin VSS 9.0 VSS-0.3 4.0 DS11585 Rev 16 Unit 1.4 Input voltage on FT_xxx pins Input voltage on any other pins 122/284 Min V STM32L496xx Electrical characteristics Table 19. Voltage characteristics(1) (continued) Symbol Ratings Min Max Unit |∆VDDx| Variations between different VDDX power pins of the same domain - 50 mV |VSSx-VSS| Variations between all the different ground pins(5) - 50 mV VDDX-VSS External main supply voltage (including VDD, VDDA, VDDUSB, VBAT, VREF+) -0.3 4.0 V VREF+ - VDDA Allowed voltage difference for VREF+ > VDDA - 0.4 V 1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 20 for the maximum allowed injected current values. 3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table. 4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled. 5. Include VREF- pin. Table 20. Current characteristics Symbol Ratings Max ∑IVDD Total current into sum of all VDD power lines (source)(1) (2) 150 ∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 150 IVDD(PIN) Maximum current into each VDD power pin (source)(1)(2) 100 IVSS(PIN) IIO(PIN) ∑IIO(PIN) IINJ(PIN)(4) ∑|IINJ(PIN)| Maximum current out of each VSS ground pin (sink)(1) Unit 100 Output current sunk by any I/O and control pin except FT_f 20 Output current sunk by any FT_f pin 20 Output current sourced by any I/O and control pin 20 Total output current sunk by sum of all I/Os and control pins(3) mA 100 (3) Total output current sourced by sum of all I/Os and control pins Injected current on FT_xxx, TT_xx, RST and B pins, except PA4, PA5 100 -5/+0(5) Injected current on PA4, PA5 -5/0 Total injected current (sum of all I/Os and control pins)(6) 25 1. All main power (VDD, VDDA, VDDIO2, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range. 2. Valid also for VDD12 on SMPS package 3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 5. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 19 for the minimum allowed input voltage values. 6. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values). DS11585 Rev 16 123/284 244 Electrical characteristics STM32L496xx Table 21. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 6.3 Operating conditions 6.3.1 General operating conditions Value Unit –65 to +150 °C 150 °C Table 22. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 80 fPCLK1 Internal APB1 clock frequency - 0 80 fPCLK2 Internal APB2 clock frequency - 0 80 VDD Standard operating voltage - VDD12 Standard operating voltage VDDIO2 PG[15:2] I/Os supply voltage VDDA Analog supply voltage Up to 26 MHz 1.05 At least one I/O in PG[15:2] used 1.08 3.6 0 3.6 PG[15:2] not used ADC or COMP used 1.62 DAC or OPAMP used 1.8 VREFBUF used 2.4 USB used USB not used TT_xx I/O BOOT0 VIN All I/O except BOOT0 and TT_xx 124/284 DS11585 Rev 16 1.32 3.6 V 0 1.55 3.6 3.0 3.6 0 3.6 -0.3 VDDIOx+0.3(2) 0 9 -0.3 Min(Min(VDD, VDDA, VDDIO2, VDDUSB, VLCD)+3.6 V, 5.5 V)(3)(4) I/O input voltage MHz 3.6 1.08 Backup operating voltage VDDUSB USB supply voltage (1) Full frequency range ADC, DAC, OPAMP, COMP, VREFBUF not used VBAT 1.71 Unit STM32L496xx Electrical characteristics Table 22. General operating conditions (continued) Symbol PD PD Parameter Conditions Power dissipation at TA = 85 °C for suffix 6(5) - - 625 LQFP100 - - 476 LQFP64 - - 444 - 385 UFBGA132 - - 364 WLCSP100L - - 559 LQFP144 - - 156 LQFP100 - - 119 LQFP64 - - 111 - 96 UFBGA169 UFBGA132 - - 91 WLCSP100L - - 140 Ambient temperature for the suffix 6 version Maximum power dissipation –40 85 Low-power dissipation(6) –40 105 Ambient temperature for the suffix 3 version Maximum power dissipation –40 125 Low-power dissipation(6) –40 130 Suffix 6 version –40 105 Suffix 3 version –40 130 TA TJ Max LQFP144 UFBGA169 Power dissipation at TA = 125 °C for suffix 3(5) Min Junction temperature range Unit mW mW °C °C 1. When RESET is released functionality is guaranteed down to VBOR0 Min. 2. A GPIO with analog input function enabled cannot exceed min(VDDA, VREF+) + 0.3 V. 3. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min(VDD, VDDA, VDDIO2, VDDUSB, VLCD)+3.6 V and 5.5V. 4. For operation with voltage higher than Min (VDD, VDDA, VDDIO2, VDDUSB, VLCD) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled. 5. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.8: Thermal characteristics). 6. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.8: Thermal characteristics). 6.3.2 Operating conditions at power-up / power-down The parameters given in Table 23 are derived from tests performed under the ambient temperature condition summarized in Table 22. Table 23. Operating conditions at power-up / power-down(1) Symbol tVDD tVDDA Parameter Conditions VDD rise time rate - VDD fall time rate VDDA rise time rate - VDDA fall time rate DS11585 Rev 16 Min Max 0 ∞ 10 ∞ 0 ∞ 10 ∞ Unit µs/V µs/V 125/284 244 Electrical characteristics STM32L496xx Table 23. Operating conditions at power-up / power-down(1) (continued) Symbol Parameter Conditions VDDUSB rise time rate tVDDUSB Max 0 ∞ 10 ∞ 0 ∞ 10 ∞ - VDDUSB fall time rate VDDIO2 rise time rate tVDDIO2 Min - VDDIO2 fall time rate Unit µs/V µs/V 1. At Power up, the VDD12 voltage should not be forced externally The requirements for power-up/down sequence specified in Section 3.10.1: Power supply schemes must be respected. 6.3.3 Embedded reset and power control block characteristics The parameters given in Table 24 are derived from tests performed under the ambient temperature conditions summarized in Table 22. Table 24. Embedded reset and power control block characteristics Symbol tRSTTEMPO(2) 126/284 Parameter Reset temporization after BOR0 is detected VBOR0(2) Brown-out reset threshold 0 VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 VBOR3 Brown-out reset threshold 3 VBOR4 Brown-out reset threshold 4 VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 Conditions(1) Min Typ Max Unit - 250 400 μs Rising edge 1.62 1.66 1.7 Falling edge 1.6 1.64 1.69 Rising edge 2.06 2.1 2.14 Falling edge 1.96 2 2.04 Rising edge 2.26 2.31 2.35 Falling edge 2.16 2.20 2.24 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.85 2.90 2.95 Falling edge 2.76 2.81 2.86 Rising edge 2.1 2.15 2.19 Falling edge 2 2.05 2.1 Rising edge 2.26 2.31 2.36 Falling edge 2.15 2.20 2.25 Rising edge 2.41 2.46 2.51 Falling edge 2.31 2.36 2.41 Rising edge 2.56 2.61 2.66 Falling edge 2.47 2.52 2.57 Rising edge 2.69 2.74 2.79 Falling edge 2.59 2.64 2.69 VDD rising DS11585 Rev 16 V V V V V V V V V V STM32L496xx Electrical characteristics Table 24. Embedded reset and power control block characteristics (continued) Conditions(1) Min Typ Max Rising edge 2.85 2.91 2.96 Falling edge 2.75 2.81 2.86 Rising edge 2.92 2.98 3.04 Falling edge 2.84 2.90 2.96 Hysteresis in continuous Hysteresis voltage of BORH0 mode - 20 - Hysteresis in other mode - 30 - Symbol Parameter VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Vhyst_BORH0 Unit V V mV Hysteresis voltage of BORH (except BORH0) and PVD - - 100 - mV BOR(3) (except BOR0) and IDD (2) (BOR_PVD) PVD consumption from VDD - - 1.1 1.6 µA Vhyst_BOR_PVD VPVM3 VDDA peripheral voltage monitoring Rising edge 1.61 1.65 1.69 Falling edge 1.6 1.64 1.68 VPVM4 VDDA peripheral voltage monitoring Rising edge 1.78 1.82 1.86 Falling edge 1.77 1.81 1.85 V V Vhyst_PVM3 PVM3 hysteresis - - 10 - mV Vhyst_PVM4 PVM4 hysteresis - - 10 - mV IDD PVM1 and PVM2 (PVM1/PVM2) consumption from VDD (2) - - 0.2 - µA IDD PVM3 and PVM4 (PVM3/PVM4) consumption from VDD (2) - - 2 - µA 1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes. 2. Guaranteed by design. 3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables. DS11585 Rev 16 127/284 244 Electrical characteristics 6.3.4 STM32L496xx Embedded voltage reference The parameters given in Table 25 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 22. Table 25. Embedded internal voltage reference Symbol VREFINT Parameter Conditions Internal reference voltage –40 °C < TA < +130 °C Min Typ Max Unit 1.182 1.212 1.232 V tS_vrefint (1) ADC sampling time when reading the internal reference voltage - 4(2) - - µs tstart_vrefint Start time of reference voltage buffer when ADC is enable - - 8 12(2) µs - - 12.5 20(2) µA - 5 7.5(2) mV - 30 50(2) ppm/°C ppm ppm/V VREFINT buffer consumption IDD(VREFINTBUF) from VDD when converted by ADC ∆VREFINT TCoeff ACoeff VDDCoeff Internal reference voltage spread over the temperature range VDD = 3 V Average temperature coefficient –40°C < TA < +130°C Long term stability 1000 hours, T = 25°C - 300 1000(2) Average voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) 24 25 26 49 50 51 74 75 76 VREFINT_DIV1 1/4 reference voltage VREFINT_DIV2 1/2 reference voltage VREFINT_DIV3 3/4 reference voltage - 1. The shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. 128/284 DS11585 Rev 16 % VREFINT STM32L496xx Electrical characteristics Figure 25. VREFINT versus temperature V 1.235 1.23 1.225 1.22 1.215 1.21 1.205 1.2 1.195 1.19 1.185 -40 -20 0 20 40 Mean 60 Min 80 100 120 °C Max MSv40169V1 6.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 24. Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode • All peripherals are disabled except when explicitly mentioned • The flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0351 reference manual). • When the peripherals are enabled fPCLK = fHCLK The parameters given in Table 26 to Table 49 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 22: General operating conditions. DS11585 Rev 16 129/284 244 Conditions Symbol Parameter - Voltage scaling DS11585 Rev 16 IDD_ALL (LPRun) Unit 85 °C 2.9 3.0 3.3 3.8 4.7 2.53 1.9 2.0 2.2 2.7 3.7 1.29 1.74 1.0 1.1 1.4 1.8 2.8 0.68 0.9 1.35 0.6 0.7 0.9 1.4 2.4 0.36 0.48 0.7 1.15 0.4 0.5 0.7 1.2 2.2 0.23 0.26 0.38 0.6 1.06 0.3 0.4 0.6 1.1 2.0 100 kHz 0.14 0.17 0.3 0.52 0.97 0.2 0.3 0.5 1.0 2.0 80 MHz 9.44 9.5 9.67 9.93 10.4 10.3 10.4 10.7 11.3 12.4 72 MHz 8.52 8.59 8.75 9.01 9.53 9.3 9.4 9.7 10.3 11.4 64 MHz 7.61 7.67 7.83 8.09 8.61 8.3 8.4 8.7 9.3 10.4 Range 1 48 MHz 5.72 5.78 5.94 6.2 6.72 6.3 6.4 6.7 7.3 8.4 32 MHz 3.87 3.92 4.07 4.33 4.84 4.2 4.4 4.7 5.2 6.3 24 MHz 2.94 2.99 3.14 3.39 3.9 3.2 3.4 3.6 4.2 5.3 16 MHz 2.01 2.06 2.2 2.45 2.95 2.2 2.3 2.6 3.2 4.2 2 MHz 274 307 444 678 1150 318 425 656 1167 2197 1 MHz 158 195 328 564 1040 195 309 558 1047 2084 400 kHz 88.2 123 256 490 969 116 232 485 973 2012 100 kHz 63 90.6 223 457 934 79 195 447 942 1975 fHCLK = fHSE up to 48MHz included, bypass Supply mode current in PLL ON above Run mode 48 MHz all peripherals disable Supply current in fHCLK = fMSI Low-power all peripherals disable run mode 25 °C 55 °C 85 °C 26 MHz 2.65 2.69 2.82 3.05 3.51 16 MHz 1.68 1.72 1.85 2.07 8 MHz 0.91 0.94 1.07 4 MHz 0.52 0.55 2 MHz 0.33 1 MHz fHCLK 1. Guaranteed by characterization results, unless otherwise specified. 105 °C 125 °C 25 °C 105 °C 125 °C mA µA STM32L496xx 55 °C Range 2 IDD_ALL(Run) MAX(1) TYP Electrical characteristics 130/284 Table 26. Current consumption in Run and Low-power run modes, code with data processing running from flash, ART enable (Cache ON Prefetch OFF) Conditions(1) Symbol Unit - IDD_ALL(Run) TYP Parameter Supply current in Run mode fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable DS11585 Rev 16 fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 80 MHz 3.39 3.42 3.48 3.57 3.74 72 MHz 3.06 3.09 3.15 3.24 3.43 64 MHz 2.74 2.76 2.81 2.91 3.10 48 MHz 2.06 2.08 2.14 2.23 2.42 32 MHz 1.39 1.41 1.46 1.56 1.74 24 MHz 1.06 1.07 1.13 1.22 1.40 16 MHz 0.72 0.74 0.79 0.88 1.06 8 MHz 0.39 0.41 0.46 0.56 0.75 4 MHz 0.22 0.24 0.29 0.39 0.58 2 MHz 0.14 0.16 0.21 0.30 0.50 1 MHz 0.10 0.11 0.16 0.26 0.46 100 kHz 0.06 0.07 0.13 0.22 0.42 STM32L496xx Table 27. Current consumption in Run modes, code with data processing running from flash, (ART enable Cache ON Prefetch OFF) and power supplied (by external SMPS (VDD12 = 1.10 V) mA 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V Electrical characteristics 131/284 Conditions Symbol Parameter - Voltage scaling Range 2 IDD_ALL(Run) DS11585 Rev 16 IDD_ALL (LPRun) fHCLK = fHSE up to 48MHz included, bypass Supply mode current in PLL ON above Run mode 48 MHz all peripherals disable MAX(1) TYP Unit fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 26 MHz 3.1 3.14 3.28 3.51 3.98 3.5 3.6 3.8 4.3 5.3 16 MHz 2.19 2.23 2.36 2.59 3.05 2.5 2.6 2.8 3.3 4.3 8 MHz 1.22 1.26 1.39 1.61 2.07 1.4 1.5 1.7 2.2 3.2 4 MHz 0.69 0.73 0.85 1.08 1.53 0.8 0.9 1.1 1.6 2.6 2 MHz 0.41 0.44 0.57 0.79 1.24 0.5 0.6 0.8 1.3 2.3 1 MHz 0.27 0.3 0.43 0.65 1.1 0.3 0.4 0.6 1.1 2.1 100 kHz 0.14 0.18 0.3 0.52 0.97 0.2 0.3 0.5 1.0 2.0 80 MHz 10 10.1 10.3 10.5 11.1 11.1 11.2 11.6 12.2 13.31 72 MHz 9.02 9.1 9.29 9.59 10.1 10 10.1 10.5 11.0 12.2 64 MHz Range 1 48 MHz 8.94 9.02 9.2 9.48 10 9.9 10.1 10.4 11.0 12.1 7.51 7.59 7.77 8.05 8.59 8.4 8.6 8.9 9.5 10.6 32 MHz 5.38 5.45 5.62 5.88 6.41 6.0 6.2 6.5 7.0 8.2 24 MHz 4.07 4.12 4.28 4.54 5.06 4.5 4.7 5.0 5.5 6.6 16 MHz 2.86 2.92 3.07 3.33 3.84 3.2 3.3 3.6 4.2 5.3 2 MHz 378 412 549 782 1260 436 538 761 1287 2317 1 MHz 213 246 381 618 1100 255 367 609. 1105 2138 400 kHz 101 144 277 514 989 141 256 507 995 2033 100 kHz 62 95.8 228 463 939 85 201 454 947 1982 Supply current in fHCLK = fMSI Low-power all peripherals disable run Electrical characteristics 132/284 Table 28. Current consumption in Run and Low-power run modes, code with data processing running from flash, ART disable mA µA 1. Guaranteed by characterization results, unless otherwise specified. STM32L496xx Conditions(1) Symbol - IDD_ALL(Run) TYP Parameter Supply current in Run mode fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK 25 °C 55 °C DS11585 Rev 16 85 °C 105 °C 125 °C 80 MHz 3.59 3.63 3.70 3.77 3.99 72 MHz 3.24 3.27 3.34 3.45 3.63 64 MHz 3.21 3.24 3.31 3.41 3.59 48 MHz 2.70 2.73 2.79 2.89 3.09 32 MHz 1.93 1.96 2.02 2.11 2.30 24 MHz 1.46 1.48 1.54 1.63 1.82 16 MHz 1.03 1.05 1.10 1.20 1.38 8 MHz 0.53 0.54 0.60 0.69 0.89 4 MHz 0.30 0.31 0.37 0.47 0.66 2 MHz 0.18 0.19 0.25 0.34 0.53 1 MHz 0.12 0.13 0.19 0.28 0.47 100 kHz 0.06 0.08 0.13 0.22 0.42 Uni t STM32L496xx Table 29. Current consumption in Run modes, code with data processing running from flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) mA 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V Electrical characteristics 133/284 Conditions Symbol Parameter - Voltage scaling Range 2 IDD_ALL(Run) Supply current in Run mode DS11585 Rev 16 fHCLK = fHSE up to 48MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Range 1 IDD_ALL (LPRun) Supply current in low-power run mode fHCLK = fMSI all peripherals disable FLASH in power-down MAX(1) TYP fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 26 MHz 2.72 2.76 2.89 3.12 3.58 3.0 3.1 3.4 3.8 4.8 16 MHz 1.73 1.76 1.89 2.12 2.58 1.9 2.0 2.3 2.7 3.7 8 MHz 0.93 0.96 1.09 1.31 1.77 1.0 1.1 1.42 1.8 2.8 4 MHz 0.53 0.57 0.69 0.91 1.36 0.6 0.7 0.9 1.4 2.4 2 MHz 0.33 0.36 0.49 0.71 1.16 0.4 0.5 0.7 1.2 2.2 1 MHz 0.23 0.26 0.39 0.61 1.06 0.2 0.4 0.6 1.1 2.1 100 kHz 0.14 0.17 0.3 0.52 0.97 0.2 0.3 0.5 1.0 2.0 80 MHz 9.71 9.78 9.95 10.2 10.8 10.6 10.7 11.1 11.6 12.7 72 MHz 8.77 8.84 9 9.27 9.8 9.6 9.7 10.0 10.6 11.7 64 MHz 7.82 7.89 8.05 8.32 8.84 8.5 8.7 9.0 9.5 10.6 48 MHz 5.87 5.93 6.1 6.36 6.88 6.4 6.6 6.9 7.4 8.5 32 MHz 3.97 4.03 4.18 4.44 4.95 4.4 4.5 4.8 5.3 6.4 24 MHz 3.02 3.07 3.22 3.47 3.99 3.3 3.5 3.7 4.3 5.4 16 MHz 2.07 2.11 2.26 2.51 3.02 2.3 2.4 2.7 3.2 4.3 2 MHz 258 296 430 665 1140 295 402 634 1154 2180 1 MHz 136 180 314 550 1020 170 283 530 1034 2065 400 kHz 78.5 109 241 475 951 90 206 458 958 1991 100 kHz 37.4 78.1 208 440 918 53 171 429 925 1957 Unit Electrical characteristics 134/284 Table 30. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 mA µA 1. Guaranteed by characterization results, unless otherwise specified. STM32L496xx Conditions(1) Symbol TYP Parameter Unit - fHCLK = fHSE up to 48MHz included, bypass mode IDD_ALL(Run) Supply current in Run mode PLL ON above 48 MHz all peripherals disable DS11585 Rev 16 25 °C 55 °C 85 °C 80 MHz 3.49 3.52 3.58 3.67 3.88 72 MHz 3.15 3.18 3.24 3.33 3.52 64 MHz 2.81 2.84 2.89 2.99 3.18 48 MHz 2.11 2.13 2.19 2.29 2.47 32 MHz 1.43 1.45 1.50 1.60 1.78 24 MHz 1.09 1.10 1.16 1.25 1.43 16 MHz 0.74 0.76 0.81 0.90 1.09 8 MHz 0.40 0.41 0.47 0.57 0.76 4 MHz 0.23 0.25 0.30 0.39 0.59 2 MHz 0.14 0.16 0.21 0.31 0.50 1 MHz 0.10 0.11 0.17 0.26 0.46 100 kHz 0.06 0.07 0.13 0.22 0.42 fHCLK 105 °C 125 °C STM32L496xx Table 31. Current consumption in Run, code with data processing running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) mA 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V Electrical characteristics 135/284 Electrical characteristics STM32L496xx Table 32. Typical current consumption in Run and Low-power run modes, with different codes running from flash, ART enable (Cache ON Prefetch OFF) Conditions Supply current in Run mode TYP Voltage scaling - Range 2 fHCLK = 26 MHz IDD_ALL (Run) Parameter fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Range 1 fHCLK = 80 MHz Symbol Code 2.65 102 Coremark 2.97 114 Dhrystone 2.1 3.1 IDD_ALL (LPRun) mA 119 Fibonacci 2.9 112 While(1) 2.43 93 9.44 118 Coremark 10.6 133 Dhrystone 2.1 10.9 Fibonacci 10.3 129 While(1) 8.66 108 274 137 Reduced code(1) code(1) mA Unit 25 °C Reduced code(1) Reduced Supply current in fHCLK = fMSI = 2 MHz Low-power all peripherals disable run 25 °C TYP Unit 136 Coremark 307 Dhrystone 2.1 308 Fibonacci 273 137 While(1) 258 129 µA/MHz µA/MHz 154 µA 154 µA/MHz 1. Reduced code used for characterization results provided in Table 26, Table 28, Table 30. Table 33. Typical current consumption in Run, with different codes running from flash, ART enable (Cache ON Prefetch OFF) and power supplied (by external SMPS (VDD12 = 1.10 V) Conditions(1) Supply current in Run mode - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling fHCLK = 26 MHz IDD_ALL (Run) Parameter fHCLK = 80 MHz Symbol TYP TYP Unit Code 25 °C Reduced code(2) 1.14 44 Coremark 1.28 49 Dhrystone 2.1 1.34 51 Fibonacci 1.25 48 While(1) 1.05 Reduced code(2) 3.39 Coremark 3.81 48 Dhrystone 2.1 3.92 49 Fibonacci 3.70 46 While(1) 3.11 39 mA Unit 25 °C 40 42 µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V 2. Reduced code used for characterization results provided in Table 26, Table 28, Table 30. 136/284 DS11585 Rev 16 STM32L496xx Electrical characteristics Table 34. Typical current consumption in Run, with different codes running from flash, ART enable (Cache ON Prefetch OFF) and power supplied (by external SMPS (VDD12 = 1.05 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode - Voltage scaling fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK = 26 MHz Symbol TYP TYP Unit Code 25 °C Reduced code(2) 1.04 40 Coremark 1.17 45 Dhrystone 2.1 1.22 Fibonacci 1.14 44 While(1) 0.96 37 mA Unit 25 °C 47 µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.05 V 2. Reduced code used for characterization results provided in Table 26, Table 28, Table 30. Table 35. Typical current consumption in Run and Low-power run modes, with different codes running from flash, ART disable Conditions IDD_ALL (Run) IDD_ALL (LPRun) Parameter Supply current in Run mode - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Voltage scaling Range 1 Range 2 fHCLK = 80 MHz fHCLK = 26 MHz Symbol Supply current in fHCLK = fMSI = 2 MHz Low-power all peripherals disable run TYP Code 25 °C TYP Unit 25 °C Reduced code(1) 3.1 119 Coremark 2.85 110 Dhrystone 2.1 2.86 mA 110 Fibonacci 2.63 101 While(1) 2.42 93.1 10 125 9.33 117 Reduced code(1) Coremark mA Dhrystone 2.1 9.4 Fibonacci 8.66 108 118 While(1) 8.61 108 Reduced code(1) 378 189 Coremark 412 Dhrystone 2.1 418 Fibonacci 392 196 While(1) 266 133 Unit µA/MHz µA/MHz 206 µA 209 µA/MHz 1. Reduced code used for characterization results provided in Table 26, Table 28, Table 30. DS11585 Rev 16 137/284 244 Electrical characteristics STM32L496xx Table 36. Typical current consumption in Run modes, with different codes running from flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode Voltage scaling - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP Code 25 °C Reduced code(2) 1.34 TYP Unit 25 °C Unit 51 Coremark 1.23 47 Dhrystone 2.1 1.23 47 Fibonacci 1.13 44 While(1) 1.04 Reduced code(1) 3.59 mA 40 45 Coremark 3.35 42 Dhrystone 2.1 3.38 42 Fibonacci 3.11 39 While(1) 3.10 39 µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V 2. Reduced code used for characterization results provided in Table 26, Table 28, Table 30. Table 37. Typical current consumption in Run modes, with different codes running from flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals Voltage scaling fHCLK = 26 MHz Symbol TYP Code 25 °C Reduced code(2) 1.22 TYP Unit 25 °C Unit 47 Coremark 1.12 Dhrystone 2.1 1.12 43 Fibonacci 1.03 40 While(1) 0.95 37 mA 43 µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.05 V 2. Reduced code used for characterization results provided in Table 26, Table 28, Table 30. 138/284 DS11585 Rev 16 STM32L496xx Electrical characteristics Table 38. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 Conditions IDD_ALL (Run) IDD_ALL (LPRun) Parameter Voltage scaling - Range 1 Range 2 fHCLK = 80 MHz fHCLK = 26 MHz Symbol fHCLK = fHSE up to 48 MHz included, Supply bypass mode current in PLL ON above Run mode 48 MHz all peripherals disable Supply current in fHCLK = fMSI = 2 MHz Low-power all peripherals disable run TYP Code Reduced code(1) 25 °C TYP Unit 2.72 Coremark 2.72 Dhrystone 2.1 2.65 Fibonacci 2.47 25 °C 105 105 mA 102 2.37 91 Reduced code(1) 9.71 121 9.7 Dhrystone 2.1 9.48 µA/MHz 95 While(1) Coremark Unit 121 mA 119 Fibonacci 8.79 110 While(1) 8.45 106 Reduced code(1) 258 129 Coremark 268 134 Dhrystone 2.1 240 Fibonacci 230 115 While(1) 255 128 µA 120 µA/MHz µA/MHz 1. Reduced code used for characterization results provided in Table 26, Table 28, Table 30. Table 39. Typical current consumption in Run, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode - fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable TYP Voltage scaling fHCLK = 80 MHz fHCLK = 26 MHz Symbol TYP Unit Code 25 °C Reduced code(2) 1.17 45 Coremark 1.17 45 Dhrystone 2.1 1.14 44 Fibonacci 1.07 41 While(1) 1.02 Reduced code(1) 3.49 mA 25 °C 39 44 Coremark 3.49 44 Dhrystone 2.1 3.41 43 Fibonacci 3.16 39 While(1) 3.04 38 Unit µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V 2. Reduced code used for characterization results provided in Table 26, Table 28, Table 30. DS11585 Rev 16 139/284 244 Electrical characteristics STM32L496xx Table 40. Typical current consumption in Run, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.05 V) Conditions(1) IDD_ALL (Run) Parameter Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable TYP Voltage scaling fHCLK = 26 MHz Symbol Code 25 °C Reduced code(2) 1.07 TYP Unit 25 °C Unit 41 Coremark 1.07 Dhrystone 2.1 1.04 41 Fibonacci 0.97 37 While(1) 0.93 36 mA 40 µA/MHz 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.05 V 2. Reduced code used for characterization results provided in Table 26, Table 28, Table 30. 140/284 DS11585 Rev 16 Conditions Symbol Parameter - Voltage scaling Range 2 IDD_ALL (Sleep) DS11585 Rev 16 IDD_ALL (LPSleep) Supply current in sleep mode, fHCLK = fHSE up to 48 MHz included, bypass mode pll ON above 48 MHz all peripherals disable MAX(1) TYP Unit 25 °C 55 °C 85 °C 26 MHz 0.79 0.82 0.95 1.17 1.63 16 MHz 0.54 0.57 0.7 0.92 8 MHz 0.33 0.37 0.49 0.71 4 MHz 0.23 0.26 0.39 2 MHz 0.18 0.21 0.34 fHCLK 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 0.9 1.0 1.2 1.7 2.7 1.38 0.6 0.7 1.0 1.4 2.4 1.17 0.4 0.5 0.7 1.2 2.2 0.61 1.06 0.3 0.4 0.6 1.1 2.1 0.56 1.01 0.2 0.3 0.5 1.0 1.0 1 MHz 0.16 0.19 0.31 0.53 0.99 0.2 0.3 0.5 1.0 1.0 100 kHz 0.13 0.17 0.29 0.51 0.96 0.1 0.3 0.5 1.0 1.9 80 MHz 2.57 2.62 2.76 3.01 3.53 2.8 2.9 3.2 3.8 4.9 72 MHz 2.34 2.38 2.53 2.78 3.29 2.6 2.7 3.0 3.5 4.6 64 MHz Range 1 48 MHz 2.1 2.15 2.29 2.54 3.05 2.3 2.4 2.7 3.3 4.4 1.58 1.63 1.78 2.03 2.54 1.8 1.9 2.2 2.7 3.8 32 MHz 1.11 1.15 1.3 1.54 2.05 1.2 1.4 1.7 2.2 3.3 24 MHz 0.87 0.91 1.06 1.3 1.81 1.0 1.1 1.4 1.9 3.0 16 MHz 0.63 0.67 0.82 1.06 1.56 0.7 0.8 1.1 1.6 2.7 2 MHz 103 140 270 506 985 130 247 500 990 2025 1 MHz 74.2 111 245 476 955 100 215 467 963 1999 400 kHz 60 89.8 224 457 937 79 194 444 941 1975 100 kHz 53.7 84.1 216 448 928 70 185 434 933 1967 Supply current in =f f low-power HCLK MSI all peripherals disable sleep mode mA µA 141/284 Electrical characteristics 1. Guaranteed by characterization results, unless otherwise specified. STM32L496xx Table 41. Current consumption in Sleep and Low-power sleep modes, flash ON Conditions(1) Symbol Unit - IDD_ALL(Sleep) TYP Parameter Supply current in sleep mode, fHCLK = fHSE up to 48 MHz included, bypass mode pll ON above 48 MHz all peripherals disable DS11585 Rev 16 fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 80 MHz 0.92 0.94 0.99 1.08 1.27 72 MHz 0.84 0.86 0.91 1.00 1.18 64 MHz 0.75 0.77 0.82 0.91 1.10 48 MHz 0.57 0.59 0.64 0.73 0.91 32 MHz 0.40 0.41 0.47 0.55 0.74 24 MHz 0.31 0.33 0.38 0.47 0.65 16 MHz 0.23 0.24 0.29 0.38 0.56 8 MHz 0.14 0.16 0.21 0.31 0.50 4 MHz 0.10 0.11 0.17 0.26 0.46 2 MHz 0.08 0.09 0.15 0.24 0.44 1 MHz 0.07 0.08 0.13 0.23 0.43 100 kHz 0.06 0.07 0.13 0.22 0.41 Electrical characteristics 142/284 Table 42. Current consumption in Sleep, flash ON and power supplied by external SMPS (VDD12 = 1.10 V) mA 1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V STM32L496xx Conditions Symbol Parameter Voltage scaling - IDD_ALL (LPSleep) Supply current =f f in low-power HCLK MSI all peripherals disable sleep mode MAX(1) TYP Unit fHCLK 25 °C 55 °C 2 MHz 92.7 124 85 °C 258 105 °C 125 °C 25 °C 487 968 105 55 °C 85 °C 224 474 105 °C 125 °C 969 STM32L496xx Table 43. Current consumption in Low-power sleep modes, flash in power-down 2006 1 MHz 63.5 97.5 223 460 951 75 193 446 942 1975 400 kHz 42.6 75.6 207 443 947 54 171 426 923 1955 100 kHz 31.2 67.6 199 437 905 44 162 420 916 1947 µA 1. Guaranteed by characterization results, unless otherwise specified. Table 44. Current consumption in Stop 2 mode Conditions Symbol Unit DS11585 Rev 16 - LCD disabled IDD_ALL (Stop 2) MAX(1) TYP Parameter Supply current in Stop 2 mode, RTC disabled LCD enabled(2) clocked by LSI VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 1.8 V 2.57 6.86 25.2 60.1 135 2.4 V 2.62 6.91 25.5 60.6 3V 2.69 6.93 25.7 3.6 V 2.7 7.08 1.8 V 2.92 2.4 V 105 °C 125 °C 5.3 16.4 64 154.6 353 137 5.3 16.6 64.9 156.7 359 61.5 140 5.4 16.9 66.3 159.7 366 26.3 62.9 143 5.4 17.4 67.8 163.8 375 7.19 25.3 59.5 135 5.3 16.6 64.8 155.6 355 2.99 7.3 25.6 60.3 136 5.5 16.8 65.9 157.9 360 3V 3.04 7.41 26.1 61.7 140 5.9 17.3 67.1 160.8 367 3.6 V 3.31 7.7 26.8 63.2 143 6.2 17.9 69.1 165.0 376 µA Electrical characteristics 143/284 Conditions Symbol MAX(1) TYP Parameter Unit 55 °C 85 °C 105 °C 125 °C 6.1 17.2 64.8 155.4 354 140 6.2 17.5 65.7 157.6 360 63.5 144 6.5 17.9 67.2 160.6 367 27.7 65.2 147 7.1 18.7 69.0 164.9 376 7.31 25.5 60 135 5.5 16.8 65.1 155.8 355 3.10 7.46 25.8 60.7 137 5.8 17.1 66.3 158.2 360 3V 3.23 7.63 26.4 62.1 141 6.2 17.5 67.6 161.4 367 3.6 V 3.47 7.95 27.1 63.6 144 6.58 18.3 69.5 165.5 376 1.8 V 2.93 7.52 26.2 61.4 139 - - - - - RTC clocked by LSE 2.4 V bypassed at 32768Hz,LCD disabled 3 V 3.1 7.68 26.6 62.1 140 - - - - - 3.3 7.81 26.9 63.4 143 - - - - - 3.6 V 3.48 8.07 27.6 65.0 146 - - - - - 1.8 V 2.86 7.48 26.2 61.4 - - - - - - 2.4 V 3.01 7.56 26.5 62.2 - - - - - - 3V 3.18 7.65 26.8 63.5 - - - - - - 3.6 V 3.31 7.94 27.5 65.1 - - - - - - - RTC clocked by LSI, LCD disabled RTC clocked by LSI, LCD enabled(3) DS11585 Rev 16 Supply current in IDD_ALL(Stop 2 Stop 2 mode, with RTC) RTC enabled RTC clocked by LSE quartz(3) in low drive mode, LCD disabled VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 1.8 V 2.97 7.46 26.2 61.4 139 2.4 V 3.09 7.61 26.5 62.3 3V 3.15 7.81 27 3.6 V 3.4 8.05 1.8 V 2.98 2.4 V Electrical characteristics 144/284 Table 44. Current consumption in Stop 2 mode (continued) µA STM32L496xx Conditions Symbol MAX(1) TYP Parameter Unit VDD 25 °C 55 °C Wakeup clock is MSI = 48 MHz, voltage Range 1. See (4). 3V 1.69 - - - - Wakeup clock is MSI = 4 MHz, voltage Range 2. See (4). 3V 1.35 - - - Wakeup clock is HSI16 = 16 MHz, voltage Range 1. See (4). 3V 1.7 - - - - Supply current IDD_ALL(wake during wakeup up from from Stop 2 Stop 2) mode 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C - - - - - - - - - - - - - - - - - STM32L496xx Table 44. Current consumption in Stop 2 mode (continued) mA DS11585 Rev 16 1. Guaranteed by characterization results, unless otherwise specified. 2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 4. Wakeup with code execution from flash. Average value given for a typical wakeup time as specified in Table 51: Low-power mode wakeup timings. Electrical characteristics 145/284 Symbol Parameter Conditions - IDD_ALL (Stop 1) Supply current in Stop 1 mode, RTC disabled - - LCD disabled LCD enabled(2) clocked by LSI DS11585 Rev 16 LCD disabled RTC clocked by LSI Supply current IDD_ALL in stop 1 (Stop 1 with mode, RTC) RTC enabled RTC clocked by LSE bypassed at 32768 Hz RTC clocked by LSE quartz(3) in low drive mode LCD enabled(2) LCD disabled LCD disabled MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 11.2 30.7 107 243 523 25.4 79.6 287 651 1395 2.4 V 11.3 30.8 108 244 526 25.5 79.8 288 655 1403 3V 11.6 31 108 245 530 25.9 80.5 290 659 1413 3.6 V 11.9 31.5 109 248 536 28.6 81.4 293 665 1428 1.8 V 11.7 29.7 102 234 504 27.1 81.1 288.5 653 1397 2.4 V 11.7 29.9 102 234 506 27.2 81.0 289 656 1405 3V 12.1 29.9 103 234 508 27.4 81.6 291 660 1415 3.6 V 12.2 30.1 103 235 510 28.8 82.4 294 667 1429 1.8 V 11.9 31.1 108 244 524 26.6 80.5 288 652 1396 2.4 V 12.1 31.4 109 245 528 26.7 80.9 289 656 1404 3V 12.4 31.7 109 246 531 27.7 81.6 291 660 1415 3.6 V 12.6 32.3 110 249 537 28.9 82.8 295 667 1429 1.8 V 11.7 30.1 104 235 510 26.7 80.6 288 653 1397 2.4 V 11.8 30.2 104 238 511 26.7 81.1 290 657 1406 3V 11.8 30.5 104 238 515 28.3 81.8 2912 661 1416 3.6 V 12.3 31 105 239 519 30.9 83.0 295 668 1430 1.8 V 11.6 31.3 108 244 524 - - - - - 2.4 V 11.8 31.6 109 245 527 - - - - - 3V 12.3 31.9 109 246 531 - - - - - 3.6 V 12.7 32.5 111 249 537 - - - - - 1.8 V 11.5 31.1 108 244 - - - - - - 2.4 V 11.5 31.4 109 246 - - - - - - 3V 12 31.7 109 247 - - - - - - 3.6 V 12.4 32.3 110 250 - - - - - - Unit µA Electrical characteristics 146/284 Table 45. Current consumption in Stop 1 mode µA STM32L496xx Symbol Conditions Parameter - - Wakeup clock MSI = 48 MHz, voltage Range 1. See (4). Supply current Wakeup clock MSI = 4 MHz, IDD_ALL voltage Range 2. during (wakeup wakeup from See (4). from Stop1) Stop 1 Wakeup clock HSI16 = 16 MHz, voltage Range 1. See (4). MAX(1) TYP VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 3V 0.99 - - - - - - - - - 3V 1.1 - - - - - - - - - 3V 0.95 - - - - - - - - - Unit STM32L496xx Table 45. Current consumption in Stop 1 mode (continued) mA 1. Guaranteed by characterization results, unless otherwise specified. DS11585 Rev 16 2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 4. Wakeup with code execution from flash. Average value given for a typical wakeup time as specified in Table 51: Low-power mode wakeup timings. Table 46. Current consumption in Stop 0 mode Conditions Parameter IDD_ALL (Stop 0) Supply current in Stop 0 mode, RTC disabled VDD 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 127 153 244 404 734 148 218 471 905 1795 2.4 V 129 155 247 407 737 151 221 474 910 1803 3V 131 156 249 409 741 154 224 478 915 1813 3.6 V 133 158 251 412 744 157 228 482 921 1822(2) 1. Guaranteed by characterization results, unless otherwise specified. 2. Guaranteed by test in production. 25 °C 55 °C Unit µA 147/284 Electrical characteristics Symbol MAX(1) TYP Conditions Symbol Parameter Unit - IDD_ALL (Standby) DS11585 Rev 16 IDD_ALL (Standby with RTC) MAX(1) TYP Supply current in Standby mode (backup registers retained), RTC disabled Supply current in Standby mode (backup registers retained), RTC enabled VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 108 299 1343 3822 10353 227 899 4159 13059 36572 2.4 V 118 348 1562 4447 12012 252 1009 4846 15026 41366 3V 133 404 1777 5071 13589 318 1211 6082 17245 46714 3.6 V 171 501 2115 5898 15539 435 1508 7230 19850 52888(2) 1.8 V 296 - - - - - - - - - 2.4 V 349 - - - - - - - - - 3V 411 - - - - - - - - - 3.6 V 506 - - - - - - - - - 1.8 V 377 581 1700 4270 11100 763 1422 5182 13585 36564 RTC clocked by LSI, no 2.4 V independent watchdog 3V 461 700 2020 5030 12900 942 1704 5992 15473 41383 559 843 2390 5990 15500 1166 2032 6938 17889 46728 3.6 V 689 1050 2920 7130 18100 1454 2511 7754 20714 53018 1.8 V 422 - - - - - - - - - 2.4 V 518 - - - - - - - - - 3V 560 - - - - - - - - - 3.6 V 780 - - - - - - - - - No independent watchdog With independent watchdog RTC clocked by LSI, with independent watchdog nA Electrical characteristics 148/284 Table 47. Current consumption in Standby mode nA STM32L496xx Conditions Symbol Parameter Unit - IDD_ALL (Standby with RTC) DS11585 Rev 16 IDD_ALL (SRAM2)(4) IDD_ALL (wakeup from Standby) MAX(1) TYP Supply current in Standby mode (backup registers retained), RTC enabled Supply current to be added in Standby mode when SRAM2 is retained Supply current during wakeup from Standby mode RTC clocked by LSE bypassed at 32768Hz RTC clocked by LSE quartz (3) in low drive mode - Wakeup clock is MSI = 4 MHz. See (5). VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 308 504 1683 4193 10783 - - - - - 2.4 V 400 633 1963 4957 12583 - - - - - 3V 508 779 2319 5925 15130 - - - - - 3.6 V 661 1009 2825 7027 17540 - - - - - 1.8 V 426 624 1679 4244 10884 - - - - - 2.4 V 521 751 1985 4952 12619 - - - - - 3V 643 914 2371 5931 15121 - - - - - 3.6 V 819 1162 2914 7019 17551 - - - - - 1.8 V 371 1111 4297 10153 22747 806 2640 10537 24695 54376 2.4 V 372 1112 4328 10154 22888 809 2661 10545 24767 54505 3V 374 1116 4403 10429 23711 811 2683 10553 24840 54634 3.6 V 378 1149 4545 10702 24361 814 2704 10561 24913 54763 3V 1.4 - - - - - - - - - STM32L496xx Table 47. Current consumption in Standby mode (continued) nA nA mA 1. Guaranteed by characterization results, unless otherwise specified. 2. Guaranteed by test in production. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 5. Wakeup with code execution from flash. Average value given for a typical wakeup time as specified in Table 51: Low-power mode wakeup timings. 149/284 Electrical characteristics 4. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IIDD_ALL(Standby + RTC) + IDD_ALL(SRAM2). Conditions Symbol Unit - IDD_ALL (Shutdown) DS11585 Rev 16 IDD_ALL (Shutdown with RTC) MAX(1) TYP Parameter Supply current in Shutdown mode (backup registers retained) RTC disabled Supply current in Shutdown mode (backup registers retained) RTC enabled Supply current IDD_ALL during wakeup (wakeup from from Shutdown Shutdown) mode - RTC clocked by LSE bypassed at 32768 Hz RTC clocked by LSE quartz (2) in low drive mode Wakeup clock is MSI = 4 MHz. See (3). VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 24 161 983 3020 8970 85 556 3314 10498 31391 2.4 V 31 193 1150 3530 10300 111 648 3844 11897 35017 3V 44 242 1400 4260 12500 154 780 4447 13473 39297 3.6 V 76 338 1790 5220 14700 236 1009 5354 15679 44571 1.8 V 225 363 1190 3230 9180 - - - - - 2.4 V 314 478 1440 3820 10700 - - - - - 3V 421 621 1790 4660 12900 - - - - - 3.6 V 561 831 2280 5730 15300 - - - - - 1.8 V 341 472 1303 3459 - - - - - - 2.4 V 435 586 1572 4041 - - - - - - 3V 553 732 1982 5145 - - - - - - 3.6 V 716 948 2520 6325 - - - - - - 3V 0.6 - - - - - - - - - nA Electrical characteristics 150/284 Table 48. Current consumption in Shutdown mode nA mA 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 3. Wakeup with code execution from flash. Average value given for a typical wakeup time as specified in Table 51: Low-power mode wakeup timings. STM32L496xx Conditions Symbol MAX(1) TYP Parameter Unit - RTC disabled RTC enabled and Backup domain clocked by LSE IVDD_VBAT(VBAT) supply current bypassed at 32768 Hz DS11585 Rev 16 RTC enabled and clocked by LSE quartz(2) VBAT 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C 1.8 V 2 18 110 329 908 - - - - - 2.4 V 2 20 125 371 1016 - - - - - 3V 3 25 154 546 1965 - - - - - 3.6 V 10 57 324 963 2688 - - - - - 1.8 V 198 216 312 535 - - - - - - 2.4 V 280 300 411 664 - - - - - - 3V 375 402 544 943 - - - - - - 3.6 V 488 529 791 1459 - - - - - - 1.8 V 320 347 448 856 1432 - - - - - 2.4 V 405 436 550 921 1567 - - - - - 3V 512 545 686 1128 2529 - - - - - 3.6 V 648 705 976 1588 3293 - - - - - STM32L496xx Table 49. Current consumption in VBAT mode nA 1. Guaranteed by characterization results, unless otherwise specified. 2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. Electrical characteristics 151/284 Electrical characteristics STM32L496xx I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 70: I/O static characteristics. For the output pins, any internal or external pull-up or pull-down and external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 50), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load internal and external connected to the pin: I SW = V DDIOx × f SW × C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDIOx is the I/O supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS CS is the PCB board capacitance including the pad pin. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 152/284 DS11585 Rev 16 STM32L496xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 50. The MCU is placed under the following conditions: • All I/O pins are in Analog mode • The given value is calculated by measuring the difference of the current consumptions: – when the peripheral is clocked on – when the peripheral is clocked off • Ambient operating temperature and supply voltage conditions summarized in Table 19: Voltage characteristics • The power consumption of the digital part of the on-chip peripherals is given in Table 50. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. Table 50. Peripheral current consumption Range 1 Range 2 Low-power run and sleep Bus Matrix(1) 4.44 3.75 4.00 ADC independent clock domain 0.40 0.08 0.30 ADC AHB clock domain 5.55 4.63 5.00 CRC 0.48 0.42 0.50 DMA1 2.00 1.60 2.00 DMA2 1.76 1.50 1.50 DMA2D 24.33 20.21 24.50 FLASH 8.50 7.10 8.00 FMC Peripheral 7.58 6.29 7.00 (2) 1.59 1.25 1.50 GPIOB(2) 1.56 1.25 1.50 (2) GPIOC 1.58 1.29 1.50 GPIOD(2) 1.40 1.17 1.40 GPIOE(2) 1.36 1.13 1.40 (2) 1.70 1.40 1.50 (2) GPIOG 1.80 1.50 1.80 GPIOH(2) 1.50 1.30 1.50 GPIOI 1.18 0.96 1.00 DCMI 1.6 1.3 1.2 OTG_FS independent clock domain 23.20 NA NA OTG_FS AHB clock domain 14.30 NA NA QUADSPI 6.84 5.67 6.50 GPIOA AHB GPIOF (2) DS11585 Rev 16 Unit µA/MHz 153/284 244 Electrical characteristics STM32L496xx Table 50. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep RNG independent clock domain 2.20 NA NA RNG AHB clock domain 0.51 NA NA SRAM1 2.80 2.29 2.50 SRAM2 1.20 1.00 1.00 TSC 1.50 1.17 1.00 121.00 79.10 87.20 AHB to APB1 bridge(3) 0.90 0.70 0.90 CAN1 3.68 3.04 3.50 DAC1 3.20 2.70 3.00 I2C1 independent clock domain 3.80 3.20 3.30 I2C1 APB clock domain 1.00 0.79 1.00 I2C2 independent clock domain 3.41 2.83 3.00 I2C2 APB clock domain 0.98 0.79 1.00 I2C3 independent clock domain 2.89 2.38 2.50 I2C3 APB clock domain 0.98 0.83 1.00 I2C4 independent clock domain 3.41 2.83 3.00 I2C4 APB clock domain 0.98 0.79 1.00 LCD 1.03 0.80 1.03 LPUART1 independent clock domain 2.40 2.00 2.20 LPUART1 APB clock domain 0.98 0.83 0.80 LPTIM1 independent clock domain 3.10 2.54 2.54 LPTIM1 APB clock domain 0.88 0.75 0.90 LPTIM2 independent clock domain 2.86 2.42 2.25 LPTIM2 APB clock domain 0.90 0.67 0.75 OPAMP 0.29 0.20 0.30 PWR 0.80 0.63 0.60 SPI2 1.78 1.50 1.50 SPI3 1.76 1.50 1.50 SWPMI1 independent clock domain 2.10 1.50 2.00 SWPMI1 APB clock domain 1.00 0.79 0.75 Peripheral AHB All AHB peripherals APB1 154/284 DS11585 Rev 16 Unit µA/MHz µA/MHz STM32L496xx Electrical characteristics Table 50. Peripheral current consumption (continued) Range 1 Range 2 Low-power run and sleep TIM2 5.85 4.88 5.70 TIM3 5.20 4.25 5.00 TIM4 4.50 3.67 4.20 TIM5 5.60 4.58 5.10 TIM6 0.85 0.70 0.90 TIM7 0.86 0.71 0.90 USART2 independent clock domain 4.06 3.40 4.00 USART2 APB clock domain 1.38 1.17 1.40 USART3 independent clock domain 4.80 3.92 4.60 USART3 APB clock domain 1.80 1.50 1.80 UART4 independent clock domain 3.80 3.10 3.00 UART4 APB clock domain 1.30 1.13 1.30 UART5 independent clock domain 3.83 3.17 3.50 UART5 APB clock domain 1.60 1.25 1.50 WWDG 0.39 0.33 0.40 84.20 74.96 82.70 AHB to APB2 bridge 1.00 0.90 0.90 DFSDM1 6.00 5.00 5.50 FW 0.28 0.30 0.30 SAI1 independent clock domain 2.60 2.10 2.30 SAI1 APB clock domain 2.09 1.80 2.00 SAI2 independent clock domain 3.30 2.70 3.00 SAI2 APB clock domain 2.50 2.00 2.50 SDMMC1 independent clock domain 4.20 3.90 4.20 SDMMC1 APB clock domain 2.10 1.80 2.00 SPI1 1.71 1.42 1.50 SYSCFG/VREFBUF/COMP 0.55 0.50 0.50 TIM1 8.41 6.96 7.50 TIM8 8.83 7.33 8.00 TIM15 3.96 3.29 3.50 TIM16 3.24 2.67 3.00 TIM17 2.94 2.46 2.50 USART1 independent clock domain 5.20 4.29 5.50 USART1 APB clock domain 1.70 1.50 1.60 Peripheral APB1 All APB1 on (4) APB2 DS11585 Rev 16 Unit µA/MHz µA/MHz 155/284 244 Electrical characteristics STM32L496xx Table 50. Peripheral current consumption (continued) Peripheral APB2 All APB2 on ALL Range 1 Range 2 Low-power run and sleep 55.40 41.33 46.00 234.98 195.83 235.70 Unit µA/MHz 1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA). 2. The GPIOx (x= A…I) dynamic current consumption is approximately divided by a factor two versus this table values when the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes). 3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1. 4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2. The consumption for the peripherals when using SMPS can be found using STM32CubeMX PCC tool. 6.3.6 Wakeup time from low-power modes and voltage scaling transition times The wakeup times given in Table 51 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction. Table 51. Low-power mode wakeup timings(1) Symbol tWUSLEEP Parameter Typ Max - 6 6 Wakeup time from Sleep mode to Run mode Wakeup time from LowtWULPSLEEP power sleep mode to Lowpower run mode Wakeup in flash with flash in power-down during low-power sleep mode (SLEEP_PD=1 in FLASH_ACR) and with clock MSI = 2 MHz Range 1 Wake up time from Stop 0 mode to Run mode in flash Range 2 tWUSTOP0 Range 1 Wake up time from Stop 0 mode to Run mode in SRAM1 156/284 Conditions Range 2 7 9 Wakeup clock MSI = 48 MHz 7.0 11.6 Wakeup clock HSI16 = 16 MHz 6.2 10.7 Wakeup clock MSI = 24 MHz 7.3 11.7 Wakeup clock HSI16 = 16 MHz 6.2 10.7 Wakeup clock MSI = 4 MHz 7.6 13.2 Wakeup clock MSI = 48 MHz 2.5 2.9 Wakeup clock HSI16 = 16 MHz 2.7 2.9 Wakeup clock MSI = 24 MHz 3.2 3.6 Wakeup clock HSI16 = 16 MHz 2.7 2.9 Wakeup clock MSI = 4 MHz 5.7 13.2 DS11585 Rev 16 Unit Nb of CPU cycles µs STM32L496xx Electrical characteristics Table 51. Low-power mode wakeup timings(1) (continued) Symbol Parameter Conditions Range 1 Wake up time from Stop 1 mode to Run mode in flash Range 2 Range 1 tWUSTOP1 Wake up time from Stop 1 mode to Run mode in SRAM1 Wake up time from Stop 1 mode to Low-power run mode in flash Wake up time from Stop 1 mode to Low-power run mode in SRAM1 Range 2 Regulator in low-power mode (LPR=1 in PWR_CR1) Range 1 Wake up time from Stop 2 mode to Run mode in flash Range 2 tWUSTOP2 Range 1 Wake up time from Stop 2 mode to Run mode in SRAM1 tWUSTBY tWUSTBY SRAM2 tWUSHDN Range 2 Wakeup time from Standby mode to Run mode Range 1 Wakeup time from Standby with SRAM2 to Run mode Range 1 Wakeup time from Shutdown mode to Run mode Range 1 Typ Max Wakeup clock MSI = 48 MHz 8.4 9.4 Wakeup clock HSI16 = 16 MHz 7.8 8.4 Wakeup clock MSI = 24 MHz 8.7 9.6 Wakeup clock HSI16 = 16 MHz 7.8 8.3 Wakeup clock MSI = 4 MHz 8.0 12.9 Wakeup clock MSI = 48 MHz 5.5 5.9 Wakeup clock HSI16 = 16 MHz 6.6 7.0 Wakeup clock MSI = 24 MHz 6.1 6.5 Wakeup clock HSI16 = 16 MHz 6.6 7.0 Wakeup clock MSI = 4 MHz 8.5 12.8 13.8 20.0 11.8 22.0 Wakeup clock MSI = 48 MHz 8.9 9.8 Wakeup clock HSI16 = 16 MHz 8.3 9.2 Wakeup clock MSI = 24 MHz 9.3 10.2 Wakeup clock HSI16 = 16 MHz 8.2 9.2 Wakeup clock MSI = 4 MHz 14.2 16.1 Wakeup clock MSI = 48 MHz 6.1 7.1 Wakeup clock HSI16 = 16 MHz 7.2 8.1 Wakeup clock MSI = 24 MHz 6.8 7.8 Wakeup clock HSI16 = 16 MHz 7.2 8.2 Wakeup clock MSI = 4 MHz 8.4 16.7 Wakeup clock MSI = 8 MHz 15.3 23.2 Wakeup clock MSI = 4 MHz 21.3 30.5 Wakeup clock MSI = 8 MHz 15.3 23.1 Wakeup clock MSI = 4 MHz 21.3 30.6 Wakeup clock MSI = 4 MHz 305.9 322.3 Unit µs Wakeup clock MSI = 2 MHz µs µs µs µs 1. Guaranteed by characterization results. DS11585 Rev 16 157/284 244 Electrical characteristics STM32L496xx Table 52. Regulator modes transition times(1) Symbol Parameter tWULPRUN tVOST Conditions Typ Max Wakeup time from Low-power run mode to Code run with MSI 2 MHz Run mode(2) 5 7 Regulator transition time from Range 2 to Range 1 or Range 1 to Range 2(3) 20 40 Typ Max Stop 0 mode - 1.7 Stop 1 mode and Stop 2 mode - 8.5 Unit µs Code run with MSI 24 MHz 1. Guaranteed by characterization results. 2. Time until REGLPF flag is cleared in PWR_SR2. 3. Time until VOSF flag is cleared in PWR_SR2. Table 53. Wakeup time using USART/LPUART(1) Symbol Parameter tWUUSART tWULPUART Conditions Wakeup time needed to calculate the maximum USART/LPUART baud rate permitting to wakeup up from Stop mode when USART/LPUART clock source is HSI16 Unit µs 1. Guaranteed by design. 6.3.7 External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 26. Table 54. High-speed external user clock characteristics(1) Symbol fHSE_ext Parameter User external clock source frequency Conditions Min Typ Max Voltage scaling Range 1 - 8 48 Voltage scaling Range 2 - 8 26 MHz VHSEH OSC_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIOx Voltage scaling Range 1 7 - - Voltage scaling Range 2 18 tw(HSEH) OSC_IN high or low time tw(HSEL) 1. Guaranteed by design. 158/284 DS11585 Rev 16 Unit V ns - - STM32L496xx Electrical characteristics Figure 26. High-speed external clock source AC timing diagram tw(HSEH) VHSEH 90% 10% VHSEL tr(HSE) tf(HSE) t tw(HSEL) THSE MS19214V2 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 27. Table 55. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency - - 32.768 1000 VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIOx - 250 - - tw(LSEH) OSC32_IN high or low time tw(LSEL) V ns 1. Guaranteed by design. Figure 27. Low-speed external clock source AC timing diagram tw(LSEH) VLSEH 90% 10% VLSEL tr(LSE) tf(LSE) t tw(LSEL) TLSE MS19215V2 DS11585 Rev 16 159/284 244 Electrical characteristics STM32L496xx High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 56. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 56. HSE oscillator characteristics(1) Symbol fOSC_IN RF Conditions(2) Min Typ Max Unit Oscillator frequency - 4 8 48 MHz Feedback resistor - - 200 - kΩ - - 5.5 VDD = 3 V, Rm = 30 Ω, CL = 10 pF@8 MHz - 0.44 - VDD = 3 V, Rm = 45 Ω, CL = 10 pF@8 MHz - 0.45 - VDD = 3 V, Rm = 30 Ω, CL = 5 pF@48 MHz - 0.68 - VDD = 3 V, Rm = 30 Ω, CL = 10 pF@48 MHz - 0.94 - VDD = 3 V, Rm = 30 Ω, CL = 20 pF@48 MHz - 1.77 - Startup - - 1.5 mA/V VDD is stabilized - 2 - ms Parameter During startup IDD(HSE) Gm HSE current consumption Maximum critical crystal transconductance tSU(HSE)(4) Startup time (3) mA 1. Guaranteed by design. 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 28). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. 160/284 DS11585 Rev 16 STM32L496xx Note: Electrical characteristics For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 28. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MHz resonator CL2 REXT (1) fHSE RF Bias controlled gain OSC_OUT MS19876V1 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 57. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 57. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol IDD(LSE) Parameter LSE current consumption Maximum critical crystal Gmcritmax gm tSU(LSE)(3) Startup time Conditions(2) Min Typ Max LSEDRV[1:0] = 00 Low drive capability - 250 - LSEDRV[1:0] = 01 Medium low drive capability - 315 - LSEDRV[1:0] = 10 Medium high drive capability - 500 - LSEDRV[1:0] = 11 High drive capability - 630 - LSEDRV[1:0] = 00 Low drive capability - - 0.5 LSEDRV[1:0] = 01 Medium low drive capability - - 0.75 LSEDRV[1:0] = 10 Medium high drive capability - - 1.7 LSEDRV[1:0] = 11 High drive capability - - 2.7 VDD is stabilized - 2 - DS11585 Rev 16 Unit nA µA/V s 161/284 244 Electrical characteristics STM32L496xx 1. Guaranteed by design. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 29. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN fLSE Drive programmable amplifier 32.768 kHz resonator OSC32_OUT CL2 MS30253V2 Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. 6.3.8 Internal clock source characteristics The parameters given in Table 58 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 22: General operating conditions. The provided curves are characterization results, not tested in production. High-speed internal (HSI16) RC oscillator Table 58. HSI16 oscillator characteristics(1) Symbol fHSI16 TRIM Parameter HSI16 Frequency HSI16 user trimming step DuCy(HSI16)(2) Duty Cycle Conditions Min Typ Max Unit 15.88 - 16.08 MHz Trimming code is not a multiple of 64 0.2 0.3 0.4 Trimming code is a multiple of 64 -4 -6 -8 45 - 55 % -1 - 1 % -2 - 1.5 % -0.1 - 0.05 % VDD=3.0 V, TA=30 °C - ∆Temp(HSI16) HSI16 oscillator frequency TA= 0 to 85 °C drift over temperature TA= -40 to 125 °C ∆VDD(HSI16) HSI16 oscillator frequency VDD=1.62 V to 3.6 V drift over VDD 162/284 DS11585 Rev 16 % STM32L496xx Electrical characteristics Table 58. HSI16 oscillator characteristics(1) (continued) Symbol Conditions Min Typ Max Unit HSI16 oscillator start-up time - - 0.8 1.2 μs tstab(HSI16)(2) HSI16 oscillator stabilization time - - 3 5 μs IDD(HSI16)(2) HSI16 oscillator power consumption - - 155 190 μA tsu(HSI16)(2) Parameter 1. Guaranteed by characterization results. 2. Guaranteed by design. Figure 30. HSI16 frequency versus temperature MHz 16.4 +2 % 16.3 +1.5 % 16.2 +1 % 16.1 16 15.9 -1 % 15.8 -1.5 % 15.7 -2 % 15.6 -40 -20 0 Mean 20 40 60 min 80 100 120 °C max MSv39299V2 DS11585 Rev 16 163/284 244 Electrical characteristics STM32L496xx Multi-speed internal (MSI) RC oscillator Table 59. MSI oscillator characteristics(1) Symbol Parameter Conditions Min Typ Max Range 0 98.7 100 101.3 Range 1 197.4 200 202.6 Range 2 394.8 400 405.2 Range 3 7896 800 810.4 Range 4 0.987 1 1.013 Range 5 1.974 2 2.026 Range 6 3.948 4 4.052 Range 7 7.896 8 8.104 Range 8 15.79 16 16.21 Range 9 23.69 24 24.31 Range 10 31.58 32 32.42 Range 11 47.38 48 48.62 Range 0 - 98.304 - Range 1 - 196.608 - Range 2 - 393.216 - Range 3 - 786.432 - Range 4 - 1.016 - PLL mode Range 5 XTAL= 32.768 kHz Range 6 - 1.999 - - 3.998 - Range 7 - 7.995 - Range 8 - 15.991 - Range 9 - 23.986 - Range 10 - 32.014 - Range 11 - 48.005 - -3.5 - 3 -8 - 6 MSI mode fMSI ∆TEMP(MSI)(2) 164/284 MSI frequency after factory calibration, done at VDD=3 V and TA=30 °C MSI oscillator frequency drift over temperature TA= -0 to 85 °C MSI mode TA= -40 to 125 °C DS11585 Rev 16 Unit kHz MHz kHz MHz % STM32L496xx Electrical characteristics Table 59. MSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ VDD=1.62 V to 3.6 V -1.2 - VDD=2.4 V to 3.6 V -0.5 - VDD=1.62 V to 3.6 V -2.5 - VDD=2.4 V to 3.6 V -0.8 - VDD=1.62 V to 3.6 V -5 - VDD=2.4 V to 3.6 V -1.6 - TA= -40 to 85 °C - 1 2 TA= -40 to 125 °C - 2 4 Range 0 to 3 ∆VDD(MSI) (2) MSI oscillator frequency drift over VDD (reference is 3 V) MSI mode Range 4 to 7 Range 8 to 11 ∆FSAMPLING (MSI)(2)(4) CC jitter(MSI)(4) P jitter(MSI)(4) tSU(MSI)(4) tSTAB(MSI)(4) Max Unit 0.5 0.7 % 1.2 Frequency variation in sampling mode(3) MSI mode RMS cycle-tocycle jitter PLL mode Range 11 - - 60 - ps RMS Period jitter PLL mode Range 11 - - 50 - ps Range 0 - - 10 20 Range 1 - - 5 10 Range 2 - - 4 8 Range 3 - - 3 7 Range 4 to 7 - - 3 6 Range 8 to 11 - - 2.5 6 10 % of final frequency - - 0.25 0.5 5 % of final frequency - - 0.5 1.25 1 % of final frequency - - - 2.5 MSI oscillator start-up time MSI oscillator PLL mode stabilization time Range 11 DS11585 Rev 16 % us ms 165/284 244 Electrical characteristics STM32L496xx Table 59. MSI oscillator characteristics(1) (continued) Symbol IDD(MSI)(4) Parameter MSI oscillator power consumption Conditions MSI and PLL mode Min Typ Max Range 0 - - 0.6 1 Range 1 - - 0.8 1.2 Range 2 - - 1.2 1.7 Range 3 - - 1.9 2.5 Range 4 - - 4.7 6 Range 5 - - 6.5 9 Range 6 - - 11 15 Range 7 - - 18.5 25 Range 8 - - 62 80 Range 9 - - 85 110 Range 10 - - 110 130 Range 11 - - 155 190 1. Guaranteed by characterization results. 2. This is a deviation for an individual part once the initial frequency has been measured. 3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable. 4. Guaranteed by design. Figure 31. Typical current consumption versus MSI frequency 166/284 DS11585 Rev 16 Unit µA STM32L496xx Electrical characteristics High-speed internal 48 MHz (HSI48) RC oscillator Table 60. HSI48 oscillator characteristics(1) Symbol fHSI48 TRIM USER TRIM COVERAGE Parameter Conditions HSI48 Frequency VDD=3.0V, TA=30°C HSI48 user trimming step - HSI48 user trimming coverage ±32 steps DuCy(HSI48) Duty Cycle VDD = 3.0 V to 3.6 V, TA = –15 to 85 °C Accuracy of the HSI48 oscillator ACCHSI48_REL over temperature (factory calibrated) DVDD(HSI48) HSI48 oscillator frequency drift with VDD Min Typ Max Unit - 48 - MHz - 0.11 (2) 0.18 (2) % ±3(3) ±3.5(3) - % 45(2) - 55(2) % - - ±3(3) % VDD = 1.65 V to 3.6 V, TA = –40 to 125 °C - - VDD = 3 V to 3.6 V - 0.025(3) 0.05(3) VDD = 1.65 V to 3.6 V - 0.05(3) 0.1(3) (3) ±4.5 % tsu(HSI48) HSI48 oscillator start-up time - - 2.5(2) 6(2) μs IDD(HSI48) HSI48 oscillator power consumption - - 340(2) 380(2) μA NT jitter Next transition jitter Accumulated jitter on 28 cycles(4) - - +/-0.15(2) - ns PT jitter Paired transition jitter Accumulated jitter on 56 cycles(4) - - +/-0.25(2) - ns 1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4. Jitter measurement are performed without clock source activated in parallel. DS11585 Rev 16 167/284 244 Electrical characteristics STM32L496xx Figure 32. HSI48 frequency versus temperature % 6 4 2 0 -2 -4 -6 -50 -30 -10 10 Avg 30 50 70 90 min 110 130 °C max MSv40989V1 Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics(1) Symbol Parameter LSI Frequency fLSI Min Typ Max VDD = 3.0 V, TA = 30 °C 31.04 - 32.96 VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34 - - 80 130 μs 5% of final frequency - 125 180 μs - - 110 180 nA LSI oscillator startup time tSU(LSI)(2) tSTAB(LSI)(2) IDD(LSI)(2) Conditions LSI oscillator stabilization time LSI oscillator power consumption Unit kHz 1. Guaranteed by characterization results. 2. Guaranteed by design. 6.3.9 PLL characteristics The parameters given in Table 62 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 22: General operating conditions. Table 62. PLL, PLLSAI1, PLLSAI2 characteristics(1) Symbol fPLL_IN 168/284 Parameter Conditions Min Typ Max Unit PLL input clock(2) - 4 - 16 MHz PLL input clock duty cycle - 45 - 55 % DS11585 Rev 16 STM32L496xx Electrical characteristics Table 62. PLL, PLLSAI1, PLLSAI2 characteristics(1) (continued) Symbol Parameter Conditions fPLL_P_OUT PLL multiplier output clock P fPLL_Q_OUT PLL multiplier output clock Q fPLL_R_OUT PLL multiplier output clock R fVCO_OUT tLOCK Jitter IDD(PLL) PLL VCO output Min Typ Max Voltage scaling Range 1 2.0645 - 80 Voltage scaling Range 2 2.0645 - 26 Voltage scaling Range 1 8 - 80 Voltage scaling Range 2 8 - 26 Voltage scaling Range 1 8 - 80 Voltage scaling Range 2 8 - 26 Voltage scaling Range 1 64 - 344 Voltage scaling Range 2 64 - 128 - 15 40 - 40 - - 30 - VCO freq = 64 MHz - 150 200 VCO freq = 96 MHz - 200 260 VCO freq = 192 MHz - 300 380 VCO freq = 344 MHz - 520 650 PLL lock time - RMS cycle-to-cycle jitter System clock 80 MHz RMS period jitter PLL power consumption on VDD(1) Unit MHz MHz MHz MHz μs ±ps μA 1. Guaranteed by design. 2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the 3 PLLs. 6.3.10 Flash memory characteristics Table 63. Flash memory characteristics(1) Symbol Parameter Conditions Typ Max Unit tprog 64-bit programming time - 81.69 90.76 µs tprog_row one row (32 double word) programming time normal programming 2.61 2.90 fast programming 1.91 2.12 tprog_page one page (2 Kbyte) programming time normal programming 20.91 23.24 fast programming 15.29 16.98 22.02 24.47 normal programming 5.35 5.95 fast programming 3.91 4.35 22.13 24.59 tERASE tprog_bank tME Page (2 KB) erase time one bank (512 Kbyte) programming time - Mass erase time (one or two banks) - DS11585 Rev 16 ms s ms 169/284 244 Electrical characteristics STM32L496xx Table 63. Flash memory characteristics(1) (continued) Symbol IDD Parameter Conditions Average consumption from VDD Maximum current (peak) Typ Max Write mode 3.4 - Erase mode 3.4 - Write mode 7 (for 2 μs) - Erase mode 7 (for 41 μs) - Unit mA 1. Guaranteed by design. Table 64. Flash memory endurance and data retention Symbol NEND Min(1) Unit TA = –40 to +105 °C 10 kcycles 1 kcycle(2) at TA = 85 °C 30 Parameter Endurance Conditions 1 kcycle tRET Data retention 1 (2) kcycle(2) at TA = 105 °C 15 at TA = 125 °C 7 (2) at TA = 55 °C 30 10 kcycles(2) at TA = 85 °C 15 10 kcycles 10 kcycles(2) at TA = 105 °C Years 10 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. 6.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling two LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 65. They are based on the EMS levels and classes defined in application note AN1709. 170/284 DS11585 Rev 16 STM32L496xx Electrical characteristics Table 65. EMS characteristics Conditions Level/ Class Symbol Parameter VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 80 MHz, conforming to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, TA = +25 °C, fHCLK = 80 MHz, conforming to IEC 61000-4-4 5A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling two LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. DS11585 Rev 16 171/284 244 Electrical characteristics STM32L496xx Table 66. EMI characteristics for fHSE = 8 MHz and fHCLK = 80 MHz Symbol Parameter SEMI Peak(1) Conditions Monitored frequency band Value 0.1 MHz to 30 MHz 3 30 MHz to 130 MHz VDD = 3.6 V, TA = 25 °C, BGA169 package 130 MHz to 1 GHz compliant with IEC 61967-2 1 GHz to 2 GHz -2 0.1 MHz to 30 MHz 1.5 (2) Level Unit dBµV 0 8 - 1. Refer to AN1709 “EMI radiated test” section. 2. Refer to AN1709 “EMI level classification” section. 6.3.12 + Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pins). This test conforms to the ANSI/JEDEC standard. Table 67. ESD absolute maximum ratings Symbol VESD(HBM) Ratings Conditions Class Electrostatic discharge voltage TA = +25 °C, conforming to (human body model) ANSI/ESDA/JEDEC JS-001 Electrostatic discharge voltage TA = +25 °C, conforming to VESD(CDM) (charge device model) ANSI/ESD STM5.3.1 Maximum Unit value(1) 2 2000 V C3 250 1. Guaranteed by characterization results. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • a supply overvoltage is applied to each power supply pin • a current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 68. Electrical sensitivities Symbol LU Parameter Static latch-up class Conditions TA = +105 °C conforming to JESD78A 1. Negative injection is limited to -30 mA for PF0, PF1, PG6, PG7, PG8, PG12, PG13, PG14. 172/284 DS11585 Rev 16 Class II level A(1) STM32L496xx 6.3.13 Electrical characteristics I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation). The characterization results are given in Table 69. Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. Table 69. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Unit Negative injection Positive injection Injected current on all pins except PA4, PA5, PB0, PF12, PF13, OPAMP1_V1NM, OPAMP2_V1NM -5 NA(2) Injected current on pins PB0, PF12, PF13 0 NA(2) Injected current on OPAMP1_V1NM, OPAMP2_V1NM 0 0 Injected current on PA4, PA5 pins -5 0 mA 1. Guaranteed by characterization. 2. Injection is not possible 6.3.14 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 70 are derived from tests performed under the conditions summarized in Table 22: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant (except BOOT0). Note: For information on GPIO configuration, refer to the application note AN4899 “STM32 GPIO configuration for hardware settings and low-power consumption” available from the ST website www.st.com. DS11585 Rev 16 173/284 244 Electrical characteristics STM32L496xx Table 70. I/O static characteristics Symbol VIL(1) VIH(1) Parameter Conditions 174/284 Typ Max I/O input low level voltage except BOOT0 1.62 V