PM6641
Monolithic VR for chipset and DDR2/3 supply
for ultra-mobile PC (UMPC) applications
Features
■
0.8 V ±1% internal voltage reference
■
2.7 V to 5.5 V input voltage range
■
Fast response, constant frequency,
current mode control
■
Three independent, adjustable, out-of-phase
SMPS for DDR2/3 (VDDQ) and chipset supply
■
Low noise DDR2/3 reference (VTTREF)
■
±2 Apk LDO for DDR2/3 termination (VTT)
with foldback
■
S0-S5 states compliant DDR2/3 section
■
Active soft-end for all outputs
■
Selectable tracking discharge for VDDQ
■
Separate Power Good signals
■
Pulse skipping at light load
■
Programmable current limit and soft-start for
all outputs
■
Latched OVP, UVP protection
■
Thermal protection
Description
The PM6641 is a monolithic voltage regulator
module specifically designed to supply DDR2/3
memory and chipset in ultra-mobile PC and real
estate constrained portable systems.
It integrates three independent, adjustable,
constant frequency buck converters, a ±2 Apk low
drop-out (LDO) linear regulator and a
±15 mA low noise buffered reference.
Each regulator provides basic UV and OV
protections, programmable soft-start and current
limit and active soft-end.
Applications
Pulse-skipping technique is performed to increase
efficiency at very light load.
■
DDR2/3 memory and chipset supply
■
UMPC and portable equipment
■
Handheld and PDAs
Table 1.
VFQFPN-48 7x7 mm
Device summary
Order codes
Package
PM6641
Packaging
Tray
VFQFPN-48 7x7 (exposed pad)
PM6641TR
May 2009
Tape and reel
Doc ID 13510 Rev 3
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www.st.com
47
Contents
PM6641
Contents
1
Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
2.1
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1
2/47
Memory supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.1
VDDQ switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.2
VTT LDO and VTTREF buffered reference . . . . . . . . . . . . . . . . . . . . . . 20
7.1.3
VTT and VTTREF soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1.4
S3 and S5 power management pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2
Chipset supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3
SW regulators control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.4
SW regulators pulse skipping and PWM mode . . . . . . . . . . . . . . . . . . . . 25
7.5
Output voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.6
Outputs soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.7
Outputs soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.8
Switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.9
Phase management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.10
Peak current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.11
Fault management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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PM6641
8
9
Contents
7.11.1
Output overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.11.2
Output under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.11.3
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.11.4
Input under voltage lock-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.2
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.3
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.4
SW regulator compensation components selection . . . . . . . . . . . . . . . . . 37
8.5
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.1
UMPC DDR2 and chipset power supply . . . . . . . . . . . . . . . . . . . . . . . . . 40
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Doc ID 13510 Rev 3
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Doc ID 13510 Rev 3
1.8V
VCC
PG_1S8
PG_1S8
3.3V
AVCC
PG_1S05
PM6641
3.3V
PG_1S05
EN_1S8 (S5)
VTTREF
VTTREF
AGND
SS_1S8
CSNS
COMP_1S8
SGND_1S8
VFB_1S8
VOUT_1S8
VSW_1S8
EN_1S05
LDOIN
VIN_1S8
VTTGND
COMP_1S05
5V
VTT
SET_PH1
3.3V
VTTFB
AGND
EN_VTT (S3)
SS_1S05
PG_1S5
EN_1S5
SS_1S5
COMP_1S5
SGND_1S5
VFB_1S5
VSW_1S5
VIN_1S5
1.05V
3.3V
PG_1S5
1.5V
Figure 1.
SGND_1S05
4/47
VFB_1S05
1
VSW_1S05
VTT
Typical application circuit
PM6641
Typical application circuit
Application circuit
SET_SWF
VIN_1S05
PM6641
Pin settings
2
Pin settings
2.1
Connections
EN_1S8 (S5)
Pin connection (through top view)
VCC
VTTFB
DSCG
VTTREF
LDOIN
VTT
VTTGND
AVCC
AGND
SET_PH1
AGND
Figure 2.
EN_VTT (S3)
EN_1S5
EN_1S05
VIN_1S5
VSW_1S5
VSW_1S5
AGND
SET_SWF
VOUT_1S8
CSNS
SGND_1S8
PM6641
SGND_1S8
VSW_1S8
VSW_1S8
VIN_1S8
VIN_1S8
VFB_1S8
COMP_1S8
SGND_1S5
SGND_1S5
VFB_1S5
COMP_1S5
SS_1S5
PG_1S5
PG_1S8
PG_1S05
VIN_1S05
VIN_1S05
VSW_1S05
VSW_1S05
SGND_1S05
SGND_1S05
VFB_1S05
COMP_1S05
SS_1S05
SS_1S8
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Pin settings
2.2
PM6641
Pin description
Table 2.
6/47
Pin functions
n°
Pin
Function
1
AGND
2
SET_SWF
Switching frequency setting input.
See Chapter 7.8: Switching frequency selection on page 29
3
VOUT_1S8
VDDQ/2 divider input and discharge path for 1.8 V rail.
4
CSNS
5
SGND_1S8
Switcher power ground for 1.8 V rail.
6
SGND_1S8
Switcher power ground for 1.8 V rail.
7
VSW_1S8
Switch node for 1.8 V rail.
8
VSW_1S8
Switch node for 1.8 V rail.
9
VIN_1S8
Power supply input for 1.8 V rail.
10
VIN_1S8
Power supply input for 1.8 V rail.
11
VFB_1S8
Feedback input for 1.8 V rail.
See Chapter 7.5: Output voltage divider on page 27
12
COMP_1S8
13
SS_1S8
Positive terminal of the external soft-start capacitor for 1.8 V rail.
See Chapter 7.6: Outputs soft-start on page 28 section for details.
14
SS_1S05
Positive terminal of the external soft-start capacitor for 1.05 V rail.
See Chapter 7.6: Outputs soft-start on page 28 section for details.
15
COMP_1S05
16
VFB_1S05
17
SGND_1S05
Switcher power ground for 1.05 V rail.
18
SGND_1S05
Switcher power ground for 1.05 V rail.
19
VSW_1S05
Switch node for 1.05 V rail.
20
VSW_1S05
Switch node for 1.05 V rail.
21
VIN_1S05
Power supply input for 1.05 V rail.
22
VIN_1S05
Power supply input for 1.05 V rail.
23
PG_1S05
Power Good signal for 1.05 V rail. Open drain. See Chapter 7.2: Chipset
supply on page 22 section for details.
24
PG_1S8
Power Good signal for 1.8 V rail. Open drain. See Chapter 7.1.1: VDDQ
switching regulator on page 20 section for details.
25
PG_1S5
Power Good signal for 1.5 V rail. Open drain. See Chapter 7.2: Chipset
supply on page 22 section for details.
Analog and signal ground.
Current limit setting input for all rails.
See Chapter 7.10: Peak current limit on page 31
Loop compensation output for 1.8 V rail. See Chapter 7.3: SW regulators
control loop on page 24 and Chapter 8.4: SW regulator compensation
components selection on page 38 sections for details.
Loop compensation output for 1.05 V rail. See Chapter 7.3: SW regulators
control loop on page 24 and Chapter 8.4: SW regulator compensation
components selection on page 38 for details.
Feedback input for 1.05 V rail.
See Chapter 7.5: Output voltage divider on page 27 section for details
Doc ID 13510 Rev 3
PM6641
Pin settings
Table 2.
Pin functions (continued)
n°
Pin
Function
26
SS_1S5
27
COMP_1S5
28
VFB_1S5
29
SGND_1S5
Switcher power ground for 1.5 V rail.
30
SGND_1S5
Switcher power ground for 1.5 V rail.
31
VSW_1S5
Switch node for 1.5 V rail.
32
VSW_1S5
Switch node for 1.5 V rail.
33
VIN_1S5
Power supply input for 1.5 V rail.
34
EN_1S05
Enable input for 1.05 V rail.
35
EN_1S5
Enable input for 1.5 V rail.
36
EN_VTT
Enable input for VTT rail. High in S0 system states. See Chapter 7.1.4: S3
and S5 power management pins on page 22 section for details.
37
EN_1S8
Enable input for 1.8 V (VDDQ) rail. High in S0-S3 system states.
See Chapter 7.1.4: S3 and S5 power management pins on page 22 section
for details.
38
AGND
39
SET_PH1
40
AGND
Analog and signal ground.
41
AVCC
Analog circuitry supply. Connect to +5 V by a simple RC filter.
42
VTTGND
43
VTT
44
LDOIN
45
VTTREF
46
DSCG
Tracking/non-tracking discharge selection for DDR2-3 section. See
Chapter 7.7: Outputs soft-end on page 29 section for details.
47
VTTFB
Feedback input for VTT linear regulator output.
48
VCC
Positive terminal of the external soft-start capacitor for 1.5 V rail.
See Chapter 7.6: Outputs soft-start on page 28 section for details.
Loop compensation output for 1.5 V rail. Chapter 7.3: SW regulators control
loop on page 24 and Chapter 8.4: SW regulator compensation components
selection on page 38 sections for details.
Feedback input for 1.5 V rail.
See Chapter 7.5: Output voltage divider on page 27 section for details
Analog and signal ground.
Switching regulator phase control.
See Chapter 7.9: Phase management on page 30 section for details.
LDO linear regulator power ground.
LDO linear regulator output. DDR2-3 termination voltage. See Chapter 7.1:
Memory supply on page 20 and Chapter 7.1.2: VTT LDO and VTTREF
buffered reference on page 21 sections for details.
LDO linear regulator input. Typically connected to the 1.8 V rail.
Reference voltage buffer output. See Chapter 7.1: Memory supply on
page 20 and Chapter 7.1.2: VTT LDO and VTTREF buffered reference on
page 21 sections for details.
+5 V switching circuitry supply. Bypass to AGND by a 100 nF capacitor.
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Electrical data
PM6641
3
Electrical data
3.1
Maximum rating
Table 3.
Absolute maximum ratings (1)
Symbol
Parameter
VVIN
VIN_x to SGND_x
VVCC
VCC to AGND or SGND_x
VAVCC
AVCC to AGND or SGND_x
VIN = VAVCC
VVCC = VAVCC
Value
Unit
-0.3 to 6
AGND to SGND_x
-0.3 to 0.3
VTTGND to SGND_x
V
VSW_x to SGND_x
VVSW
-0.3 to 6
VSW_x to AGND
CSNS, PG_x, EN_x, DSCG, COMP_x, VFB_x, SS_x,
SET_SWF, SET_PH1, VOUT_1S8 to AGND
VTT, VTTREF, VTTFB to AGND
-0.3 to VAVCC + 0.3
LDOIN, VTT, VTTREF, VTTFB to VTTGND
PTOT
Power dissipation @ TA = 25 °C
4
W
1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under “absolute
maximum ratings” may cause permanent damage to the device. Exposure to absolute maximum rated
conditions for extended periods may affect device reliability.
3.2
Thermal data
Table 4.
Symbol
8/47
Thermal data
Parameter
Value
Unit
25
°C/W
RthJA
Thermal resistance junction to ambient
TSTG
Storage temperature range
-50 to 150
°C
TA
Operating ambient temperature range
-40 to 85
°C
TJ
Junction operating temperature range
-40 to 125
°C
Doc ID 13510 Rev 3
PM6641
3.3
Electrical data
Recommended operating conditions
Table 5.
Recommended operating conditions
Values
Symbol
Parameter
Unit
Min
Typ
Max
VAVCC
AVCC voltage range
4.5
5.5
VVCC
VCC IC supply voltage
4.5
VAVCC
VIN_x input voltage range
2.7
VVCC
VIN
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9/47
Electrical characteristics
4
PM6641
Electrical characteristics
TA = 0 °C to 85 °C, AVCC = 5 V, VCC = 5 V, VIN_x = 3.3 V and LDOIN connected to 1.8 V
output if not otherwise specified (a).
Table 6.
Electrical characteristics
Values
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
Supply section all rails
ICC
ISHDN
AVCC+VCC operating current
VVCC = +5 V, all switching
regulators active without load
3
mA
Total shutdown current into
VIN_x + AVCC + VCC pins
VIN = VAVCC = VVCC = +5 V,
all EN_x low
10
μA
AVCC under voltage lockout
upper threshold
4.0
4.1
4.35
V
UVLOth
AVCC under voltage lockout
lower threshold
3.6
UVLO hysteresis
100
3.9
4.0
mV
Error amplifier, FB AND SS – all rails
VREF
Error amplifier reference voltage VAVCC = VVCC = 5 V
792
800
IFB
FB input bias current
VFB_X = 0.8 V
ISS
Soft-start current
VSS_X = 0.4 V
10
RSETSWF = 140 kΩ
500
808
mV
25
nA
μA
Oscillator frequency
fSW
Switching frequency
SET_SWF to VCC
675
RSETSWF = 70 kΩ
750
825
kHz
1000
Comp all rails
gm
COMP_x transconductance
300
µS
UVP/OVP protections and PGOOD signal (SMPS only) all rails
OVPth
Overvoltage threshold
116
120
124
UVPth
Undervoltage threshold
56
60
64
Power good upper threshold
106
110
115
Power Good lower threshold
86
90
94
PGth
%
IPG,LEAK
PG_x outputs leakeage current
PG_x tied to +5 V
VPG,LOW
PG_x outputs low level
VFB_X = 0.6 V or 1V, IPG_X = 2 mA
1
µA
250
mV
a. All parameters at operating temperature extremes are guaranteed by design and statistical analysis
(not production tested).
10/47
Doc ID 13510 Rev 3
PM6641
Table 6.
Electrical characteristics
Electrical characteristics (continued)
Values
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
Thermal shutdown
TSHDN
Thermal shutdown threshold
150
Thermal shutdown hysteresis
15
°C
Switching node – chipset 1.5 V rail
Minimum on-time
200
RDSon,HS
High side PMOS Ron
150
220
RDSon,LS
Low side NMOS Ron
100
160
tOnmin
IINLEAK
ns
mΩ
VIN_1S5 leakage current
Peak current limit
VAVCC = VVCC = +5 V, all
EN_1S5 low
VIN =
+5 V
1
μA
VIN =
+3.3 V
RCSNS = 50 kΩ
3.9
A
25
Ω
Soft-end section – chipset 1.5 V rail
Discharge resistance
LS turn-on VFB_1SX threshold
with internal divider
VFB_S1X to OUT_X
0.29
LS turn-on VFB_1SX threshold
with external divider
VFB_S1X to external divider
0.16
V
Power management section – chipset 1.5 V rail
EN_1S5 turn-off level
EN_1S5 turn-on level
0.8
VAVCC = 5 V
V
2
Switching node – chipset 1.05 V rail
Minimum on-time
180
RDSon,HS
High side PMOS Ron
100
160
RDSon,LS
Low side NMOS Ron
70
110
tOnmin
IINLEAK
ns
mΩ
VIN_1S05 leakage current
VAVCC = VVCC = +5 V, all
EN_1S05 low
Peak current limit
RCSNS = 50 kΩ
VIN =
+5 V
1
VIN =
+3.3 V
1
μA
5.1
A
25
Ω
Soft end section – chipset 1.05 V rail
Discharge resistance
Doc ID 13510 Rev 3
11/47
Electrical characteristics
Table 6.
PM6641
Electrical characteristics (continued)
Values
Symbol
Parameter
Test condition
Unit
Min
LS turn-on VFB_1SX threshold
with internal divider
VFB_S1X to OUT_X
Typ
Max
0.2
V
LS turn-on VFB_1SX threshold
with external divider
VFB_S1X to external divider
0.16
Power management section – chipset 1.05 V rail
0.8
EN_1S05 turn-off level
EN_1S05 turn-on level
VAVCC = +5 V
V
2
Switching node – DDR2/3 rails
Minimum on-time
200
RDSon,HS
High side PMOS Ron
90
130
RDSon,LS
Low side NMOS Ron
80
120
tOnmin
IINLEAK
ns
mΩ
VIN_1S8 leakage current
VAVCC = VVCC = 5 V,
all EN_1S8 low
VIN =
+5 V
1
VIN =
+3.3 V
1
μA
6.1
A
VDDQ discharge resistance in
non-tracking discharge mode
25
Ω
VTTREF discharge resistance
in non-tracking discharge mode
200
Ω
VTTFB discharge resistance in
non-tracking discharge mode
40
Ω
VFB_1SX threshold for final
tracking/Non-tracking discharge VFB_S1X to OUT_X
transition with internal divider
0.340
V
VFB_1SX threshold for final
tracking/Non-tracking discharge VFB_S1X to external divider
transition with external divider
0.160
V
Peak current limit
RCSNS = 50 kΩ
Soft-end section – DDR2/3 rails
Power management section – DDR2/3 rails
1.5
DSCG turn-off level
DSCG turn-on level
VAVCC = +5 V
EN_1S8 (S5), EN_VTT (S3)
Turn-Off Level
EN_1S8 (S5), EN_VTT (S3)
Turn-On Level
12/47
3.5
V
0.8
VAVCC = +5 V
2
Doc ID 13510 Rev 3
PM6641
Table 6.
Electrical characteristics
Electrical characteristics (continued)
Values
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
Power Good upper threshold
106
110
114
%
Power Good lower threshold
86
90
94
%
1
10
VTT LDO section – DDR2/3 rails
PG_VTT_TH
ILDOIN,ON
LDO input bias current in fullON state
EN_1S8 = EN_VTT = +5 V,
no load on VTT
ILDOIN,STR
LDO input bias current in
suspend-to-RAM state
EN_1S8 = +5 V, EN_VTT = 0 V,
no load on VTT
10
ILDOIN,STD
LDO input bias current in
suspend-to-disk state
EN_1S8 = EN_VTT = 0 V,
no load on VTT
3
IVTTFB, BIAS VTTFB bias current
EN_1S8 = EN_VTT = +5 V,
VVTTFB = VVOUT_1S8 /2
1
IVTTFB, LEAK VTTFB leakage current
EN_1S8 = +5 V, EN_VTT = 0 V,
VVTTFB = VVOUT_1S8 /2
1
IVTT,LEAK
VTT leakage current
EN_1S8 = +5 V, EN_VTT = 0 V,
VVTT = VVOUT_1S8 /2
LDO linear regulator output
voltage (DDR2)
EN_1S8 = EN_VTT = +5 V,
IVTT 0 A, VLDOIN = 1.8 V
0.9
LDO linear regulator output
voltage (DDR3)
EN_1S8 = EN_VTT = +5 V,
IVTT = 0 A, VLDOIN = 1.5 V
0.75
-10
V
-20
20
LDO output accuracy respect to EN_1S8 = EN_VTT = +5 V,
VTTREF, VLDOIN =1.8 V
-1 A < IVTT < 1 A
-25
25
EN_1S8 = EN_VTT = +5 V,
-2 A < IVTT < 2 A
-35
35
VVTT < 1.10*(VVOUT_1S8 /2)
2
2.3
3
VVTT > 1.10*(VVOUT_1S8 /2)
1
1.25
1.5
VVTT > 0.90*(VVOUT_1S8 /2)
-3
-2.3
-2
VVTT < 0.90*(VVOUT_1S8 /2)
-1.5
-1.25
-1
LDO source current limit
IVTT,CL
LDO sink current limit
μA
10
EN_1S8 = EN_VTT = +5 V,
-1 mA < IVTT < 1 mA
VVTT
μA
mV
A
VTTREF section – DDR2/3 rails
VVTTREF
IVTTREF
VTTREF output voltage
IVTTREF = 0A, VVOUT_1S8 = 1.8 V
VTTREF output voltage
accuracy relative to
VVOUT_1S8/2
-15 mA < IVTTREF < +15 mA,
VVOUT_1S8 = 1.8 V
VTTREF short circuit source
current
VVOUT_1S8 = 1.8 V, VVTTREF = 0 V
0.9
-2
V
2
%
40
mA
VTTREF short circuit sink
current
VVOUT_1S8 = 1.8 V, VVTTREF = 1.8 V
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-40
13/47
Typical operating characteristics
PM6641
5
Typical operating characteristics
Figure 3.
VDDQ and VTT soft-start
without load
Figure 4.
VDDQ and VTT soft-start with AVG
load
Figure 5.
1V5 soft-start without load
Figure 6.
1V5 soft-start with load
Figure 7.
1V05 soft-start without load
Figure 8.
1V05 soft-start without load
14/47
Doc ID 13510 Rev 3
PM6641
Figure 9.
Typical operating characteristics
VDDQ output ripple and phase @
AVG current
Figure 10. VTT, VTTREF output ripple @ AVG
current
Figure 11. 1V5 output ripple and phase @
AVG current
Figure 12. 1V05 output ripple and phase @
AVG current
Figure 13. SW reg. efficiency @ VIN = 3.3 V,
FSW = 600 kHz
Figure 14. VDDQ (1.8 V) load regulation
95
1,808
1,806
1,804
Output voltage (V)
Efficiency %
90
85
80
75
70
1,802
1,800
1,798
1V8
1,796
1,794
1,792
1V8
1V5
1V05
1,790
1,788
0,00
0,50
1,00
1,50
2,00
2,50
3,00
3,50
4,00
Loa d C ur r e nt [ A ]
65
1,0E-03
1,0E-02
1,0E-01
1,0E+00
1,0E+01
Load Current [A]
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Typical operating characteristics
PM6641
Figure 15. 1.5 V load regulation
Figure 16. 1.05 V load regulation
g
1,536
1,053
1,052
1,532
1,530
1V5
1,528
1,526
1,524
1,522
0,00
Output Voltage [V]
Output voltage (V)
1,534
1,051
1,050
1V05
1,049
1,048
0,50
1,00
1,50
2,00
Load Current [ A]
2,50
1,047
0,00
0,50
1,00
1,50
2,00
2,50
3,00
3,50
Load Current [A]
Figure 17. VDDQ (1.8 V) load transient: 0-AVG Figure 18. VTT load transient: -1 A +1 A
Figure 19. 1V5 load transient: 0-AVG
16/47
Figure 20. 1V05 load transient: 0-AVG
Doc ID 13510 Rev 3
PM6641
Typical operating characteristics
Figure 21. VDDQ e VTT soft-end with
DSCG = AVCC
Figure 22. VDDQ e VTT soft-end with
DSCG = AGND
Figure 23. Current limit
Figure 24. Soft-OV (1V05)
Figure 25. Output OV (1V5) @ RCSNS = 1 MΩ
Figure 26. Output UV (1V5)
Note:
All the above measures and screen captures are based on PM6641EVAL demonstration
board. Refer to PM6641 demonstration kit for details.
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Block diagram
6
PM6641
Block diagram
Figure 27. Functional and block diagram
VCC
+
_
PG_1S8
VIN_1S8
VREF+10%
+
_
ANTI X
COND
VIMAX
ASM
VREF-10%
ZERO
CROSS &
VALLEY
C.L.
0.9V
VTTREF
1.237V
VSW_1S8
VREF = 0.8V
VTTFB
VIMIN
LDOIN
_
PEAK
CURR.
LIMIT
HiZ
SGND_1S8
VTT
+
+
_
R
EN
NTD
NTD
R
VIMAX
VOUT_1S8
COMP_1S8
gm
PULSE
SKIP
?3
+
VFB_1S8
+
SET_PH1
_
VTTGND
VREF
0.9V
VIMIN
SS_1S8
OSC
_
SS CONTROL
SET_SWF
?1
?2
VIN_1S05
VIN_1S5
ANTI X
COND
ANTI X
COND
ASM
ASM
ZERO
CROSS &
VALLEY
C.L.
SW_1S05
PEAK
CURR.
LIMIT
ZERO
CROSS &
VALLEY
C.L.
VSW_1S5
PEAK
CURR.
LIMIT
SGND_1S05
SGND_1S5
_
_
VIMAX
gm
gm
OVP
UVP
_
+
PULSE
SKIP
VREF
PULSE
SKIP
SS
CONTROL
VIMIN
EN HiZ
VFB_1S5
VREF
VIMIN
SS_1S05
COMP_1S5
+
VFB_1S05
+
_
VIMAX
COMP_1S05
+
TD
NTD
SS_1S5
SS
CONTROL
THERMAL PROTECTION
VREF+10%
VREF+10%
CONTROL LOGIC
+
_
PG_1S05
+
_
OVP
UVP
UVLO
OVP
UVP
+
_
+
_
VREF-10%
VREF-10%
CSNS
Table 7.
TD
NTD
18/47
DSCG
AVCC
Legend
Tracking discharge enable
Non-tracking discharge enable
EN
VTTREF buffer enable
HiZ
LDO high impedance mode enable
Doc ID 13510 Rev 3
PG_1S5
PM6641
7
Device description
Device description
The PM6641 is an integrated voltage regulator module designed to supply DDR2/3 memory
and chipset I/O in real estate constrained portable equipment and ultra-mobile PCs. The
device consists of three buck regulators (two for chipset supply and one for main DDR
supply), a low drop-out (LDO) linear regulator capable of ±2 Apk (DDR termination voltage)
and a low noise buffered reference (DDR input buffer reference). It has been developed for
single-series Li-Ion battery stack powered equipment, allowing an input power supply from
2.7 V up to 5.5 V.
The PM6641 provides a compact solution by integrating DDR and chipset voltage regulators
on a single IC with internal power MOSFETs and requiring a minimum number of external
components. All its buck regulators are based on a current-mode control scheme with
integrated features to guarantee stability and fast load transient response. Each regulator
output voltage can be adjusted or a pre-fixed output voltage can be chosen, if external
components are unwanted. Each switching regulator has independent programmable softstart, to reduce inrush current, and output soft-end, to avoid inductor and MOSFETs high
peak current.
Other buck regulators features include output over-voltage and under-voltage protections,
programmable current limit and output Power Good signals high efficiency is achieved over
a wide range of load conditions by using a pulse-skipping technique at light load.
The PM6641 can detect the AVCC pin under-voltage through the under-voltage lock-out
(UVLO) block and it is able to limit its internal temperature through its auto-recovery thermal
shutdown.
The switching frequency of the buck controllers can be set in the range 500 kHz-1 MHz with
an external resistor or can be set equal to 750 kHz without external components use. All
buck regulators work at the same switching frequency with selectable phase shift.
The regulators can support both electrolytic and ceramic output capacitors because no
minimum output voltage ripple is required for stability purposes.
The PM6641 is provided in a QFN7x7 mm 48-pin lead-free package.
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Device description
7.1
PM6641
Memory supply
The DDR2/3 section of PM6641 is based on the VDDQ rail, the VTT termination rail and the
VTTREF reference voltage buffer.
The VDDQ rail is provided by a step-down switching regulator whose output voltage, by
default, is set to 1.8 V, in order to be compliant with DDR2 JEDEC specs. The output voltage
can also be adjusted using an external resistor divider. This rail performs latched output
under-voltage and over-voltage and auto-recovery current limit, without requiring external
sensing resistor.
The VTT termination rail is supplied by a low drop-out (LDO) linear regulator, able to sink
and source up to 2 A peak current. This regulator follows the half of the VDDQ rail and is a
replica of the VTTREF reference voltage buffer. When LDOIN is directly supplied by VDDQ,
i.e. the PM6641 1S8 rail, VTT and VDDQ can perform the so called tracking discharge, in
compliance with the JEDEC specs, as described in the following section. If higher efficiency
is required, VTT can be supplied by a lower voltage rail. An output capacitor of at least 20 µF
is the only external component required.
The VTTREF reference voltage buffer is always in tracking with the half of VDDQ and is able
to sink and source up to 15 mA with an accuracy of ±2% relative to VDDQ half. A 10 nF up
to 100 nF bypass capacitor for stability purposes is required.
7.1.1
VDDQ switching regulator
The VDDQ rail is provided by a constant frequency current-mode buck regulator, whose
frequency is set by inserting an external resistor between SET_SWF pin and AGND (see
Chapter 7.8: Switching frequency selection on page 29 section for details). The output
voltage can easily be set to 1.8 V by connecting the feedback pin VFB_1S8 directly to the
output rail, avoiding the use of external components. However, if a different output voltage is
desired, the VFB_1S8 pin must be connected to the central tap of a resistor divider.
The output voltage can be adjusted from 0.8 V up to the input voltage value, decreased by a
drop due to the high-side MOSFET on resistance.
(see Chapter 7.5: Output voltage divider on page 27 section for details).
The control loop needs to be compensated by inserting a resistor-capacitor series
connected between the COMP_1S8 pin and ground; if electrolytic capacitor with relevant
equivalent series resistance (ESR) are used, an additional capacitor between the
COMP_1S8 pin and ground can be useful (see Chapter 7.3: SW regulators control loop on
page 24 section for details). The classical slope compensation is internally implemented
and no external components are required.
The internal high-side PMOS and low-side NMOS allow the regulator to source an average
current of 2.8 A and a peak current of 5 A. The peak current limit protection is performed by
sensing the internal high side MOSFET current and can be decreased by inserting an
external resistor between CSNS pin and AGND (see Chapter 7.10: Peak current limit on
page 31 section for details).
This 1S8 rail is able to protect the load from Over-Voltage and Under-Voltage protection,
which avoid the output to be higher than 120% or lower than 60% of the nominal value (see
Chapter 7.11.1: Output overvoltage on page 33 and Chapter 7.11.2: Output under voltage
on page 33 section for details).
When the EN_1S8 pin goes high the VDDQ rail is turned on and the output voltage soft-start
is performed by slowly charging the rail output capacitor; this behavior is achieved because
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Doc ID 13510 Rev 3
PM6641
Device description
the loop voltage reference is increased linearly from zero up to 0.8V in a long time (up to a
couple of milliseconds) (see Chapter 7.6: Outputs soft-start on page 28 for details).
When the EN_1S8 pin goes low, the VDDQ rail output capacitor is discharged through
internal discharge MOSFET and, at the end of the capacitor discharge, the low side power
MOSFET is eventually closed (see Chapter 7.7: Outputs soft-end on page 29 for details).
The Power Good signal (PG_1S8 pin) is an open drain output, shorting the output to GND in
the following conditions:
●
When the 1.8 V rail output voltage is outside +/- 10% range from nominal value
●
When a protection (UV, OV, thermal) has been triggered
●
When the regulator is in soft-start.
When VDDQ and VTT rails are enabled, PG_1S8 is left floating and, as a consequence,
pulled-up by the external pull-up resistor, if both the rails are inside +/- 10% range of nominal
value. The PG_1S8 pin can sink current up to 4 mA when it’s asserted low.
7.1.2
VTT LDO and VTTREF buffered reference
The PM6641 provides the required DDR2/3 reference voltage on VTTREF pin. The internal
buffer tracks half the voltage on VOUT_1S8 pin and has a sink and source capability up to
15 mA with an accuracy of ±2% referred to the VDDQ half.
Higher currents rapidly deteriorate the output accuracy. A 10 nF to 100 nF (33 nF typical)
bypass capacitor to SGND is required for stability.
The VTT low-drop-out linear regulator has been designed to sink and source up to 2 A peak
current and 1 A continuously. The VTT voltage tracks VTTREF within ±35 mV. A remote
voltage sensing pin (VTTFB) is provided to recovery voltage drops due to parasitic
resistance. In DDR2/3 applications, the linear regulator input LDOIN is typically connected
to VDDQ output; connecting LDOIN pin to a lower voltage (if available in the system)
reduces the power dissipation of the LDO, but a minimum drop-out voltage must be
guaranteed, depending on the maximum current expected.
A minimum output capacitance of 20 µF (2x10 µF or single 22 µF ceramic capacitors) is
enough to assure stability and fast load transient response.
According to DDR2/3 JEDEC specifications, when the system enters the suspend-to-RAM
state (S5 high and S3 low) the LDO output is left in high-impedance while VTTREF and
VDDQ are still alive. When the suspend-to-disk state (S3 and S5 tied to ground) is entered,
all outputs are actively discharged by a tracking or a non-tracking discharge as selected
through the DSCG pin (see Chapter 7.7: Outputs soft-end on page 29 for details).
7.1.3
VTT and VTTREF soft-start
Soft-start on VTT and VTTREF outputs is achieved by current clamping. The LDO linear
regulator is provided of a current fold-back protection: when the output voltage exits the
internal ±10% VTT-Good window, the output current is clamped at ±1 A. Re-entering VTTGood window releases the current limit clamping. The fold-back mechanism naturally
implements a two steps soft-start charging the output capacitors with a 1 A constant current.
Something similar occurs at VTTREF pin, where the output capacitor is smoothly charged at
a fixed 40 mA (typ) current limit.
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Device description
7.1.4
PM6641
S3 and S5 power management pins
According to DDR2/3 memories supply requirements, the PM6641 can manage all S0 to S5
system states just connecting EN_VTT – EN_1S8 pins to their respective sleep-mode
signals in the notebook’s motherboard: connect EN_1S8 to S5 and EN_VTT to S3.
Keeping EN_VTT and EN_1S8 high, the S0 (full-on) state is decoded and the outputs are
alive.
In S3 state (EN_1S8 = 1, EN_VTT = 0), the PM6641 maintains VDDQ and VTTREF outputs
active and VTT output in high-impedance as needed.
In S4/S5 states (EN_1S8 = EN_VTT = 0) all outputs are turned off and, according to DSCG
pin voltage, the proper Soft-End is performed (see Chapter 7.7: Outputs soft-end on
page 29 section for details).
The following table resumes the DDR power supply states.
Table 8.
S3 and S5 sleep-states decoding
S3 (EN_VTT) S5 (EN_1S8)
7.2
System state
VDDQ
VTTREF
VTT
1
1
S0
(Full-on)
On
On
On
0
1
S3
(Suspend-to-RAM)
On
On
Hi-Z
0
0
S4/S5
(Suspend-to-disk)
Off (Discharge) Off (Discharge) Off (Discharge)
Chipset supply
The chipset power supply section is based on two constant frequency current-mode buck
regulators with a pre-fixed output voltage of 1.5 V and 1.05 V.
These two independent rails have programmable switching frequency, set by inserting an
external resistor between SET_SWF pin and AGND. The PM6641 allows also to manage
the switching regulators phases for 1.5 V, 1.05 V and 1.8 V (VDDQ) rails in order to limit the
RMS input current (see Chapter 7.8: Switching frequency selection on page 29 and
Chapter 7.9: Phase management on page 30 section for details).
The output voltages can easily be set to the pre-fixed value by connecting the feedback pins
VFB_1S5 and VFB_1S05 directly to the respective output rail, avoiding the use of external
components. However, if a different output voltage is desired, the feedback pins can be
independently connected to the central tap of a resistor divider.
The output voltage can be adjusted from 0.8 V up to the input voltage value, decreased by a
drop due to the high-side MOSFET on resistance.
(see Chapter 7.5: Output voltage divider on page 27 section for details).
Both regulators are current-mode step-down switching regulators whose control loop needs
to be compensated by inserting a resistor-capacitor series connected between the
compensation pin (COMP_1S5 and COMP_1S05) and ground; if electrolytic capacitor with
relevant equivalent series resistance (ESR) are used, an additional capacitor between this
compensation pin and ground can be useful (see Chapter 7.3: SW regulators control loop
on page 24 section for details). The classical slope compensation, which allows the peak
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Doc ID 13510 Rev 3
PM6641
Device description
current mode loop to avoid sub-harmonic instability with duty cycle greater than 50%, is
internally implemented and no further external components are required.
The chipset supply is able to source the following average and peak currents, assuming
1 A peak-to-peak inductor current ripple:
Table 9.
Chipset supply currents
Chipset supply rail [V]
Average current [A]
Peak current [A]
1.5
1.5
3.0
1.05
2.1
4.0
The peak current and the inductor ripple must be carefully evaluated in order to choose the
right current limit protection; this feature is performed by sensing the internal high side
MOSFET current and can be decreased by inserting an external resistor between CSNS pin
and AGND (see Chapter 7.10: Peak current limit on page 31 for details).
Both rails are able to protect the load from over-voltage and under-voltage protection, which
avoid the output to be higher than 120% or lower than 60% of the nominal value (see
Chapter 7.11.1: Output overvoltage on page 33 and Chapter 7.11.2: Output under voltage
on page 33 section for details).
When the EN_1S5 or EN_1S05 pin goes high the respective rail is turned on and the output
voltage soft-start is performed by slowly charging the rail output capacitor; this behavior is
achieved because the loop voltage reference is increased linearly from zero up to 0.8V (see
Chapter 7.6: Outputs soft-start on page 28 section for details). When the EN_1S5 or
EN_1S05 pin goes low, the respective rail output capacitor is discharged through internal
discharge MOSFET and, at the end of the capacitor discharge, the low side power MOSFET
is finally closed (see Chapter 7.7: Outputs soft-end on page 29 section for details).
Each rail has a dedicated pin to assert if its output voltage is not in the power good window,
i.e. if the output voltage drops 10% below or rises 10% above the nominal regulated value.
These power good signals (PG_1S5 and PG_1S05 pins) are open drain outputs, tied to
GND in the following conditions:
●
When the rail output voltage is outside +/- 10% range from nominal value
●
When a protection (UV, OV, thermal) has been triggered
●
When the regulator is in soft-start.
The PG_1S5 and PG_1S05 pins can sink current up to 4 mA when it’s asserted low.
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Device description
7.3
PM6641
SW regulators control loop
The PM6641 switching regulators are buck converters employing a constant frequency,
peak current mode PWM control loop, as shown in the following figure:
Figure 28. SW regulator control loop
Power Stage
IL
RES
VO
RO
CO
a
KL
VC
CRO
gm
RC
VREF
CC
Signal Stage
In the current mode constant frequency loop the power stage is represented by a controlled
current generator feeding the power stage output capacitor and load. The equivalent
transfer function is:
Equation 1
H(s) =
(sC ORES + 1) R
VO (s)
=
O
IL (s)
sC O (RES + R O ) + 1
with Co and Res being the output capacitance and its equivalent series resistance and Ro
representing the output load.
24/47
Doc ID 13510 Rev 3
PM6641
Device description
In order to obtain the typical integrative loop transfer function the signal stage must
compensate for the power stage pole (due to the output capacitor and the load) and zero
(above the loop bandwidth if ceramic output capacitors are selected). The signal stage
transfer function is:
Equation 2
G(s) = gmK L α
sC CR C + 1
⎛
⎞
C
sC C ⎜⎜ sCRoR C + Ro + 1⎟⎟
CC
⎝
⎠
Where gM is the power stage transconductance, KL is a design parameter and α is the gain
due to the output resistor divider (0.8 V / Vout). The external compensation network (Rc, Cc
and CRO) introduces:
●
One zero, to compensate the power stage pole:
CCR C = CO (RO + RES )
●
One pole in order to delete the static output voltage error;
●
One pole, if necessary, in order to compensate the high frequency zero due to the
output capacitor ESR:
CROR C = CORES
The control loop gain is obtained by multiplying G(s) by H(s):
Equation 3
GLOOP (s) = g mK L α
(sC CR C + 1)
⎛
⎞
C
sC C ⎜⎜ sCRoR C + Ro + 1⎟⎟
CC
⎝
⎠
⋅
(sC ORES + 1) R
O
sC O (RES + R O ) + 1
This model provides good results if the control loop cut-off frequency fCO is lower than about
fsw/10.
Doc ID 13510 Rev 3
25/47
Device description
7.4
PM6641
SW regulators pulse skipping and PWM mode
In order to enhance the light load efficiency each switching regulator enters the pulse
skipping algorithm when the output current sourced is too low. The threshold load current
which allows the regulator to enter the pulse skipping mode can be estimated with the
following formula: (Vi-Vo)/(2Lfsw)*Vo/Vi
Equation 4
( VI – VO ) VO
Iomin ≈ ------------------------ ⋅ ------( 2Lf SW ) V I
When the load current is lower than IOmin value, the switching regulator begins to skip some
cycle, decreasing the effective switching frequency and, as a consequence, reducing the
switching losses. This mode of operation is guaranteed by the presence of the zero crossing
current comparator, the internal block which senses the inductor current and avoids this
current to becoming negative, in the normal operating condition.
The inductor current is allowed to become negative when the output voltage rises above the
+10% power good threshold. In this condition of output soft over voltage the zero crossing
current comparator is deactivated and the pulse skipping algorithm is replaced by the typical
PWM one; as a consequence each switching regulator can sink up to some hundreds milli
amps to decrease the output voltage to the nominal value.
Figure 29. SW regulators pulse skipping and PWM mode
Vout
Vout
IL
IL
Clock
Clock
a) Pulse Skipping Mode
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Doc ID 13510 Rev 3
b) PWM Mode
PM6641
7.5
Device description
Output voltage divider
PM6641 switching regulators are adjustable voltage converters.
If the feedback pin (VFB_1S8, VFB_1S5, VFB_1S05 respectively belonging to
VDDQ (1.8 V), 1.5 V, 1.05 V rail) is directly tied to the rail output capacitor the internal divider
with pre-fixed output voltage value is activated and the nominal output voltages are
selected.
If the feedback pin is connected to the output voltage divider central tap (as depicted in
Figure 30)
Figure 30. SW regulator with external divider
Vout_1Sxx
R1
VFB_1Sxx
R2
the PM6641 switching regulator automatically recognizes the external divider and the output
voltage is regulated to the following value:
Equation 5
⎞
⎛R
Vout _ 1Sxx = ⎜⎜ 1 + 1⎟⎟ ⋅ 0.8V
R
⎠
⎝ 2
Doc ID 13510 Rev 3
27/47
Device description
7.6
PM6641
Outputs soft-start
The soft-start function of each switching regulator is achieved by ramping up the SS pin
voltage with a constant slew rate dV/dt.
When the switching section is enabled (EN high), the SS pin constant current charges the
capacitor connected between SS and ground pins.
The SS voltage is used as reference of the switching regulator and the output voltage of the
converter follows the ramp of the SS voltage. When the SS pin voltage is higher than 0.8 V,
the error amplifier uses the internal 0.8 V ±1% reference to regulate the output voltage.
Figure 31. SW regulator programmable soft-start
Iss
SS_1Sx
SW
Regulator
SS DO
VREF
During the soft-start period the current limit is set to the nominal value.
The dV/dt slope is set by charging the external capacitor with a 10 µA current. The
capacitance values has to be of the order of magnitude of 10 nF for a 1 msec soft-start
duration, as pointed out by the following formula:
Equation 6
C=
I ⋅ Δt 10μA ⋅ 1ms
=
= 12.5nF
ΔV
0. 8 V
During the soft-start the output under voltage management is not enabled, whereas the
output over voltage, the current limit and the thermal overheat are always monitored.
When the first switching regulator is turned on the output soft-start begins after an additional
delay of about 180 µs, due to PM6641 initializing and fuses reading.
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Doc ID 13510 Rev 3
PM6641
7.7
Device description
Outputs soft-end
When the switching regulator enable pin (EN_1S8 for the VDDQ section, EN_1S5 and
EN_1S05 for chipset sections) goes down or when UV or thermal protections are detected,
the switching regulator output capacitor is actively discharged through a dedicated
discharge MOSFET of about 25 Ω typical resistance.
The PM6641 DDR supply allows choosing between two different output discharge
behaviors, involving the VDDQ (1S8) switching rail, VTT LDO termination and VTTREF
reference buffered voltage: the tracking discharge and the non-tracking discharge. This
selection is set by tying the discharge pin (DSCG) to AVCC (tracking discharge enabled) or
to AGND (tracking discharge disabled).
When the 1.8 V rail is turned off (EN_1S8 goes low) and non-tracking discharge is active
(DSCG is low), or when UV or thermal protections are detected, the VDDQ and VTT rails
and the VTTREF buffer are discharged by internal discharge MOSFETs, through the
VSW_1S8, VTTFB and VTTREF pins respectively. VTT termination output capacitor is
discharged through 25 Ω dedicated MOSFET whereas VTTREF output capacitor is
discharged through 200 Ω dedicated MOSFET.
When the 1.8 V rail is turned off (EN_1S8 goes low) and tracking discharge is selected
(DSCG is high), tracking discharge takes place:
●
The 1.8 V rail regulator is discharged by internal MOSFET
●
The 0.9 V VTT LDO and VTTREF work in tracking with the half of 1.8 V rail
When the VTT LDO and VTTREF reach a voltage threshold of about 200-300 mV, the
device switches to non-tracking discharge mode and the internal discharge MOSFETs are
turned on.
7.8
Switching frequency selection
SET_SWF (pin 2) allows to vary the internal oscillator switching frequency, in the range of
500 kHz Ù 1 MHz, by connecting this pin to AGND through a resistor between
70 kΩ Ù 140k Ω.
The following table summarizes the output resistor – switching frequency correspondence:
Table 10.
Typical values for switching frequency selection
RSET_SWF (kΩ)
Approx. switching frequency (kHz)
140
500
100
670
70
1000
When SET_SWF is tied to AVCC the internal reference is chosen and each regulator
performs a typical 750 kHz switching frequency.
Doc ID 13510 Rev 3
29/47
Device description
7.9
PM6641
Phase management
When all the three switching regulators high side MOSFETs are turned on simultaneously
the input root mean square (RMS) current could rise up to very high values, increasing the
system losses and inducing external components overheating. It’s possible to reduce the
input overall RMS current by inserting one ceramic capacitor as close as possible to each
switching regulator power supply input, reducing the impulsive input current path. However
this synchronous mode of operation is jitter-free and noise immune.
Another possible way to reduce the input RMS current is based on the phase shifting
technique, which decreases the total input current by delaying the regulators turn on pulse.
With three regulators turned on, the 120d e.g. phase shifting allows to reduce the overall
input current up to 1.73 times as depicted in the following configuration, in which three
independent regulators with Vout/Vin lower than 0.333 and identical output current (I) are
managed with synchronous or 120 deg phase shifted turning on.
Figure 32. SW regulator phase management
IL1
IL1
IL2
+
+
IL3
+
+
=
=
ICIN
IL2
IL3
ICIN
Synchronous
120deg delay
Each regulator RMS input current is easily computed:
Equation 7
IL1,L 2,L 3 =
1
TSW
∫I
2
L1,L 2,L 3 dt
TSW
=
1
TSW
I2 TON
defining TSW the switching period, equal to 1 f
and TON the high side MOSFET on time.
SW
30/47
Doc ID 13510 Rev 3
PM6641
Device description
The synchronous mode of operation provides the following total input current:
Equation 8
ICIN,SYNC =
∫ (I
1
TSW
L1
+ IL 2 + IL 3 ) dt =
1
2
TSW
TSW
(3I)2 TON
whereas by shifting the three regulator turn on pulses of 120 deg the resulting total input
current is given by
Equation 9
ICIN,DELAY =
that is
1
TSW
∫ (I
+ IL 2 + IL 3 ) dt =
2
L1
TSW
1
TSW
(I
2
)
+ I2 + I2 TON
3 ≅ 1.73 times smaller than the one computed before.
The PM6641 SET_PH1 pin, if tied to AVCC, enables the synchronous switching regulators
high side MOSFET turn on, whereas if tied to ground enables the 120 deg phase shifting.
7.10
Peak current limit
The peak current limit performed by the PM6641 switching regulators allows to monitor,
cycle by cycle, the inductor current; this feature prevents IC wire bonding overheating and
failure.
If the current sensed on the monolithic high side MOSFET reaches the programmed current
limit the regulator starts behaving like a current generator, more than a voltage regulator.
Consequently, if the output load still increases the rail output capacitor discharges itself and
the regulator works as current generator until the output under voltage occurs and the
regulator is latched off (see Chapter 7.11.2: Output under voltage on page 33 section for
details).
The pin 4 (CSNS) allows to select the right value for the peak current limit by inserting an
external resistor (RCSNS) between this pin and ground. CSNS forces a constant voltage on
RCSNS resistor or, when tied to AVCC, enables the internal reference (equal to a 50 kΩ
external resistor). A simple equation shows how to compute the right value for RCSNS in
order to decrease the peak current limit:
Equation 10
RCSNS = α ⋅
Doc ID 13510 Rev 3
VREF
ICL
31/47
Device description
PM6641
where VREF = 0.9V is the constant voltage forced by CSNS pin, RCSNS [Ω] is the resistor
connected between CSNS and AGND, α is the coefficient that collects the MOS current
sensing scaling factor and other design parameters and ICL is the peak current limit [A].
The following table resumes values for all the switching regulators.
Table 11.
Typical SW regulators values
SW regulator
α
1.8V
333x10e3
1.5V
222x10e3
1.05V
278x10e3
The following graph is a plot of the switching regulators peak current limit, increasing the
RCSNS resistor:
Figure 33. SW regulators peak current limit
7.00
6.00
CL_1V8
CL_1V5
Current Limit [A]
5.00
CL_1V05
4.00
3.00
2.00
1.00
0.00
40
60
80
100
120
140
160
180
Rcsns [kOhm]
From the previous plot and table it’s clear that the three regulators peak current limits are
scaled; by changing the RCSNS external resistor the three peak current limits all change.
32/47
Doc ID 13510 Rev 3
PM6641
7.11
Device description
Fault management
PM6641 has been conceived to constantly monitor the rails output voltage. In order to
protect itself from failure and the load from damage, the device is able to:
●
Limit the power MOSFETs current
●
Detect output overvoltage
●
Detect output under voltage
●
Monitor the device temperature
●
Detect input power supply under voltage
The current limit is an auto-recovery protection, monitoring cycle by cycle the regulators
high side MOSFET current (see Chapter 7.10: Peak current limit on page 31 section for
details).
The output over voltage and under voltage and the input under voltage are latched
protections, whereas the thermal shutdown is auto-recovery; all these features are
described in the following sections.
7.11.1
Output overvoltage
If the output voltage of a switching regulator (memory supply rail VDDQ (1.8 V), chipset
supply rails 1.5 V or 1.05 V) becomes greater than 120% of its nominal value, an over
voltage (OV) protection for that rail is triggered. As a consequence the regulator stops
switching, the internal low-side power MOSFET of that rail is turned on and the high-side
MOSFET is turned off. The OV protection effect is the very quick discharge of the rail output
capacitor.
The OV condition is latched, and it can be reset only by toggling the enable pin of that rail or
by turning off and on the IC power supply (AVCC pin).
An OV condition for one of the outputs of the PM6641 has no effect on the operation of the
other outputs (e.g., if the OV protection is triggered for the VDDQ regulator, the 1.5 V and
1.05 V regulators continue to work normally).
7.11.2
Output under voltage
If the output voltage of a switching regulator (memory supply rail VDDQ (1.8 V), chipset
supply rails 1.5 V or 1.05 V) becomes lower than 60% of its nominal value (e.g. because the
rail was shorted to ground or the output load is increased dramatically), an under voltage
(UV) protection for that rail is triggered.
An UV condition causes the soft-end of the rail, which implies the regulator turn off and the
rail discharge MOSFET turn on (see Chapter 7.7: Outputs soft-end on page 29 section for
details); the UV condition is latched, and it can be reset only by toggling the enable pin of
that rail or by turning off and on the PM6641 power supply (AVCC pin).
As for OV protection, each switching regulator can perform under voltage protection without
affecting other regulators.
The over-current feature is implemented in the PM6641 by limiting the output current of
each rail (see Chapter 7.10: Peak current limit on page 31 section for details) and triggering
a latched UV protection if the output voltage falls because of a load requesting more current
than the limit.
Doc ID 13510 Rev 3
33/47
Device description
7.11.3
PM6641
Thermal shutdown
If the device temperature exceeds 150 °C, a thermal protection is triggered. As a
consequence, the output soft end takes place for all the outputs of the PM6641 (VDDQ rail
(1.8 V), VTT, VTTREF, 1.5 V, 1.05 V) by closing the output discharge MOSFET (see
Chapter 7.7: Outputs soft-end on page 29 section for details).
The thermal protection condition is not latched: the device leaves this condition and
reactivates itself automatically when its temperature falls below 135 °C (i.e. there is a 15 °C
of hysteresis).
7.11.4
Input under voltage lock-out
The PM6641 AVCC pin is the device power supply input. This pin must be fed with 5 V,
±10% in order to allow the device to work properly. If this rail falls under 3.9 V typical
threshold, the input under voltage is detected and the device performs the under voltage
lock-out (UVLO) protection. When this event occurs, each regulator stops switching and the
following actions are performed:
●
The memory supply rails (VDDQ, VTT and VTTREF) are discharged by closing the
output discharge MOSFET (see Chapter 7.7: Outputs soft-end on page 29 section for
details);
●
Chipset power supply output rails (1V5 and 1V05 rails) are discharged through the low
side power MOSFETs;
●
The device is turned OFF.
The PM6641 is turned on again when the AVCC pin voltage reaches the UVLO on threshold
(about 4.1 V).
34/47
Doc ID 13510 Rev 3
PM6641
8
Components selection
Components selection
The PM6641 switching regulator sections are buck converters employing a constant
frequency, current mode PWM current loop (see Chapter 7.3: SW regulators control loop on
page 24 section for details).
The duty-cycle of the buck converter is, in steady-state conditions, given by
Equation 11
D=
VOUT
VIN
The switching frequency directly affects two parameters:
8.1
●
Inductor size: greater frequencies mean smaller inductances. In notebook applications,
real estate solutions (i.e. low-profile power inductors) are mandatory also with high
saturation and root mean square (RMS) currents.
●
Efficiency: switching losses are proportional to the frequency. Generally, higher
frequencies imply lower efficiency.
Inductor selection
Once the switching frequency has been defined, the inductance value depends on the
desired inductor current ripple. Low inductance value means great ripple current that brings
to poor efficiency and great output noise. On the other hand a great current ripple is
desirable for fast transient response when a load step is applied.
Otherwise, great inductance brings to good efficiency but the load transient response is
critical, especially if VINmin - VOUT is little. The product of the output capacitor’s ESR
multiplied by the inductor ripple current must be taken in consideration; the PM6641
switching regulators current loop doesn’t need a minimum output ripple in order to work
properly, so a ceramic output capacitor can be considered a good choice.
A good trade-off between the transient response time, the efficiency, the cost and the size is
choosing the inductance value in order to maintain the inductor ripple current between 20%
and 50% (usually 30%) of the maximum output current.
The maximum inductor current ripple, ΔIL,MAX, occurs at the maximum input voltage.
With these considerations, the inductance value can be calculated with the following
expression:
Equation 12
L=
VIN − VOUT VOUT
⋅
fsw ⋅ ΔIL
VIN
where fSW is the switching frequency, VIN is the input voltage, VOUT is the output voltage and
ΔIL is the inductor current ripple.
Doc ID 13510 Rev 3
35/47
Components selection
PM6641
Once the inductor value is determined, the inductor current ripple is then recalculated:
Equation 13
ΔIL,MAX =
VIN,MAX − VOUT
fsw ⋅ L
⋅
VOUT
VIN,MAX
The next step is the computation of the maximum RMS inductor current:
Equation 14
IL,RMS = (ILOAD,MAX ) 2 +
(ΔIL,MAX ) 2
12
The inductor must have an RMS current greater than IL,RMS in order to assure thermal
stability.
Then the calculation of the maximum inductor peak current follows:
Equation 15
IL,PEAK = ILOAD,MAX +
ΔIL,MAX
2
IL,PEAK is important when choosing the inductor, in term of its saturation current.
The saturation current of the inductor should be greater than the maximum between ILpeak
and the programmed peak current limit, selected by an external resistor connected between
CSNS pin and AGND (as described in current limit section).
8.2
Input capacitor selection
In a buck topology converter the current that flows through the input capacitor is pulsed and
with zero average value. The RMS input current, for each switching regulator, can be
calculated as follows:
Equation 16
2
ICinRMS = ILOAD ⋅ D ⋅ (1 − D) +
1
D ⋅ (ΔIL ) 2
12
Neglecting the second term, the equation is reduced to:
Equation 17
ICinRMS ≅ ILOAD D ⋅ (1 − D)
36/47
Doc ID 13510 Rev 3
PM6641
Components selection
The losses due to the input capacitor are thus maximized when the duty-cycle is 0.5:
Equation 18
Ploss = ESR Cin ⋅ I2 CinRMS,MAX = ESR Cin ⋅ (0.5 ⋅ ILOAD,MAX )
2
The input capacitor should be selected with a RMS rated current higher than ICinRMS,MAX.
Tantalum capacitors are good in term of low ESR and small size, but they occasionally can
burn out if subjected to very high current during operation. Multi-Layers-Ceramic-Capacitors
(MLCC) have usually a higher RMS current rating with smaller size and very low ESR.
When only one common input capacitor is chosen for the application, instead of one
dedicated capacitor for each regulator (close to each input power supply pins), the total
input current can be quite different from the arithmetic sum of the buck regulators RMS input
currents, if phase management is allowed (see Chapter 7.9: Phase management on
page 30 section for details).
8.3
Output capacitor selection
Using tantalum or electrolytic capacitors, the selection is made referring to ESR and voltage
rating rather than by a specific capacitance value.
The output capacitor has to satisfy the output voltage ripple requirements. At a given
switching frequency, small inductor values are useful to reduce the size of the choke but
increase the inductor current ripple. Thus, to reduce the output voltage ripple a low ESR
capacitor is required:
Equation 19
ESR ≤
VRIPPLE,MAX
ΔIL,MAX
where VRIPPLE is the maximum tolerable ripple voltage.
The zero introduced by the output capacitor ESR must be higher than the switching
frequency or must be compensated (see Chapter 7.3: SW regulators control loop on
page 24 section for details):
Equation 20
1
f SW > f Z = ------------------------------------------2π ⋅ ESR ⋅ C OUT
In order to minimize the output voltage ripple, ceramic capacitors are suggested.
Doc ID 13510 Rev 3
37/47
Components selection
PM6641
If ceramic capacitors are used, the output voltage ripple due to inductor current ripple is
negligible. Then the inductance could be smaller, reducing the size of the choke. In this case
it is important that output capacitor can adsorb the inductor energy without generating an
overvoltage condition when the system changes from a full load to a no load condition.
The minimum output capacitance can be chosen by the following equation:
Equation 21
C OUT,min =
L ⋅ I2 LOAD,MAX
Vf 2 − Vi 2
where Vf is the output capacitor voltage after the load transient and Vi is the output capacitor
voltage before the load transient.
8.4
SW regulator compensation components selection
As described in section SW regulators control loop, the PM6641 switching regulators control
loop is:
Equation 22
GLOOP (s) = g mK L α
(sC CR C + 1)
⎛
⎞
C
sC C ⎜⎜ sCRoR C + Ro + 1⎟⎟
CC
⎝
⎠
⋅
(sC ORES + 1) R
O
sC O (RES + R O ) + 1
If the output capacitor CO and its equivalent series resistance (ESR) RES provide a low
frequency zero, f = 1
, the roll-off compensation pole must be added:
zo
2πC ORES
Equation 23
fPRO ≅
1
2πCROR C
This pole is useful if the fzo zero is greater than about fC0
.
5
However, the first assumption must relate the cross-over frequency, fCO, with the control
loop gain:
Equation 24
GLOOP (j2πfCO ) ≅ g mK L α
38/47
2πfCO C CR C
R CR O
R O = g mK L α
2πfCO C C ⋅ 2πfCO C O (RES + R O )
2πfCO C O (RES + R O )
Doc ID 13510 Rev 3
PM6641
Components selection
From the definition of cross-over frequency, the value of the compensation resistor is
derived:
Equation 25
GLOOP ( j2πfCO ) = 1 ⇒ R C =
2πfCO C O (RES + R O )
g m K L αR O
A good choice for the cross-over frequency is to assign fCO equal to fSW
.
10
The fixed parameters gm = 300 μs and KL = 4.4 s are design parameters, whereas the
feedback divider factor (α) is application dependant (see Chapter 7.3: SW regulators control
loop on page 24 section for details).
After computing RC, the compensation capacitor can be designed in order to place the
compensation zero near the power stage pole:
Equation 26
CC =
C O (R O + RES )
RC
The roll-off capacitance, as said previously, must compensate for the power stage high
frequency zero, when necessary:
Equation 27
CRO =
C ORES
RC
As final step, it’s important to verify that the compensation zero is quite far from the crossover frequency. An empirical rule is satisfied if the following holds:
Equation 28
fZC =
f
1
≤ CO
2πC CR C
5
All these considerations are true if the cross-over frequency is quite lower than the switching
frequency, and the compensation zero and the power stage pole are far enough from fCO.
Doc ID 13510 Rev 3
39/47
Components selection
8.5
PM6641
Layout guidelines
Each signal is referred to AGND, the analog ground. In a typical 4-layers PCB one internal
layer should be dedicated to this common ground. The IC thermal pad must be connected to
AGND plane through multiple VIAs, in order to remove the IC heat and to obtain the best
performance. Furthermore, each switching regulator has a dedicated power ground
(SGND_1Sxx); all these SGNDs must be star-connected, in a single point, with AGND.
For each switching section the power components (inductor and input/output capacitors)
must be placed near the VSW_1Sxx, VIN_1Sxx and SGND_1Sxx pins and connected with
large (at least 20 mils or larger) and short PCB traces, in order to limit the path of the current
high frequency components and, consequently, to reduce the injected noise. If the power
components routing involves more than one layer, as many VIAs as possible must be
inserted to reduce the series resistance and improve the global efficiency.
The VTT external components (input and output capacitors) must be placed near the LDO
regulator input (LDOIN) and output (VTT) pins, and must be routed with large and short
traces, in order to limit the parasitic series resistance.
The feedback pins (VFB_1Sxx and VTTFB) must reach the feedback points through
dedicated PCB traces, typically 10 mils width; larger feedback traces are not required.
For reference layout, refer to PM6641 demonstration kit document.
40/47
Doc ID 13510 Rev 3
PM6641
9
Application examples
Application examples
The following application examples are typical or customized applications. Each example
has been tested and evaluated and the schematic and BOM are available for reference
design.
9.1
UMPC DDR2 and chipset power supply
Figure 34. System architecture for DDR2 and chipset power supply
VDDQ
1.8V @ 2.5A
3.3V
VTT (LDO)
0.9V @ 2A
PM6641
1.5V @ 2.8A
1.05V @ 4A
This application is conceived for real estate constrained portable equipment with DDR2
memory. An input power voltage pre-regulated to 3.3 V or 5 V is available and the available
output maximum power levels are shown in Figure 34. The switching regulator average load
is estimated to be about 50% of the maximum load; this upper limit must be respected in
order to avoid dangerous stresses for internal power MOSFETs. The following table
resumes these current values.
Table 12.
Expected average and peak currents for DDR2 and chipset power supply
Output rail
Max non continuous load [A]
Expected average load [A]
1.8 V (VDDQ)
2.5
1.3
0.9 V (VTT)
±2
0.3
1.5 V
2.8
1.4
1.05 V
4
2
Doc ID 13510 Rev 3
41/47
1
TP9
VOUT_1S8
1
VCC
C1
R1
0603-3R3
1
L1
2
AVCC
C22
0603-330p
R11
0603-100k
VIN
C6
1206 - 100u
0603-22n
C19
C2
0805-10u
C15
1206 - 100u
0603-100n
0603-22n
C21
C24
0603-330p
R13
0603-68k
0603-join
R32
2839-1u0
49
1
2
3
4
5
6
7
8
9
10
11
12
C12
0805-10u
0603-33n
C18
1
AVCC
1
C16
1
0603-1u
AGND_1
SET_SWF
VOUT_1S8
CSNS
SGND_1S8_1
SGND_1S8_2
VSW_1S8_1
VSW_1S8_2
VIN_1S8_1
VIN_1S8_2
VFB_1S8
COMP_1S8
THERMAL
1
2
AVCC
C11
1206-22u
48
47
46
45
44
43
42
41
40
39
38
37
U1
PM6641_QFPN
L3
2839-1u
GND
1
VOUT_1S05
TP13
C10
1206 - 100u
1
36
35
34
33
32
31
30
29
28
27
26
25
TP12
C9
1206 - 100u
EN_VTT
EN_1S5
EN_1S05
VIN_1S5
VSW_1S5_2
VSW_1S5_1
SGND_1S5_2
SGND_1S5_1
VFB_1S5
COMP_1S5
SS_1S5
PG_1S5
VCC
VTT_FB
DSCG
VTTREF
LDO_IN
VTT
VTT_GND
AVCC
AGND_2
SET_PH1
AGND_3
EN_1S8
SS_1S8
SS_1S05
COMP_1S05
VFB_1S05
SGND_1S05_1
SGND_1S05_2
VSW_1S05_1
VSW_1S05_2
VIN_1S05_1
VIN_1S05_2
PG_1S05
PG_1S8
13
14
15
16
17
18
19
20
21
22
23
24
2
1
TP6
AGND
C4
0805-10u
VIN
C20
0603-22n
R12
0603-47k
1
2
2839-1u5
C23
0603-470p
L2
VIN
1
VIN
TP7
R17
0603-68k
C7
1206 - 100u
C3
0805-10u
0603-100p
C25
R18
0603-68k
AVCC
R22
0603-68k
AVCC
R19
0603-68k
1
2
3
4
8
7
6
5
TP4
PG_1S05
SW DIP-4
SW1
TP2
PG_1S8
0603-100p
C28
R23
0603-68k
TP3
PG_1S5
0603-100p
C27
R21
0603-68k
0603-100p
C26
R20
0603-68k
1
TP14
VTT
1
Doc ID 13510 Rev 3
1
TP1
VTTREF
TP10
VOUT_1S5
1
42/47
TP5
VCC
Application examples
PM6641
The default switching frequency has been selected (750 kHz) and the tracking discharge
has been enabled in agreement with DDR2 JEDEC specifications. No external resistor
dividers are required for these output voltage levels. The allowed inductor current ripple is
about 35% of the expected peak load.
The power and signal components have been selected in agreement with Chapter 8 on
page 35 equations.
The following schematic and bill of materials (BOM) are for reference design.
Figure 35. Suggested schematic for DDR2 and chipset power supply
PM6641
Application examples
Table 13.
BOM suggested components for DDR2 and chipset power supply
Qty
Component
Description
Package
1
C1
Ceramic, 10 V, X5R, 10%
SMD 0603
4
C2, C3, C4,
C12
Ceramic, 10 V, X5R, 10%
SMD 0805
5
C6, C7, C9,
C10, C15
Ceramic, 4 V, X5R, 20%
1
C11
1
MFR
Value
Standard
1 µF
GRM21BR61A106KE19
Murata
10 µF
SMD 1206
AMK316BJ107ML
Taiyo Yuden
100 µF
Ceramic, 6.3 V, X5R, 10%
SMD 1206
GRM31CR60J226KE19
Murata
22 µF
C16
Ceramic, 16 V, X7R, 10%
SMD 0603
Standard
100 nF
1
C18
Ceramic, 25 V, X7R, 10%
SMD 0603
Murata
33 nF
3
C19, C20, C21
SMD 0603
Standard
22 nF
2
C22, C24
Ceramic, 50 V, C0G, 5%
SMD 0603
Standard
330 pF
1
C23
Ceramic, 50 V, C0G, 5%
SMD 0603
Standard
470 pF
4
C25, C26, C27,
C28
Ceramic, 50 V, C0G, 5%
SMD 0603
Standard
100 pF
1
R1
Chip resistor, 0.1 W, 1%
SMD 0603
Standard
3R3
1
R11
Chip resistor, 0.1 W, 1%
SMD 0603
Standard
100 kΩ
1
R12
Chip resistor, 0.1 W, 1%
SMD 0603
Standard
47 kΩ
8
R13, R17, R18,
R19, R20, R21,
R22, R23
Chip resistor, 0.1 W, 1%
SMD 0603
Standard
68 kΩ
1
R32
Chip resistor, 0.1 W, 1%
SMD 0603
Standard
0Ω
2
L1, L3
SMT 11 Arms, 9.5 mΩ
SMD 2827
744312100 /LF
Würth
1.0 µ
1
L2
SMT 9 Arms, 10.5 mΩ
SMD 2827
744312150 /LF
Würth
1.5 µ
1
U1
IC VR - 48 PIN
VFQFPN 7x7
PM6641
ST
PM6641
Note:
Part number
GRM188R71E333KA01
This applicative solution has been tested and the PM6641EVAL demonstration board is now
available for demonstration.
Please refer also to PM6641 demonstration kit document for test and measurement results.
Doc ID 13510 Rev 3
43/47
Package mechanical data
10
PM6641
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 14.
VFQFPN-48 (7x7x1.0 mm) package mechanical data
mm
Dim.
Min.
Typ.
Max.
0.80
0.90
1.00
A1
0.02
0.05
A2
0.65
1.00
A3
0.25
A
b
0.18
0.23
0.30
D
6.85
7.00
7.15
D2
2.25
4.70
5.25
E
6.85
7.00
7.15
E2
2.25
4.70
5.25
e
0.45
0.50
0.55
L
0.30
0.40
0.50
ddd
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0.08
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Package mechanical data
Figure 36. VFQFPN-48 (7x7x1.0 mm) package drawings
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Revision history
11
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Revision history
Table 15.
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Document revision history
Date
Revision
Changes
16-May-2007
1
Initial release
16-Jan-2008
2
Document status promoted from preliminary data to datasheet.
Updated: Table 2 on page 6, Table 3 on page 8, Table 6 on page 10,
Chapter 7: Device description on page 19,
Added: Chapter 9: Application examples on page 41., Chapter 8.5:
Layout guidelines on page 40
04-May-2009
3
Updated Table 4 on page 8
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