PM6675ATR

PM6675A High efficiency step-down controller with embedded 2A LDO regulator Target Specification Features switching ■ ■ Switching section – 4.5V to 36V input voltage range – 0.6V, ±1% voltage reference – Selectable 1.5V fixed output voltage – Adjustable 0.6V to 3.3V output voltage – 1.237V ±1% reference voltage available – Very fast load transient response using constant-on-time control loop – No RSENSE current sensing using low side MOSFETs' RDS(ON) – Negative current limit – Latched OVP and UVP – Soft start internally fixed at 3ms – Selectable pulse skipping at light load – Selectable No-Audible (33KHz) pulse skip mode – Ceramic output capacitors supported – Output voltage ripple compensation – Output soft-end ) s ( ct LDO regulator section – Adjustable 0.6V to 2.5V output voltage – Selectable ±1Apk or ±2Apk current limit – Dedicated power-good signal – Ceramic output capacitors supported – Output soft-end u d o r P e t e l o Applications VFQFPN-24 4x4 Description c u d ) s t( The PM6675A device consists of a single high efficiency step-down controller and an independent Low Drop-Out (LDO) linear regulator. e t le o r P The Constant On-Time (COT) architecture assures fast transient response supporting both electrolytic and ceramic output capacitors. An embedded integrator control loop compensates the DC voltage error due to the output ripple. o s b O - Selectable low-consumption mode allows the highest efficiency over a wide range of load conditions. The low-noise mode sets the minimum switching frequency to 33kHz for audio-sensitive applications. The LDO linear regulator can sink and source up to 2Apk. Two fixed current limit (±1A- ±2A) can be chosen. An active Soft-End is independently performed on both the switching and the linear regulators outputs when disabled. s b O ■ Industrial application on 24V ■ Graphic cards ■ Embedded computer systems Order codes Part number Package Packaging PM6675A VFQFPN-24 4x4 (Exposed Pad) Tube October 2006 Rev 1 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. 1/15 www.st.com 15 Contents PM6675A Contents 1 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ) s t( 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 c u d e t le ) s ( ct u d o r P e t e l o s b O 2/15 o s b O - o r P PM6675A Typical application circuit 1 Typical application circuit Figure 1. Application circuit +5V R LP VIN C IN3 C IN2 R1 C IN R2 23 8 22 VOSC 18 VCC 6 AVCC C IN4 10 VSEL LILIM VLDOIN 12 NOSKIP 3 B O O HGATE 21 T PHASE LIN 4 LPG LDO PG 24 VLDO L 20 PM6675A LOUT CSNS 5 15 14 13 C OUT2 SMPS PG ) s ( ct 7 COMP VREF LEN SPG SGND LGND SWEN PGND VSNS uc 19 16 ) s t( VSMPS LGATE 17 2 LFB 1 C BOOT R LIM 9 11 P e let d o r C OUT C INT o s b O C BYP u d o r P e t e l o s b O 3/15 Pin settings PM6675A 2 Pin settings 2.1 Connections CSNS PHASE HGATE BOOT LIN Pin connection (through top view) LOUT Figure 2. 19 24 1 18 LGND VCC LFB LGATE NOSKIP PGND PM6675A LPG c u d SPG LEN SGND 6 e t le 12 ) s ( ct u d o r P e t e l o s b O 4/15 COMP VSEL VSNS o s b O VOSC VREF 7 LILIM AVCC o r P 13 SWEN ) s t( PM6675A 2.2 Pin settings Pin description Table 1. Pin functions N° Pin 1 LGND 2 LFB 3 NOSKIP 4 LPG 5 SGND Ground Reference for analog circuitry, control logic and VTTREF buffer. Connect together with the thermal pad and VTTGND to a low impedance ground plane. See the Application Note for details. 6 AVCC +5V supply for internal logic. Connect to +5V rail through a simple RC filtering network. 7 VREF High accuracy output voltage reference (1.237V) for multilevel pins setting. It can deliver up to 50uA. Connect a 100nF capacitor between VREF and SGND in order to enhance noise rejection. 8 VOSC Frequency Selection. Connect to the central tap of a resistor divider to set the desired switching frequency. The pin cannot be left floating. See Device Description section for details. VSNS Switching section output remote sensing and discharge path during output Soft-End. Connect as close as possible to the load via a low noise PCB trace. VSEL Fixed output selector and feedback input for the switching controller. If VSEL pin voltage is higher than 4V, the fixed 1.5V output is selected. If VSEL pin voltage is lower than 4V, it is used as negative input of the error amplifier. See Mode of Operation Selection section for details. COMP DC voltage error compensation pin for input the switching section. Refer to Mode of Operation Selection section for more details. 9 10 11 LDO power ground. Connect to negative terminal of VTT output capacitor. LDO remote sensing. Connect as close as possible to the load via a low noise PCB trace. Pulse-Skip/No-Audible Pulse-Skip Modes selector. See Mode of Operation Selection section for details. LDO section Power-Good signal (open drain output). High when LDO output voltage is within ±10% of nominal value. c u d e t le ) s ( ct ) s t( o r P o s b O - u d o 12 LILIM Current limit selector for the LDO. Connect to SGND for ±1A current limit or to +5V for ±2A current limit. 13 SWEN Switching Controller Enable. When tied to ground, the switching output is turned off and a Soft-End is performed. 14 LEN Linear Regulator Enable. When tied to ground, the LDO output is turned off and a Soft-End is performed. 15 SPG Switching Section Power-Good signal (open drain output). High when the switching regulator output voltage is within ±10% of nominal value. 16 PGND Power ground for the switching section. 17 LGATE Low-side gate driver output. 18 VCC r P e t e l o s b O Function +5V low-side gate driver supply. Bypass with a 100nF capacitor to PGND. 5/15 Pin settings PM6675A Table 1. Pin functions (continued) N° Pin Function 19 CSNS Current sense input for the switching section. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDSon sensing) or to the source of the synchronous rectifier (RSENSE sensing) to set the current limit threshold. 20 PHASE Switch node connection and return path for the high side gate driver. 21 HGATE High-Side Gate Driver Output 22 BOOT Bootstrap capacitor connection. Input for the supply voltage of the high-side gate driver. 23 LIN 24 LOUT Linear Regulator Input. Bypass to LGND by a 10µF ceramic capacitor for noise rejection enhancement. LDO linear regulator output. Bypass with a 20µF (2x10µF MLCC) filter capacitor. c u d e t le ) s ( ct u d o r P e t e l o s b O 6/15 o s b O - o r P ) s t( PM6675A Electrical data 3 Electrical data 3.1 Maximum rating Table 2. Absolute maximum ratings (1) Symbol Parameter Value VAVCC AVCC to SGND -0.3 to 6 VVCC VCC to SGND -0.3 to 6 PGND, LGND to SGND VPHASE -0.3 to 0.3 HGATE and BOOT to PHASE -0.3 to 6 HGATE and BOOT to PGND -0.3 to 44 PHASE to SGND -0.3 to 38 LGATE to PGND -0.3 to VVCC +0.3 V ) s t( CSNS, SPG, LEN, SWEN, LILIM, COMP, VSEL, VSNS, VOSC, VREF, NOSKIP to SGND -0.3 to VAVCC + 0.3 LPG,VREF, LOUT, LFB to SGND -0.3 to VAVCC + 0.3 LIN, LOUT, LPG, LIN to LGND c u d o r P -0.3 to VAVCC + 0.3 Power dissipation @TA = 25°C PTOT Unit 2.3 e t le W 1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 3.2 Thermal data ) s ( ct Table 3. Thermal data Symbol RthJA TSTG t e l o TJ Parameter Value Unit 42 °C/W Storage temperature range -40 to 150 °C Operating ambient temperature range -40 to 85 °C Junction operating temperature range -25 to 125 °C Thermal resistance junction to ambient u d o r P e TA o s b O - s b O 7/15 Electrical characteristics 4 PM6675A Electrical characteristics TA = 0°C to 85°C , VCC = AVCC = +5V, LIN = 1.5V and LOUT= 0.9V if not otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit V Supply section VIN Input voltage range 4.5 36 VAVCC IC supply voltage 4.5 5.5 VVCC IC supply voltage 4.5 5.5 IIN Operating current (Switching + LDO) ISW SWEN, LEN, VSEL and NOSKIP connected to AVCC, No load on LOUT output. Shutdown operating current UVLO 4.0 AVCC Under Voltage Lockout upper threshold so ON-time (SMPS) On-time duration tOFFMIN (s) ct u d o OFF-time (SMPS) r P e d o r P e let UVLO hysteresis tON uc SWEN and LEN tied to SGND. AVCC Under Voltage Lockout upper threshold b O - ) s t( mA SWEN, VSEL and NOSKIP connected to AVCC, LEN connected to SGND. Operating current (Switching) ISHDN 2 3.8 4.1 1 10 µA 4.2 V 3.9 4.0 50 mV VSEL and NOSKIP high, VOSC = 300mV 650 750 850 VVSNS = 2V VOSC = 500mV 390 450 510 300 350 ns 1.237 1.249 V ns Minimum Off-Time Voltage reference t e l o s b O Voltage accuracy 4.5V< VIN < 25V Load regulation -50µA< IVREF < 50µA 1.224 -4 4 mV Undervoltage Lockout Fault Threshold 800 SMPS output SMPS fixed output voltage (1) VOUT Output voltage accuracy (1) 1. Guaranteed by design. Not production tested. 8/15 VSEL connected to AVCC, NOSKIP tied to SGND, No Load 1.5 -2 V 2 % PM6675A Electrical characteristics Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit CSNS input bias current 90 100 110 µA Comparator offset -5 Current limit and zero crossing comparator ICSNS VPGND - VCSNS Positive current limit threshold 5 -115 -100 -85 -130 -110 -90 -10 -5 0 HGATE high state (pullup) 2.0 3 HGATE low state (pulldown) 1.8 2.7 LGATE high state(pullup) 1.4 LGATE low state (pulldown) 0.6 ) s t( o r P 115 118 70 73 107 110 113 87 90 93 107 110 113 87 90 93 mV Fixed negative current limit threshold VZC,OFFS Zero crossing comparatot offset High and low side gate drivers HGATE driver on-resistance 2.1 LGATE driver on-resistance c u d UVP/OVP protections and PGOOD signals OVP Over voltage threshold UVP Under voltage threshold 112 63 e t le SMPS upper threshold SMPS lower threshold so PGOOD LDO upper threshold LDO lower threshold (s) t c u Soft start section (SMPS) r P e 1 µA 150 250 mV 2 3 4 ms 22.5 25 27.5 22.5 25 27.5 ILPG,SINK = ISPG,SINK = 4mA od Soft-start ramp time (4 steps current limit) Soft-start initial current limit t e l o Soft-start current limit step 0.9 % SPG and LPG forced to 5.5V IPG,LEAK SPG and LPG leakeage current¹ VPG,LOW SPG and LPG low level voltage b O - Ω µA Soft end section bs O Switching section discharge resistance 25 LDO section discharge resistance 25 Ω LDO section VLREF LDO reference voltage VDROP LDO drop-out voltage 0.594 VLOUT = 0.9V, ILOUT =1A, -10% output drop 0.6 0.606 V 0.25 9/15 Electrical characteristics PM6675A Table 5. Electrical characteristics (continued) Symbol Parameter Test condition LDO Internal high-side MOSFET RDS(on) LDO source current limit ILOUT = 1A, AVCC = 5V LDO sink current limit 0.2 0.23 Ω 2.1 2.2 VLFB < 1.10* VLREF, LILIM = 0V 1 1.1 1.2 -2.2 -2.1 -2 0.90* VLREF < VLFB < 1.10* VLREF, LILIM = 0V -1.2 -1.1 -1 VLFB > 1.10* VLREF, LILIM = 5V -1.2 -1.1 -1 VLFB > 1.10* VLREF, LILIM = 0V -0.6 -0.55 -0.6 1 10 LDO input bias current, On LEN connected to AVCC, no load LDO input bias current, Off LEN = 0V, no load -1 ILFB,LEAK LFB leakage current LEN = 0V, VLFB = 0.6V -1 Power management section e t le Fixed mode VVTHVSEL VSEL pin thresholds Adjustable mode o s b O - Forced-PWM Mode NOSKIP pin thresholds (1) No-Audible Mode ct du Logic input leakage current (1) o r P e (s) ±2A LDO Current Limit ±1A LDO Current Limit LEN, SWEN and LILIM=5V c u d o r P 1 1 3.7 4.2 1.0 3.5 2.4 0.8 1 1 IOSC,LEAK VOSC pin leakage current (1) 1 t e l o V 0.5 IIN3,LEAK Multilevel input leakage current (1) VSEL and NOSKIP=5V VOSC=1V µA 4.3 Pulse-Skip Mode VVTHLILIM LILIM pin thresholds (1) ) s t( 1 ILFB,BIAS LFB input bias current IIN,LEAK Unit 2 LEN connected to AVCC VLFB = 0.6V KIP Max. A ILDO,CL VVTHNOS Typ. VLFB < 1.10* VLREF , LILIM = 5V 0.90* VLREF < VLFB < 1.10* VLREF, LILIM = 5V ILIN,BIAS Min. µA Thermal shutdown TSHDN s b O Shutdown temperature (1) 1. Guaranteed by design. Not production tested. 10/15 150 °C PM6675A Block diagram 5 Block diagram Figure 3. Functional and block diagram VREF VOSC Vr = 0.6V 1.236V Bandgap BOOT LFB Level shifter Ton HGATE 1-shot LIN PHASE Ton min 1-shot _ LOUT Anti Cross Conduction VCC Toff min 1-shot LILIM LGATE + PGND LDS c u d LEN 0.6V Zero Crossing & Current Limit LGND _ Vr +10% LPG SWEN + - UVP/OVP od r P e LILIM t e l o NOSKIP s b O (s) t c u UVLO SWEN o s b O _ gm + Vr -10% AVCC e t le + + - SGND VREF Vr LDS LDS COMP + - Vr SPG + Vr -10% LEN VSNS Thermal Shutdown SWEN CSNS Vr +10% CONTROL LOGIC LEN o r P ) s t( SDS adj fix VSEL Table 6. Legend SWEN Switching controller enable LEN LDO regulator enable LDS LDO output discharge enable SDS Switching output discharge enable LILIM LDO regulator current limit 11/15 Package mechanical data 6 PM6675A Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 7. VFQFPN-24 4mm x 4mm mechanical data mm. Dim. Typ A A1 0.00 A2 0.65 D 4.00 D1 3.75 E 4.00 E1 3.75 0.42 e 0.50 N 24.00 Nd 6.00 b ct u d o D2 r P e t e l o s b O 12/15 1.00 0.05 0.05 ) s t( c u d e t le o r P 12° 0.60 0.30 0.50 0.18 0.30 2.10 1.95 2.25 2.10 1.95 2.25 o s b O - 6.00 L E2 0.80 0.24 (s) Ne Max. 0.80 θ P Min. 0.40 PM6675A Package mechanical data Figure 4. Package dimensions c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 13/15 Revision history 7 PM6675A Revision history Table 8. Revision history Date Revision 11-Oct-2006 1 Changes Initial release. c u d e t le ) s ( ct u d o r P e t e l o s b O 14/15 o s b O - o r P ) s t( PM6675A Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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