PM6675
High efficiency step-down controller
with embedded 2A LDO regulator
Preliminary Data
Features switching
■
■
Switching section
– 4.5V to 28V input voltage range
– 0.6V, ±1% voltage reference
– Selectable 1.5V fixed output voltage
– Adjustable 0.6V to 3.3V output voltage
– 1.237V ±1% reference voltage available
– Very fast load transient response using
constant on-time control loop
– No RSENSE current sensing using low side
MOSFETs' RDS(ON)
– Negative current limit
– Latched OVP and UVP
– Soft start internally fixed at 3ms
– Selectable pulse skipping at light load
– Selectable No-Audible (33KHz) pulse skip
mode
– Ceramic output capacitors supported
– Output voltage ripple compensation
– Output soft-end
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LDO regulator section
– Adjustable 0.6V to 3.3V output voltage
– Selectable ±1Apk or ±2Apk current limit
– Dedicated Power-Good signal
– Ceramic output capacitors supported
– Output soft-end
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Applications
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Notebook computers
■
Graphic cards
■
Embedded computers
VFQFPN-24 4x4
Description
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The PM6675 device consists of a single high
efficiency step-down controller and an
independent Low Drop-Out (LDO) linear
regulator.
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The Constant On-Time (COT) architecture
assures fast transient response supporting both
electrolytic and ceramic output capacitors. An
embedded integrator control loop compensates
the DC voltage error due to the output ripple.
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A selectable low-consumption mode allows the
highest efficiency over a wide range of load
conditions. The low-noise mode sets the minimum
switching frequency to 33kHz for audio-sensitive
applications.
The LDO linear regulator can sink and source up
to 2Apk. Two fixed current limits (±1A-±2A) can be
chosen.
An active Soft-End is independently performed on
both the switching and the linear regulators
outputs when disabled.
Order codes
Part number
Package
Packaging
PM6675
VFQFPN-24 4x4 (Exposed Pad)
Tube
January 2007
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/47
www.st.com
47
Contents
PM6675
Contents
1
Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
2.1
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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Switching section - constant on-time PWM controller . . . . . . . . . . . . . . . 15
6.1.1
Constant-On-Time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.2
Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . 18
6.1.3
Pulse-Skip and No-Audible Pulse-Skip Modes . . . . . . . . . . . . . . . . . . . 22
6.1.4
Mode-of-operation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.5
Current sensing and current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.6
POR, UVLO and Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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6.1.9
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6.2
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Switching section Power-Good signal . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Switching section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.10
Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.11
Switching section OV and UV protections . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.12
Device thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LDO Linear Regulator section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.1
LDO Section current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2.2
LDO Section Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2.3
LDO Section Power-Good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2.4
LDO Section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PM6675
7
Contents
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1
External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.1
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1.2
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.3
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1.4
MOSFETs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1.5
Diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1.6
VDDQ current limit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.1.7
All ceramic capacitors application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Typical application circuit
PM6675
1
Typical application circuit
Figure 1.
Application circuit
+5V
R LP
VBATT
C IN3
C IN2
R1
C IN
R2
23
8
VCC
18
22
VOSC
C IN4
6
AVCC
10 VSEL
NOSKIP
VLDOIN
12
LILIM
3
B
O
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T
PHASE
LIN
24
VLDO
PM6675
LOUT
CSNS
2 LFB
5
15
14
13
VREF
COMP
SWEN
LEN
SPG
LGND
PGND
SGND
1
L
20
VSMPS
LGATE 17
4 LPG
LDO PG
C BOOT
7
VSNS
16
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R LIM
9
11
C OUT2
SMPS PG
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C OUT
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C BYP
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C INT
PM6675
Pin settings
2
Pin settings
2.1
Connections
CSNS
PHASE
HGATE
BOOT
LIN
Pin connection (through top view)
LOUT
Figure 2.
19
24
1
18
LGND
VCC
LFB
LGATE
NOSKIP
PGND
PM6675
LPG
SPG
SGND
LEN
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SWEN
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LILIM
VSEL
VSNS
VOSC
VREF
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COMP
12
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13
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Pin settings
2.2
PM6675
Pin description
Table 1. Pin functions
N°
Pin
1
LGND
2
LFB
3
NOSKIP
4
LPG
5
SGND
Ground Reference for analog circuitry, control logic and VTTREF buffer.
Connect together with the thermal pad and VTTGND to a low impedance
ground plane. See the Application Note for details.
6
AVCC
+5V supply for internal logic. Connect to +5V rail through a simple RC
filtering network.
7
VREF
High accuracy output voltage reference (1.237V) for multilevel pins setting. It
can deliver up to 50µA. Connect a 100nF capacitor between VREF and
SGND in order to enhance noise rejection.
8
VOSC
Frequency Selection. Connect to the central tap of a resistor divider to set
the desired switching frequency. The pin cannot be left floating. See
Section 6: Device description on page 14 for details.
9
VSNS
Switching section output remote sensing and discharge path during output
Soft-End. Connect as close as possible to the load via a low noise PCB
trace.
10
VSEL
Fixed output selector and feedback input for the switching controller.
If VSEL pin voltage is higher than 4V, the fixed 1.5V output is selected. If
VSEL pin voltage is lower than 4V, it is used as negative input of the error
amplifier. See Section 6.1.4: Mode-of-operation selection on page 24 for
details.
11
COMP
DC voltage error compensation input pin for the switching section. Refer to
Section 6.1.4: Mode-of-operation selection on page 24 for more details.
12
LILIM
Current limit selector for the LDO. Connect to SGND for ±1A current limit or
to +5V for ±2A current limit.
13
SWEN
Switching Controller Enable. When tied to ground, the switching output is
turned off and a Soft-End is performed.
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14
LEN
Linear Regulator Enable. When tied to ground, the LDO output is turned off
and a Soft-End is performed.
15
SPG
Switching Section Power-Good signal (open drain output). High when the
switching regulator output voltage is within ±10% of nominal value.
16
PGND
Power ground for the switching section.
17
LGATE
Low-side gate driver output.
18
VCC
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LDO power ground. Connect to the negative terminal of VTT output
capacitor.
LDO remote sensing. Connect as close as possible to the load via a low
noise PCB trace.
Pulse-Skip/No-Audible Pulse-Skip Modes selector.
See Section 6.1.4: Mode-of-operation selection on page 24
LDO section Power-Good signal (open drain output). High when LDO output
voltage is within ±10% of nominal value.
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Function
+5V low-side gate driver supply. Bypass with a 100nF capacitor to PGND.
PM6675
Pin settings
Table 1. Pin functions (continued)
N°
Pin
Function
19
CSNS
Current sense input for the switching section. This pin must be connected
through a resistor to the drain of the synchronous rectifier (RDS(ON) sensing)
to set the current limit threshold.
20
PHASE
Switch node connection and return path for the high side gate driver.
21
HGATE
High-Side Gate Driver Output
22
BOOT
Bootstrap capacitor connection. Input for the supply voltage of the high-side
gate driver.
23
LIN
24
LOUT
Linear Regulator Input. Bypass to LGND by a 10µF ceramic capacitor for
noise rejection enhancement.
LDO linear regulator output. Bypass with a 20ìF (2 x 10µF MLCC) filter
capacitor.
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Electrical data
PM6675
3
Electrical data
3.1
Maximum rating
Table 2. Absolute maximum ratings (1)
Symbol
Parameter
Value
VAVCC
AVCC to SGND
-0.3 to 6
VVCC
VCC to SGND
-0.3 to 6
PGND, LGND to SGND
VPHASE
Unit
-0.3 to 0.3
HGATE and BOOT to PHASE
-0.3 to 6
HGATE and BOOT to PGND
-0.3 to 42
PHASE to SGND
-0.3 to 36
LGATE to PGND
-0.3 to VCC +0.3
V
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CSNS, SPG, LEN, SWEN, LILIM, COMP, VSEL,
VSNS, VOSC, VREF, NOSKIP to SGND
-0.3 to VAVCC + 0.3
LPG,VREF, LOUT, LFB to SGND
-0.3 to VAVCC + 0.3
LIN, LOUT, LPG, LIN to LGND
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-0.3 to VAVCC + 0.3
Maximum withstanding Voltage range test
condition: CDF-AEC-Q100-002- “Human Body
Model” acceptance criteria: “Normal
Performance”
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1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under "absolute
maximum ratings" may cause permanent damage to the device. Exposure to absolute maximum rated
conditions for extended periods may affect device reliability.
3.2
Table 3. Thermal data
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Symbol
Value
Unit
42
°C/W
Storage temperature range
-40 to 150
°C
TA
Operating ambient temperature range
-40 to 85
°C
TJ
Junction operating temperature range
0 to 125
°C
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Thermal data
TSTG
Parameter
Thermal resistance junction to ambient
PM6675
4
Electrical characteristics
Electrical characteristics
VIN = 12V; TA = 0°C to 85°C, VCC = AVCC = +5V, LIN = 1.5V and LOUT = 0.9V
(if not otherwise specified)
Table 4. Electrical characteristics
Values
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
Supply section
VIN
Input voltage range
4.5
28
VAVCC
IC supply voltage
4.5
5.5
VVCC
IC supply voltage
4.5
5.5
IIN
Operating current
(Switching + LDO)
ISW
SWEN, VSEL and NOSKIP
Operating current (Switching) connected to AVCC, LEN
connected to SGND.
ISHDN
SWEN, LEN, VSEL and
NOSKIP connected to AVCC,
No load on LOUT output.
Shutdown operating current
so
UVLO hysteresis
tON
uc
On-time duration
(t s)
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AVCC under voltage lockout
upper threshold
ON-time (SMPS)
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SWEN and LEN tied to SGND.
AVCC under voltage lockout
upper threshold
UVLO
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VSELhigh,
and
NOSKIP low,
VVSNS = 2V
VOSC=300mV
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4.25
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10
mA
µA
4.4
V
3.9
4.0
4.1
70
mV
550
630
710
330
380
430
300
350
ns
1.237
1.249
V
ns
VOSC=500mV
OFF-time (SMPS)
tOFFMIN
Minimum OFF-time
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Voltage reference
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Voltage accuracy
4.5V< VIN < 25V
Load regulation
-50µA< IVREF < 50µA
1.224
-4
4
mV
Undervoltage Lockout Fault
Threshold
800
SMPS output
VOUT
SMPS fixed output voltage (1) VSEL connected to AVCC,
NOSKIP tied to SGND, No Load
Output voltage accuracy (1)
1.5
-1.5
V
1.5
%
1. Guaranteed by design. Not production tested
9/47
Electrical characteristics
PM6675
Table 4. Electrical characteristics (continued)
Values
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
CSNS input bias current
90
100
110
Comparator offset
-5
Current limit and zero crossing comparator
ICSNS
VZC,OFFS
µA
5
Positive current limit threshold VPGND - VCSNS
-115
-100
-85
Fixed negative current limit
threshold
-130
-110
-90
Zero crossing comparator
offset
-10
-5
0
HGATE high state (pull-up)
2.0
3
HGATE low state (pull-down)
1.8
2.7
LGATE high state (pull-up)
1.4
2.1
LGATE low state (pull-down)
0.6
0.9
mV
High and low side gate drivers
HGATE driver on-resistance
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LGATE driver on-resistance
UVP/OVP protections and PGOOD signals
OVP
Over voltage threshold
UVP
Under voltage threshold
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SMPS upper threshold
SMPS lower threshold
PGOOD
LDO upper threshold
LDO lower threshold
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IPG,LEAK
SPG and LPG Leakage
Current¹
VPG,LOW
SPG and LPG Low Level
Voltage
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Soft start section (SMPS)
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Soft-start ramp time
(4 steps current limit)
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Soft-start current limit step
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112
115
118
67
70
73
107
110
113
87
90
93
107
110
113
87
90
93
Ω
%
1
µA
150
250
mV
3
4
ms
SPG and LPG forced to 5.5V
ILPG,SINK = ISPG,SINK = 4mA
2
25
µA
PM6675
Electrical characteristics
Table 4. Electrical characteristics (continued)
Values
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
Switching section discharge
resistance
15
25
35
LDO section discharge
resistance
15
25
35
VLREF
LDO reference voltage
0.594
0.6
0.606
VDROP
LDO drop-out voltage
VLOUT = 0.9V, ILOUT = 1A,
-10% output drop
0.25
LDO Internal high-side
MOSFET RDS(ON)
ILOUT = 1A, AVCC=5V
0.2
0.23
-2.8
Soft end section
Ω
LDO section
LDO sink current limit
-2
-2.3
VLFB > VLREF, LILIM = 0V
-1
-1.15
0.9 • VLREF < VLFB < VLREF,
LILIM = 5V
2.8
0.9 • VLREF < VLFB < VLREF,
LILIM = 0V
1.4
1.15
1
VLFB < 0.9 • VLREF, LILIM = 5V
1.4
1.15
1
VLFB < 0.9 • VLREF, LILIM = 0V
0.7
0.55
0.5
1
10
LDO source current limit
so
LDO input bias current, ON
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LFB input bias current
ILFB,LEAK
LFB leakage current
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LEN connected to AVCC, no
load
(t s)
LDO input bias current, OFF
ILFB,BIAS
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LEN = 0V, no load
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Ω
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VLFB > VLREF , LILIM = 5V
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ILDO,CL
ILIN,BIAS
V
-1.4
2
A
1
LEN connected to AVCC
VLFB = 0.6V
-1
1
LEN = 0V, VLFB = 0.6V
-1
1
µA
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Electrical characteristics
PM6675
Table 4. Electrical characteristics (continued)
Values
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
Power management section
VAVCC
-0.7
Fixed mode
VVTHVSEL
VSEL pin thresholds
VAVCC
-1.3
Adjustable mode
VAVCC
-0.8
Forced-PWM mode
VVTHNOSKIP
NOSKIP pin thresholds¹
No-audible mode
VAVCC
-1.5
1.0
Pulse-skip mode
0.5
VAVCC
-0.8
±2A LDO current limit
VVTHLILIM
LILIM pin thresholds¹
±1A LDO current limit
Logic input leakage current (1) LEN, SWEN and LILIM = 5V
IIN3,LEAK
Multilevel input leakage
current (1)
VSEL and NOSKIP = 5V
IOSC,LEAK
VOSC pin leakage current (1)
VOSC = 1V
TSHDN
Shutdown temperature¹
1. Guaranteed by design. Not production tested
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0.5
IIN,LEAK
Thermal shutdown
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150
10
µA
1
°C
PM6675
Block diagram
5
Block diagram
Figure 3.
Functional and block diagram
VREF
VOSC
Vr = 0.6V
1.236V
Bandgap
BOOT
LFB
Level
shifter
Ton
HGATE
1-shot
LIN
PHASE
Ton
min
1-shot
_
LOUT
Anti Cross
Conduction
VCC
Toff
min
1-shot
LILIM
LGATE
+
PGND
LDS
c
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LEN
0.6V
Zero Crossing
& Current
Limit
LGND
_
Vr +10%
VREF
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+
LPG
+
SWEN
+
-
SGND
AVCC
UVP/OVP
UVLO
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LILIM
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NOSKIP
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(s)
ct
du
SWEN
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-
+
-
Vr
SPG
Vr
LDS
LDS
Vr -10%
LEN
VSNS
SDS
Thermal Shutdown
SWEN
COMP
+
-
CONTROL LOGIC
LEN
CSNS
Vr +10%
_
gm
+
Vr -10%
o
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P
)
s
t(
adj
fix
VSEL
Table 5. Legend
SWEN
Switching controller enable
LEN
LDO regulator enable
LDS
LDO output discharge enable
SDS
Switching output discharge enable
LILIM
LDO regulator current limit
13/47
Device description
6
PM6675
Device description
The PM6675 combines a single high efficiency step-down controller and an independent
Low Drop-Out (LDO) linear regulator in the same package.
The switching controller section is a high-performance, pseudo-fixed frequency, ConstantOn-Time (COT) based regulator specifically designed for handling fast load transient over a
wide range of input voltages.
The switching section output can be easily set to a fixed 1.5V voltage without additional
components or adjusted in the 0.6V to 3.3V range using an external resistor divider. The
Switching Mode Power Supply (SMPS) can handle different modes of operation in order to
minimize noise or power consumption, depending on the application needs. Selectable lowconsumption and low-noise modes allow the highest efficiency and a 33kHz minimum
switching frequency respectively at light loads.
A loss less current sensing scheme, based on the Low-Side MOSFET's turn-on resistance,
avoids the need for an external sensing resistor.
)
s
t(
The input of the LDO can be either the switching section output or a lower voltage rail in
order to reduce the total power dissipation. Linear regulator stability is achieved by filtering
its output with a ceramic capacitor (20µF or greater). The LDO linear regulator can sink and
source up to 2Apk.
Two fixed current limit (±1A-±2A) can be chosen.
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An active Soft-End is independently performed on both the switching and the linear
regulators outputs when disabled.
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14/47
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-
PM6675
6.1
Device description
Switching section - constant on-time PWM controller
The PM6675 employees a pseudo-fixed frequency, Constant On-Time (COT) controller as
the core of the switching section. It is well known that the COT controller uses a relatively
simple algorithm and uses the ripple voltage derived across the output capacitor's ESR to
trigger the On-Time one-shot generator. In this way, the output capacitor's ESR acts as a
current sense resistor providing the appropriate ramp signal to the PWM comparator.
Nearly constant switching frequency is achieved by the system's loop in steady-state
operating conditions by varying the On-Time duration, avoiding thus the need for a clock
generator. The On-Time one shot duration is directly proportional to the output voltage,
detected by theVSNS pin, and inversely proportional to the input voltage, detected by the
the VOSC pin, as follows:
Equation 1
TON = K OSC
VSNS
+τ
VOSC
)
s
t(
where KOSC is a constant value (130ns typ.) and τ is the internal propagation delay
(40ns typ.). The one-shot generator directly drives the high-side MOSFET at the beginning
of each switching cycle allowing the inductor current to increase; after the On-Time has
expired, an Off-Time phase, in which the low-side MOSFET is turned on, follows. The OffTime duration is solely determined by the output voltage: when lower than the set value (i.e.
the voltage at VSNS pin is lower than the internal reference VR = 0.6V), the synchronous
rectifier is turned off and a new cycle begins (Figure 4).
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Figure 4.
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Inductor current and output voltage in steady state conditions
Inductor
current
)
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Output
voltage
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bs
Vreg
Ton
Toff
t
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15/47
Device description
PM6675
The duty-cycle of the buck converter is, in steady-state conditions, given by
Equation 2
V OUT
D = -------------V IN
The switching frequency is thus calculated as
Equation 3
fSW
VOUT
α
VIN
D
1
=
=
= OSC ⋅
VSNS
TON
α OUT K OSC
K OSC
VOSC
where
Equation 4a
V OSC
α OSC = -------------V IN
Equation 4b
V SNS
α OUT = -------------V OUT
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Referring to the typical application schematic (figures on cover page and Figure 5), the final
expression is then:
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Equation 5
fSW =
)
s
(
ct
α OSC
R2
1
=
⋅
K OSC R1 + R 2 K OSC
Even if the switching frequency is theoretically independent from battery and output
voltages, parasitic parameters involved in the power path (like MOSFETs' on-resistance and
inductor's DCR) introduce voltage drops responsible for a slight dependence on load
current. In addition, the internal delay is due to a small dependence on input voltage.
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The PM6675 switching frequency can be set by an external divider connected to the VOSC
pin.
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Figure 5.
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O
Switching frequency selection and VOSC pin
VIN
PM6675
R1
VOSC
R2
The voltage seen at this pin must be greater than 0.8V and lower than 2V in order to ensure
the system's linearity.
16/47
PM6675
6.1.1
Device description
Constant-On-Time architecture
Figure 6 shows the simplified block diagram of the Constant-On-Time controller.
The switching regulator of the PM6675 controls a one-shot generator that initiates the highside MOSFET when the following conditions are simultaneously satisfied: the PWM
comparator is high (i.e. output voltage is lower than Vr = 0.6V), the synchronous rectifier
current is below the current limit threshold and the minimum off-time has expired.
A minimum Off-Time contraint (300ns typ.) is introduced to assure the boot capacitor charge
and allow inductor valley current sensing on low-side MOSFET. A minimum On-Time is also
introduced to assure the start-up switching sequence.
Once the On-Time has timed out, the high side switch is turned off, while the synchronous
rectifier is ignited according to the anti-cross conduction management circuitry.
When the output voltage reaches the valley limit (determined by internal reference
Vr = 0.6V), the low-side MOSFET is turned off according to the anti-cross conduction logic
once again, and a new cycle begins.
Figure 6.
Switching section simplified block diagram
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VOSC
VOSC
Positive Current Limit comparator
CSNS
ToffToff-min
+
Level
shifter
1-Shot generator
+
VBG
PWM Comparator
-
+
(s)
0.6V
ct
VSEL k ⋅ fZout =
k
2π ⋅ C out ⋅ ESR
where k is a fixed design parameter (k > 3). It determinates the minimum integrator
capacitor value:
Equation 7
CINT >
gm
Vr
⋅
⎛ fSW
⎞ Vout
2π ⋅ ⎜
− fZout ⎟
⎝ k
⎠
c
u
d
where gm = 50µs is the integrator trans conductance.
)
s
t(
If the ripple on the COMP pin is greater than the integrator 150mV, the auxiliary capacitor
CFILT can be added. If q is the desired attenuation factor of the output ripple, CFILT is given
by:
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Equation 8
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CFILT =
CINT ⋅ (1 − q)
q
In order to reduce the noise on the COMP pin, it is possible to add a resistor RINT that,
together with CINT and CFILT, becomes a low pass filter. The cutoff frequency fCUT must be
much greater (10 or more times) than the switching frequency:
Equation 9
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)
s
(
ct
RINT =
2π ⋅ fCUT
1
CINT ⋅ CFILT
⋅
CINT + CFILT
If the ripple is very small (lower than approximately 20mV), a different compensation
network, called "Virtual-ESR" Network, is needed. This additional circuit generates a
triangular ripple that is added to the output voltage ripple at the input of the integrator. The
complete control scheme is shown in Figure 8.
19/47
Device description
PM6675
Figure 8.
"Virtual-ESR" network
COMP PIN
VOLTAGE
T NODE
VOLTAGE
∆V2
VREF
∆V1
t
VREF
t
+
I=gm(V1-Vr)
COMP
-
PWM
Comparator
RINT CINT
CFILT
gm
R1
Vr
C
R
VSNS
OUTPUT
VOLTAGE
∆V
+
-
T
RFb1
V1
RFb2
ESR
COUT
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t
)
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The ripple on the COMP pin is the sum of the output voltage ripple and the triangular ripple
generated by the Virtual-ESR Network. In fact the Virtual-ESR Network behaves like a
another equivalent series resistor RVESR.
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A good trade-off is to design the network in order to achieve an RVESR given by:
Equation 10
)
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-
R VESR =
VRIPPLE
− ESR
∆IL
where ∆IL is the inductor current ripple and VRIPPLE is the total ripple at the T node, chosen
greater than approximately 20mV.
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The new closed-loop gain depends on CINT. In order to ensure stability it must be verified
that:
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Equation 11
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CINT >
gm
Vr
⋅
2π ⋅ fZ Vout
where:
Equation 12
fZ =
and:
20/47
1
2π ⋅ C out ⋅ R TOT
PM6675
Device description
Equation 13
RTOT = ESR + RVESR
Moreover, the CINT capacitor must meet the following condition:
Equation 14
fSW > k ⋅ fZ =
k
2π ⋅ C out ⋅ R TOT
where RTOT is the sum of the ESR of the output capacitor and the equivalent ESR given by
the Virtual-ESR Network (RVESR). The k parameter must be greater than unity (k > 3) and
determines the minimum integrator capacitor value CINT:
Equation 15
CINT >
gm
Vr
⋅
⎛ fSW
⎞ Vout
2π ⋅ ⎜
− fZ ⎟
⎝ k
⎠
The capacitor of the Virtual-ESR Network, C, is chosen as follow
Equation 16
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C > 5 ⋅ CINT
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and R is calculated to provide the desired triangular ripple voltage:
Equation 17
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(t s)
R=
L
R VESR ⋅ C
Finally the R1 resistor is calculated according to expression 18:
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Equation 18
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⎛
1 ⎞
⎟⎟
R ⋅ ⎜⎜
f
π
⋅
Z ⋅C⎠
⎝
R1 =
1
R−
π ⋅ fZ ⋅ C
21/47
Device description
6.1.3
PM6675
Pulse-Skip and No-Audible Pulse-Skip Modes
High efficiency at light load conditions is achieved by PM6675 entering the Pulse-Skip Mode
(if enabled). When one of the two fixed output voltages is set, Pulse-Skip power saving is a
default feature. At light load conditions the zero-crossing comparator truncates the low-side
switch on-time as soon as the inductor current becomes negative; in this way the
comparator determines the On-Time duration instead of the output ripple (see Figure 9).
Figure 9.
Inductor current and output voltage at light load with Pulse-Skip
Inductor
current
Output
voltage
Vreg
TON TOFF
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TIDLE
)
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As a consequence, the output capacitor is left floating and its discharge depends solely on
the current drained from the load. When the output ripple on the pin COMP falls under the
reference, a new shot is triggered and the next cycle begins. The Pulse-Skip mode is
naturally obtained enabling the zero-crossing comparator and automatically takes part in the
C.O.T. algorithm when the inductor current is about half the ripple current amount, i.e.
migrating from continuous conduction mode (C.C.M.) to discontinuous conduction mode
(D.C.M.).
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The output current threshold related to the transition between PWM Mode and Pulse-Skip
Mode can be approximately calculated as:
Equation 19
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P
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)
s
(
ct
ILOAD (PWM2Skip) =
VIN − VOUT
⋅ TON
2 ⋅L
At higher loads, the inductor current never crosses the zero and the device works in pure
PWM mode with a switching frequency around the nominal value.
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22/47
A physiological consequence of Pulse-Skip Mode is a more noisy and asynchronous (than
normal conditions) output, mainly due to very low load. If the Pulse-Skip is not compatible
with the application, the PM6675, when set in adjustable mode-of-operation, allows the user
to choose between forced-PWM and No-Audible Pulse-Skip alternative modes (see
Section 6.1.4: Mode-of-operation selection on page 24 for details).
PM6675
Device description
No-Audible Pulse-Skip Mode
Some audio-noise sensitive applications cannot accept the switching frequency to enter the
audible range as it is possible in Pulse-Skip mode with very light loads. For this reason, the
PM6675 implements an additional feature to maintain a minimum switching frequency of
33kHz despite a slight efficiency loss. At very light load conditions, if any switching cycle has
taken place within 30µs (typ.) since the last one (because of the output voltage is still higher
than the reference), a No-Audible Pulse-Skip cycle begins. The low-side MOSFET is turned
on and the output is driven to fall until the reference point has been crossed. Then, the highside switch is turned on for a TON period and, once it has expired, the synchronous rectifier
is enabled until the inductor current reaches the zero-crossing threshold (see Figure 10).
Figure 10.
Inductor current and output voltage at light load with non-audible pulse-skip
Inductor
current
Output
voltage
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Vreg
TMAX
TON TOFF
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TIDLE
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-
For frequencies higher than 33kHz (due to heavier loads) the device works in the same way
as in Pulse-Skip mode. It is important to notice that in both Pulse-Skip and No-Audible
Pulse-Skip modes, the switching frequency changes not only with the load but also with the
input voltage.
)
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23/47
Device description
6.1.4
PM6675
Mode-of-operation selection
Figure 11. VSEL and NOSKIP multifunction pin configurations
VOUT
+5V
R9
PM6675
R8
VSEL
VREF
NOSKIP
)
s
t(
The PM6675 has been designed to satisfy the widest range of applications. The device is
provided with some multilevel pins which allow the user to choose the appropriate
configuration. The VSEL pin is used to firstly decide between fixed preset or adjustable
(user defined) output voltages.
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When the VSEL pin is connected to +5V, the PM6675 sets the switching section output
voltage to 1.5V without the need of an external divider.
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Applications requiring different output voltages can be managed by PM6675 simply setting
the adjustable mode. Consider that if the VSEL pin voltage is higher than 4V, the fixed
output mode is selected. When connecting an external divider to the VSEL pin, it is used as
negative input of the error amplifier and the output voltage is given by expression (20).
Equation 20
(s)
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-
VOUTADJ = 0.6 ⋅
R8 + R9
R8
The output voltage can be set in the range from 0.6V to 3.3V.
The NOSKIP is the power saving algorithm selector: if tied to +5V, the forced-PWM (fixed
frequency) control is performed. If grounded or connected to VREF pin (1.237V reference
voltage), the Pulse-Skip or Non-Audible Pulse-Skip Modes are respectively selected.
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24/47
PM6675
Device description
Table 6. Mode-of-operation settings summary
VSEL
NOSKIP
VOUT
VNOSKIP > 4.2V
VVSEL > 4.3V
VVSEL < 3.7V
Forced-PWM
1V 4.2V
Forced-PWM
1V 1V).
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The soft-start allows a gradual increase of the internal current limit threshold during startup
reducing the input/output surge currents. At the beginning of start-up, the PM6675 current
limit is set to 25% of nominal value and the Under Voltage Protection is disabled. Then, the
current limit threshold is sequentially brought to 100% in four steps of approximately 750µs
(Figure 13).
Figure 13. Soft-start waveforms
Switching output
)
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26/47
Current limit threshold
SWEN
Time
After a fixed 3ms total time, the soft-start finishes and UVP is released: if the output voltage
doesn't reach the Power-Good lower threshold within soft-start duration, the UVP condition
is detected and the device performs a soft end and latches off. Depending on the load
conditions, the inductor current may or may not reach the nominal value of the current limit
during the soft-start (Figure 14 shows two examples).
PM6675
Device description
Figure 14. Soft-start at heavy load (a) and short-circuit (b) conditions, Pulse-Skip enabled
(a)
6.1.7
(b)
Switching section Power-Good signal
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)
s
t(
The SPG pin is an open drain output used to monitor output voltage through VSNS (in fixed
output voltage mode) or VSEL (in adjustable output voltage mode) pins and is enabled after
the soft-start timer has expired. The SPG signal is held low if the output voltage drops 10%
below or rises 10% above the nominal regulated value. The SPG output can sink current up
to 4mA.
6.1.8
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Switching section output discharge
Active soft-end of the output occurs when the SWEN (SWitching ENable) is forced low.
When the switching section is turned off, an internal 25Ω resistor discharges the output
through the VSNS pin.
)
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Figure 15. Switching section Soft-End
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VOUT
Resistive Discharge
SWEN
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27/47
Device description
6.1.9
PM6675
Gate drivers
The integrated high-current gate drivers allow using different power MOSFETs. The highside driver uses a bootstrap circuit which is supplied by the +5V rail. The BOOT and PHASE
pins work respectively as supply and return path for the high-side driver, while the low-side
driver is directly fed through VCC and PGND pins.
An important feature of the PM6675 gate drivers is the Adaptive Anti-Cross-Conduction
circuitry, which prevents high-side and low-side MOSFETs from being turned on at the same
time. When the high-side MOSFET is turned off, the voltage at the PHASE node begins to
fall. The low-side MOSFET is turned on only when the voltage at the PHASE node reaches
an internal threshold (2.5V typ.). Similarly, when the low-side MOSFET is turned off, the
high-side one remains off until the LGATE pin voltage is above 1V.
The power dissipation of the drivers is a function of the total gate charge of the external
power MOSFETs and the switching frequency, as shown in the following equation:
Equation 22
PD (driver ) = VDRV ⋅ Q g ⋅ fSW
)
s
t(
The low-side driver has been designed to have a low-resistance pull-down transistor
(0.6Ω typ.) in order to prevent undesired start-up of the low-side MOSFET due to the Miller
effect.
6.1.10
c
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Reference voltage and bandgap
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The 1.237V internal bandgap reference has a granted accuracy of ±1% over the 0°C to
85°C temperature range. The VREF pin is a buffered replica of the bandgap voltage. It can
supply up to ±100µA and is suitable to set the intermediate level of NOSKIP multifunction
pin. A 100nF (min.) bypass capacitor toward SGND is required to enhance noise rejection. If
VREF falls below 0.87V (typ.), the system detects a fault condition and all the circuitry is
turned off.
)
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-
An internal divider derives a 0.6V±1% voltage (Vr) from the bandgap. This voltage is used
as reference for both the switching and the linear sections. The Over-Voltage Protection, the
Under-Voltage Protection and the Power-Good signals are also referred to Vr.
6.1.11
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Switching section OV and UV protections
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P
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When the switching output voltage is about 115% of its nominal value, a latched OverVoltage Protection (OVP) occurs. In this case the synchronous rectifier immediately turns on
while the high-side MOSFET turns off. The output capacitor is rapidly discharged and the
load is preserved from being damaged. The OVP is also active during the soft start. Once
an OVP has taken part, a toggle on SWEN pin or a Power-On-Reset is necessary to exit
from the latched state.
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When the switching output voltage is below 70% of its nominal value, a latched UnderVoltage Protection occurs. This event causes the switching section to be immediately
disabled and both switches to be opened. The controller performs a Soft-End and the output
is eventually kept to ground, turning the low side MOSFET on when the voltage is lower than
400mV.
The Under-Voltage Protection circuit is enabled only at the end of the soft-start. Once an
UVP has taken part, a toggle on SWEN pin or a Power-On-Reset is necessary to clear the
fault state and restart the section.
28/47
PM6675
6.1.12
Device description
Device thermal protection
The internal control circuitry of the PM6675 self-monitors the junction temperature and turns
all outputs off when the 150°C limit has been overrun. This event causes the switching
section to be immediately disabled and both switches to be opened. The controller performs
a Soft-End and both the outputs are eventually kept to ground, then the low side MOSFET is
turned on when the voltage of the switching section is lower than 400mV.
The thermal fault is a latched protection and, in normal operating conditions it is restored by
a Power-On Reset or toggling SWEN and LEN pins at the same time.
Table 7. Switching Section OV, UV and OT Faults management
Fault
Conditions
Over voltage
VOUT > 115% of the LGATE pin is forced high and the device latches off.
nominal value
Exit by a Power-On Reset or toggling SWEN
Under voltage
VOUT < 70% of the
nominal value
LGATE pin is forced high after the Soft-End, then the
device latches off. Exit by a Power-On Reset or
toggling SWEN.
TJ > +150°C
LGATE pin is forced high after the Soft-End, then the
device latches off. Exit by a Power-On Reset or
toggling SWEN and LEN after 15°C temperature
drop.
Junction over
temperature
6.2
Action
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LDO Linear Regulator section
)
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The independent Low-Drop-Out (LDO) linear regulator has been designed to sink and
source up to 2A peak current and 1A continuously. The LDO output voltage can be adjusted
in the range 0.6V to 3.3V simply connecting a resistor divider as shown in Figure 16.
Equation 23
)
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-
VLDO ADJ = 0.6 ⋅
u
d
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R19 + R20
R20
Figure 16. LDO output voltage selection
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PM6675
VLOUT
LOUT
Cc
COUT
R19
LFB
R20
LGND
29/47
Device description
PM6675
A compensation capacitor Cc must be added to adjust the dynamic response of the loop.
The value of Cc is calculated according to the desired bandwidth of the LDO regulator and
depends on the value of the feedback resistors. In most of applications the pole due to the
compensation capacitor is placed at 100-200kHz (equation 24).
Equation 24
fp =
1
= 200kHz
2π(R19 ⊕ R20) ⋅ C C
The LIN input can be connected to the switching section output for compact solutions or to a
lower supply, if available in the system, in order to reduce the power dissipation of the LDO.
A minimum output capacitance of 20µF (2x10µF MLCC capacitors) is enough to assure
stability and fast load transient response.
6.2.1
LDO Section current limit
)
s
t(
The LDO regulator can handle up to ±2Apk, depending on the LDO input voltage and the
LILIM pin setting. The output current is limited to ±1A or ±2A if the LILIM pin is connected to
SGND or AVCC respectively (Figure 17).
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Figure 17. LDO current limit setting
+5V
±2A CL
±1A CL
)
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ct
PM6675
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LILIM
The maximum current that the LDO can source depends also on the input and output
voltages. Due to the high side MOSFET of the output stage, the LDO cannot source the limit
current at high output voltages. In Figure 18 it is shown the maximum current that the LDO
can source as function of the input and output voltages. For output voltages higher than 2V,
the maximum output current is limited as reported.
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30/47
PM6675
Device description
Figure 18. Maximum LDO source able output current vs input voltage
2.2
ILOUT [A]
2.0
VOUT=1.05V
1.8
VOUT=1.2V
1.6
VOUT=1.5V
VOUT=1.8V
1.4
VOUT=2.0V
1.2
VOUT=2.2V
VOUT=2.5V
1.0
VOUT=3.3V
0.8
0.6
0.4
0.2
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VLIN [V]
6.2.2
c
u
d
LDO Section Soft-Start
5.0
)
s
t(
o
r
P
The LDO section Soft-Start is performed by clamping the current limit. During startup, the
LDO current limit voltage is set to 1A and the output voltage increases linearly. When the
output voltage rises above 90% of the nominal value, the current limit is released to 2A
according to the LILIM pin setting. At the end of the ramp-up phase of the Soft-Start, the
LPG signal is masked for about 100µs in order to ignore dynamic overshoot on the feedback
pin.
e
t
le
6.2.3
o
s
b
O
-
LDO Section Power-Good signal
)
s
(
ct
The LPG pin is an open drain output used to monitor the LDO output voltage through LFB
pin.
The LPG signal is held low if the output voltage drops 10% below or rises 10% above the
nominal regulated value. The LPG output can sink current up to 4mA.
6.2.4
u
d
o
r
P
e
LDO Section output discharge
s
b
O
t
e
l
o
Active soft-end of the LDO output occurs when the LEN (Linear ENable) is forced low. When
the LDO section is turned off, an internal 25Ω resistor, directly connected to the LOUT pin,
discharges the output.
Figure 19. LDO section Soft-End
VLDO
Resistive Discharge
LEN
31/47
Application information
7
PM6675
Application information
The purpose of this chapter is showing the design procedure of the switching section.
The design starts from three main specifications:
●
The input voltage range, provided by the battery or the external supply. The two
extreme values (VINMAX and VINmin ) are important for the design.
●
The maximum load current, indicated with ILOAD,MAX.
●
The maximum allowed output voltage ripple VRIPPLE,MAX.
It's also possible that specific designs should involve other specifications.
The following paragraphs will guide the user into a step-by-step design.
7.1
External components selection
)
s
t(
The PM6675 uses a pseudo-fixed frequency, Constant On-Time (COT) controller as the
core of the switching section. The switching frequency can be set by connecting an external
divider to the VOSC pin. The voltage seen at this pin must be greater than 0.8V and lower
than 2V in order to ensure system's linearity.
c
u
d
o
r
P
Nearly constant switching frequency is achieved by the system's loop in steady-state
operating conditions by varying the On-Time duration, avoiding thus the need for a clock
generator. The On-Time one shot duration is directly proportional to the output voltage,
sensed at VSNS pin, and inversely proportional to the input voltage, sensed at the VOSC
pin, as follows:
e
t
le
Equation 25
o
s
b
O
-
TON = K OSC
)
s
(
ct
VSNS
+τ
VOSC
where KOSC is a constant value (130ns typ.) and τ is the internal propagation delay
(40ns typ.).
u
d
o
The duty cycle of the buck converter is, in under steady state conditions, given by
r
P
e
Equation 26
t
e
l
o
s
b
O
D=
The switching frequency is thus calculated as
Equation 27
fSW
32/47
VOUT
VIN
VOUT
α
VIN
1
D
=
=
= OSC ⋅
VSNS
TON
α OUT K OSC
K OSC ⋅
VOSC
PM6675
Application information
where
Equation 28a
α OSC =
VOSC
VIN
α OUT =
VSNS
VOUT
Equation 28b
Referring to the typical application schematic (figure in cover page and Figure 5), the final
expression is then:
Equation 29
fSW =
α OSC
R2
1
=
⋅
K OSC R1 + R 2 K OSC
c
u
d
The switching frequency directly affects two parameters:
)
s
t(
o
r
P
●
Inductor size: greater frequencies mean smaller inductances. In notebook applications,
real estate solutions (i.e. low-profile power inductors) are mandatory also with high
saturation and r.m.s. currents.
●
Efficiency: switching losses are proportional to the frequency. Generally, higher
frequencies imply lower efficiency.
e
t
le
o
s
b
O
-
Even if the switching frequency is theoretically independent from battery and output
voltages, parasitic parameters involved in power path (like MOSFETs' on-resistance and
inductor's DCR) introduce voltage drops responsible for a slight dependence on load
current.
)
s
(
ct
In addition, the internal delay is cause of a light dependence from input voltage.
u
d
o
Table 8. Typical values for switching frequency selection
R1 (kΩ)
R2 (kΩ)
Approx switching frequency (kHz)
330
11
250
330
13
300
330
15
350
330
18
400
330
20
450
330
22
500
r
P
e
t
e
l
o
O
bs
33/47
Application information
7.1.1
PM6675
Inductor selection
Once the switching frequency has been defined, the inductance value depends on the
desired inductor ripple current. Low inductance value means great ripple current that brings
poor efficiency and great output noise. On the other hand a great current ripple is desirable
for fast transient response when a load step is applied.
High inductance brings to good efficiency but the transient response is critical, especially if
VINmin - VOUT is little. Moreover a minimum output ripple voltage is necessary to assure
system stability and jitter-free operations (see Section 7.1.3: Output capacitor selection on
page 36). The product of the output capacitor's ESR multiplied by the inductor ripple current
must be taken in consideration. A good trade-off between the transient response time, the
efficiency, the cost and the size is choosing the inductance value in order to maintain the
inductor ripple current between 20% and 50% (usually 40%) of the maximum output current.
The maximum inductor ripple current, ∆IL,MAX , occurs at the maximum input voltage.
Given these considerations, the inductance value can be calculated using the following
expression:
Equation 30
L=
c
u
d
VIN − VOUT VOUT
⋅
fsw ⋅ ∆IL
VIN
)
s
t(
o
r
P
where fSW is the switching frequency, VIN is the input voltage, VOUT is the output voltage and
∆IL is the inductor ripple current.
e
t
le
Once the inductor value is determined, the inductor ripple current is then recalculated:
Equation 31
o
s
b
O
-
∆IL,MAX =
)
s
(
ct
VIN,MAX − VOUT
fsw ⋅ L
⋅
VOUT
VIN,MAX
The next step is the calculation of the maximum r.m.s. inductor current:
u
d
o
Equation 32
r
P
e
IL,RMS = (ILOAD,MAX )2 +
t
e
l
o
s
b
O
(∆IL,MAX )2
12
The inductor must have an r.m.s. current greater than IL,RMS in order to assure thermal
stability.
Then the calculation of the maximum inductor peak current follows:
Equation 33
IL,PEAK = ILOAD,MAX +
∆IL,MAX
2
IL,PEAK is important when choosing the inductor, in term of its saturation current.
34/47
PM6675
Application information
The saturation current of the inductor should be greater than IL,PEAK as well as for case of
hard saturation core inductors. Using soft-ferrite cores is possible (but not advisable) to push
the inductor working near its saturation current.
In Table 9 some inductors suitable for notebook applications are listed.
Table 9. Evaluated inductors (@fsw = 400kHz)
Manufacturer
Series
Inductance (ìH)
+40°C RMS
current (A)
-30% saturation
current (A)
COILCRAFT
MLC1538-102
1
13.4
21.0
COILCRAFT
MLC1240-901
0.9
12.4
24.5
COILCRAFT
MVR1261C-112
1.1
20
20
WURTH
7443552100
1
16
20
COILTRONICS
HC8-1R2
1.2
16.0
25.4
In Pulse-Skip Mode, low inductance values produce a better efficiency versus load curve,
while higher values result in higher full-load efficiency because of the smaller current ripple.
7.1.2
c
u
d
Input capacitor selection
)
s
t(
o
r
P
In a buck topology converter the current that flows through the input capacitor is pulsed and
with zero average value. The RMS input current can be calculated as follows:
e
t
le
Equation 34
so
2
ICinRMS = ILOAD ⋅ D ⋅ (1 − D) +
b
O
-
1
D ⋅ (∆IL )2
12
Neglecting the second term, the equation 10 is reduced to:
)
s
(
ct
Equation 35
o
r
P
e
du
ICinRMS = ILOAD D ⋅ (1 − D)
The losses due to the input capacitor are thus maximized when the duty-cycle is 0.5:
t
e
l
o
Equation 36
s
b
O
Ploss = ESR Cin ⋅ ICinRMS (max)2 = ESR Cin ⋅ (0.5 ⋅ ILOAD (max))2
The input capacitor should be selected with a RMS rated current higher than ICINRMS(max).
Tantalum capacitors are good in terms of low ESR and small size, but they occasionally can
burn out if subjected to very high current during operation. Multi-Layers-Ceramic-Capacitors
(MLCC) have usually a higher RMS current rating with smaller size and they remain the best
choice. The drawback is their quite high cost.
35/47
Application information
PM6675
It must be taken into account that in some MLCC the capacitance decreases when the
operating voltage is near the rated voltage. In Table 10 some MLCC suitable for most of
applications are listed.
Table 10. Evaluated MLCC for input filtering
Manufacturer
7.1.3
Maximum Irms
@100kHz (A)
Capacitance (µF) Rated voltage (V)
Series
TAIYO YUDEN UMK325BJ106KM-T
10
50
2
TAIYO YUDEN
GMK316F106ZL-T
10
35
2.2
TAIYO YUDEN
GMK325F106ZH-T
10
35
2.2
TAIYO YUDEN
GMK325BJ106KN
10
35
2.5
TDK
C3225X5R1E106M
10
25
Output capacitor selection
)
s
t(
Using tantalum or electrolytic capacitors, the selection is made referring to ESR and voltage
rating rather than by a specific capacitance value.
c
u
d
The output capacitor has to satisfy the output voltage ripple requirements. At a given
switching frequency, small inductor values are useful to reduce the size of the choke but
increase the inductor current ripple. Thus, to reduce the output voltage ripple a low ESR
capacitor is required.
e
t
le
o
r
P
To reduce jitter noise between different switching regulators in the system, it is preferable to
work with an output voltage ripple greater than 25mV.
o
s
b
O
-
Concerning the load transient requirements, the Equivalent Series Resistance (ESR) of the
output capacitor must satisfy the following relationship:
Equation 37
ct
(s)
u
d
o
ESR ≤
VRIPPLE,MAX
∆IL,MAX
where VRIPPLE is the maximum tolerable ripple voltage.
r
P
e
In addition, the ESR must be high enough high to meet stability requirements. The output
capacitor zero must be lower than the switching frequency:
t
e
l
o
Equation 38
s
b
O
36/47
fSW > fZ =
1
2π ⋅ ESR ⋅ C out
PM6675
Application information
If ceramic capacitors are used, the output voltage ripple due to inductor current ripple is
negligible. Then the inductance should be smaller, reducing the size of the choke. In this
case it is important that output capacitor can adsorb the inductor energy without generating
an over-voltage condition when the system changes from a full load to a no load condition.
The minimum output capacitance can be chosen by the following equation:
Equation 39
COUT,min =
L ⋅ ILOAD,MAX
Vf 2 − Vi 2
where Vf is the output capacitor voltage after the load transient, while Vi is the output
capacitor voltage before the load transient.
In Table 11 are listed some tested polymer capacitors.
Table 11. Evaluated output capacitors
Series
Capacitance
(µF)
Rated voltage
(V)
4TPE220MF
220
4V
4TPE150MI
220
4V
4TPC220M
220
4V
TNCB OE227MTRYF
220
2.5V
Manufacturer
SANYO
HITACHI
7.1.4
MOSFETs selection
e
t
le
)
s
t(
ESR max @100kHz
(mΩ)
c
u
d
o
r
P
15 to 25
18
40
25
o
s
b
O
-
In a notebook application, power management efficiency is a high level requirement.
The power dissipation on the power switches becomes an important factor in the selection
of switches. Losses of high-side and low-side MOSFETs depend on their working condition.
)
s
(
ct
Considering the high-side MOSFET, the power dissipation is calculated as:
Equation 40
r
P
e
u
d
o
t
e
l
o
PDHighSide = Pconduction + Pswitching
Maximum conduction losses are approximately given by:
s
b
O
Equation 41
Pconduction = RDSon ⋅
VOUT
2
⋅ ILOAD,MAX
VIN. min
37/47
Application information
PM6675
where RDS(on) is the drain-source on-resistance of the control MOSFET.
Switching losses are approximately given by:
Equation 42
Pswitching =
VIN ⋅ (ILOAD (max) −
2
∆IL
∆I
) ⋅ t on ⋅ fsw VIN ⋅ (ILOAD (max) + L ) ⋅ t off ⋅ fsw
2
2
+
2
where tON and tOFF are the turn-on and turn-off times of the MOSFET and depend on the
gate-driver current capability and the gate charge Qgate. A greater efficiency is achieved with
low RDSon. Unfortunately low RDSon MOSFETs have a great gate charge.
As general rule, the RDS(on) x Qgate product should be minimized to find the suitable
MOSFET.
Logic-level MOSFETs are recommended, as long as low-side and high-side gate drivers are
powered by VVCC = +5V. The breakdown voltage of the MOSFETs (VBRDSS) must be
greater than the maximum input voltage VINmax.
Below some tested high-side MOSFETs are listed.
c
u
d
Table 12. Evaluated high-side MOSFETs
Manufacturer
Type
RDS(on)
(mΩ)
ST
STS12NH3LL
10.5
IR
IRF7811
9
ro
Gate charge
(nC)
P
e
let
12
18
)
s
t(
Rated reverse
voltage (V)
30
30
o
s
b
O
-
In buck converters the power dissipation of the synchronous MOSFET is mainly due to
conduction losses:
Equation 43
c
u
d
(t s)
PDLowSide ≅ Pconduction
Maximum conduction losses occur at the maximum input voltage:
o
r
P
e
Equation 44
t
e
l
o
s
b
O
⎛
V
Pconduction = RDSon ⋅ ⎜1 − OUT
⎜ V
IN,MAX
⎝
The synchronous rectifier should have the lowest RDS(on) as possible. When the high-side
MOSFET turns on, high dV/dt of the phase node can bring up even the low-side gate
through its gate-drain capacitance CRRS, causing a cross-conduction problem. Once again,
the choice of the low-side MOSFET is a trade-off between on resistance and gate charge; a
good selection should minimizes the ratio CRSS / CGS where
Equation 45
CGS = CISS − CRSS
Below some tested low-side MOSFETs are listed.
38/47
⎞
⎟ ⋅ ILOAD,MAX 2
⎟
⎠
PM6675
Application information
Table 13. Evaluated low-side MOSFETs
Manufacturer
Type
RDS(on) (mΩ)
CGD \ CGS
Rated reverse voltage (V)
ST
STS12NH3LL
13.5
0.069
30
ST
STS25NH3LL
40
0.011
30
IR
IRF7811
24
0.054
30
Dual N-MOS can be used in applications with lower output current.
Table 14 shows some suitable dual MOSFETs for applications requiring about 3A.
Table 14. Suitable dual MOSFETs
7.1.5
Manufacturer
Type
RDSon (mΩ)
Gate Charge (nC)
Rated reverse voltage (V)
ST
STS8DNH3LL
25
10
30
IR
IRF7313
46
33
30
Diode selection
c
u
d
)
s
t(
A rectifier across the synchronous switch is recommended. The rectifier works as a voltage
clamp across the synchronous rectifier and reduces the negative inductor swing during the
dead time between turning the high-side MOSFET off and the synchronous rectifier on.
Moreover it increases the efficiency of the system.
e
t
le
o
r
P
Choose a schottky diode as long as its forward voltage drop is very little (0.3V). The reverse
voltage should be greater than the maximum input voltage VINmax and a minimum recovery
reverse charge is preferable. Table 15 shows some evaluated diodes.
o
s
b
O
-
Table 15. Evaluated recirculation rectifiers
Manufacturer
Type
Forward
voltage (V)
Rated reverse
voltage (V)
Reverse current (µA)
ST
STPS1L30M
0.34
30
0.00039
ST
STPS1L30A
0.34
30
0.00039
o
r
P
e
du
)
s
(
ct
t
e
l
o
s
b
O
39/47
Application information
7.1.6
PM6675
VDDQ current limit setting
The valley current limit is set by RCSNS and must be chosen to support the maximum load
current. The valley of the inductor current ILvalley is:
Equation 46
ILvalley = ILOAD (max) −
∆IL
2
The output current limit depends on the current ripple as shown in Figure 20:
Figure 20. Valley current limit waveforms
Current
Inductor current
MAX LOAD 2
MAX LOAD 1
c
u
d
Inductor current
Valley current limit
)
s
t(
Time
e
t
le
o
r
P
As the valley threshold is fixed, the greater the current ripple, the greater the DC output
current will be. If an output current limit greater than ILOAD(max) over all the input voltage
range is required, the minimum current ripple must be considered in the previous formula.
Then the resistor RCSNS is:
Equation 47
)
s
(
ct
o
s
b
O
-
RCSNS =
RDSon ⋅ ILvalley
u
d
o
100uA
where RDSon is the drain-source on-resistance of the low-side switch. Consider the
temperature effect and the worst case value in RDSon calculation (typically +0.4%/°C).
r
P
e
The accuracy of the valley current also depends on the offset of the internal comparator
(±5mV).
t
e
l
o
s
b
O
40/47
The negative valley-current limit (if the device works in forced-PWM mode) is given by:
Equation 48
INEG =
120mV
RDSon
PM6675
7.1.7
Application information
All ceramic capacitors application
Design of external feedback network depends on the output voltage ripple across the output
capacitors' ESR. If the ripple is great enough (at least 20mV), the compensation network
simply consists of a CINT capacitor.
Figure 21. Integrative compensation
Ton One-shot
generator
VSNS
VOUT
+
PWM
Comparator
-
Vr=0.9
V
+
COMP
gm
Integrator
CFILT
RINT
-
c
u
d
VREF
CINT
e
t
le
)
s
t(
o
r
P
o
s
b
O
-
The stability of the system firstly depends on the output capacitor zero frequency. It must be
verified that:
)
s
(
ct
Equation 49
o
r
P
e
du
fSW > k ⋅ fZout =
k
2π ⋅ R out C out
where k is a free design parameter greater than unity (k > 3) . It determines the minimum
integrator capacitor value CINT:
s
b
O
t
e
l
o
Equation 50
CINT >
gm
Vref
⎛f
⎞ Vo
2π ⋅ ⎜ SW − fZout ⎟
k
⎝
⎠
⋅
If the ripple on the COMP pin is greater than the integrator output dynamic (150mV), an
additional capacitor Cfilt could be added in order to reduce its amplitude. If q is the desired
attenuation factor of the output ripple, select:
41/47
Application information
PM6675
Equation 51
C filt =
CINT ⋅ (1 − q)
q
In order to reduce noise on the COMP pin, it's possible to introduce a resistor RINT that,
together with CINT and Cfilt, becomes a low pas filter. The cutoff frequency fCUT must be
much greater (10 or more times) than the switching frequency:
Equation 52
RINT =
2π ⋅ fCUT
1
CINT ⋅ CFILT
CINT + CFILT
For most applications both RINT and Cfilt are unnecessary.
If the ripple is very small (e.g. such as with ceramic capacitors), a further compensation
network, called "Virtual ESR" network, is needed. This additional part generates a triangular
ripple that substitutes the ESR output voltage ripple. The complete compensation scheme is
represented in Figure 22.
c
u
d
Figure 22. Virtual ESR network
o
r
P
e
t
le
so
)
s
(
ct
b
O
-
u
d
o
r
P
e
O
42/47
R1
VOUT
C
RINT
+
gm
+
-
Vr
CFILT
t
e
l
o
bs
R
CINT
PWM Comparator
Ton
Generation
Block
L
Select C as shown:
Equation 53
C > 5 ⋅ CINT
Integrator
1.237V
)
s
t(
PM6675
Application information
Then calculate R in order to have enough ripple voltage on the integrator input:
Equation 54
R=
L
R VESR ⋅ C
Where RVESR is the new virtual output capacitor ESR. A good trade-off is to consider an
equivalent ESR of 30-50mΩ , even though the choice depends on inductor current ripple.
Then choose R1 as follows:
Equation 55
⎛
1 ⎞
⎟
R ⋅ ⎜⎜
π ⋅ fZ ⋅ C ⎟⎠
⎝
R1 =
1
R−
π ⋅ fZ ⋅ C
c
u
d
e
t
le
)
s
(
ct
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
43/47
Package mechanical data
8
PM6675
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Table 16. VFQFPN-24 4mm x 4mm mechanical data
mm.
Dim.
Typ
A
1.00
0.05
A2
0.65
0.80
D
4.00
D1
3.75
E
4.00
E1
3.75
P
0.42
e
0.50
N
24.00
Nd
6.00
c
u
d
b
o
r
P
e
D2
E2
e
t
le
o
r
P
)
s
t(
12°
0.24
0.60
0.30
0.50
0.18
0.30
2.10
1.95
2.25
2.10
1.95
2.25
(s)
o
s
b
O
-
6.00
ct
L
44/47
0.80
0.00
Ne
s
b
O
Max.
A1
θ
t
e
l
o
Min.
du
0.40
PM6675
Package mechanical data
Figure 23. Package dimensions
c
u
d
e
t
le
)
s
(
ct
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
45/47
Revision history
9
PM6675
Revision history
Table 17. Revision history
Date
Revision
31-Jan-2007
1
Changes
Initial release
c
u
d
e
t
le
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
s
b
O
46/47
o
s
b
O
-
o
r
P
)
s
t(
PM6675
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
)
s
t(
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
c
u
d
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
e
t
le
o
r
P
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
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ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
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