PM6680
No Rsense dual step-down controller with adjustable voltages
for notebook system power
Features
■
6 V to 28 V input voltage range
■
Adjustable output voltages
■
5 V always voltage available deliver 100 mA
peak current
■
1.237 V ± 1% reference voltage available
■
Lossless current sensing using low side
MOSFETs RDS(on)
■
Negative current limit
■
Soft-start internally fixed at 2ms
■
Soft output discharge
■
Latched OVP and UVP
■
Selectable pulse skipping at light loads
■
Selectable minimum frequency (33 kHz) in
pulse skip mode
■
4 mW maximum quiescent power
■
Independent power good signals
■
Output voltage ripple compensation
Applications
■
Notebook computers
■
Tablet PC or slates
■
Mobile system power supply
■
3-4 cells Li+ battery powered devices
Table 1.
VFQFPN-32 5X5
Description
PM6680 is a dual step-down controller
specifically designed to provide extremely high
efficiency conversion, with lossless current
sensing technique. The constant on-time
architecture assures fast load transient response
and the embedded voltage feed-forward provides
nearly constant switching frequency operation. An
embedded integrator control loop compensates
the DC voltage error due to the output ripple.
Pulse skipping technique increases efficiency at
very light load. Moreover a minimum switching
frequency of 33kHz is selectable to avoid audio
noise issues. The PM6680 provides a selectable
switching frequency, allowing three different
values of switching frequencies for the two
switching sections. The output voltages OUT1
and OUT2 can be adjusted from 0.9 V to 5.5 V
and from 0.9 V to 3.3 V respectively.
Device summary
Order codes
Package
PM6680
Packaging
Tray
VFQFPN-32 5mm x 5mm (Exposed pad)
PM6680TR
January 2008
Tape and reel
Rev 7
1/49
www.st.com
49
Contents
PM6680
Contents
1
Simplified application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
2.1
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/49
7.1
Constant On time PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2
Constant on time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3
Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . . 22
7.4
Pulse skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.5
No-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.6
Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.7
Soft start and soft end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.8
Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.9
Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.10
Internal linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.11
Power up sequencing and operative modes . . . . . . . . . . . . . . . . . . . . . . . 28
7.12
Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.12.1
Power good signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.12.2
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.12.3
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.12.4
Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PM6680
Contents
7.13
Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.13.1
Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.13.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.13.3
Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.13.4
Input capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.13.5
Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.13.6
Closing the integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.13.7
Other parts design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.13.8
Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3/49
List of figures
PM6680
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
4/49
Simplified application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection (Through top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5V output efficiency vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.05V output efficiency vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PWM no load input battery vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Skip no load battery current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
No-audible skip no load battery current vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Stand-by mode input battery current vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Shutdown mode input battery current vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5V switching frequency vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.05V switching frequency vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LDO5 vs output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5V voltage regulation vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.05V voltage regulation vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Voltage reference vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
OUT1, OUT2 and LDO5 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5V load transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.05V load transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5V soft start (0.25Ω load). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.05V soft start (0.175Ω load). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5V soft end (No load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.05V soft end (No load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5V soft end (1Ω Load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.05V soft end (1Ω Load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5V no-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.05V no-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Constant ON time PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Constant on-time block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Circuitry for output ripple compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PWM and pulse skip mode inductor current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
No audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
RDSON sensing technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Current waveforms in current limit conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Soft start waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Circuitry for output ripple compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Virtual ESR network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
VIN pin filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Inductor current waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Bootstrap circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Current paths, ground connection and driver traces layout . . . . . . . . . . . . . . . . . . . . . . . . 44
Package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
PM6680
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
FSEL pin selection: typical switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
V5SW multifunction pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Operatives modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Protections and operatives modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Inductor manufacturer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Output capacitor manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Input capacitor manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
High side MOSFET manufacturer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Low side MOSFET manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Dual MOSFET manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Shottky diode manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
VFQFPN 5x5x1.0 32L Pitch 0.50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Exposed pad variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5/49
OUT1-
1
OUT1+
1
SGND
FB1
VIN
+
PGND
SGND
PGOOD2
PGOOD1
V+
V+
PGND
5
27
26
16
30
29
17
20
15
21
22
23
SGND
SGND
SGND
BOOT2
SHDN
PGOOD2
PGOOD1
SGND2
COMP1
OUT1
V5SW
CSENSE1
LGATE1
PHASE1
HGATE1
BOOT1
SGND
PM6680
EN2
4
EN1
25
V+
31
VCC
V+
32
+
18
LDO5
VREF
19
LGATE2
PHASE2
HGATE2
BOOT2
SGND
FB2
FB1
NC
COMP2
OUT2
SGND
PGND
CSENSE2
VIN
SKIP
6/49
24
7
28 FB1
6
2
8
1
14
12
13
11
10
SGND
9
SGND
PGND
SGND
PGND
PGND
+
VIN
SGND
1
1
O
O
Figure 1.
FSEL
1
3
BOOT1
Simplified application schematic
PM6680
Simplified application schematic
Simplified application schematic
PM6680
Electrical data
2
Electrical data
2.1
Maximum rating
Table 2. Absolute maximum ratings
Parameter
Value
Unit
V5SW, LDO5 to PGND
-0.3 to 6
V
VIN to PGND
-0.3 to 36
V
HGATEx and BOOTx, to PHASEx
-0.3 to 6
V
(1)
V
PHASEx to PGND
-0.6
CSENSEx , to PGND
CSENSEx to BOOTx
LGATEx to PGND
-0.3
FBx, COMPx, SKIP, , FSEL,VREF to SGND1,SGND2
PGND to SGND1,SGND2
SHDN,PGOODx, OUTx, VCC, ENx to SGND1,SGND2
Power dissipation at TA = 25ºC
Maximum withstanding voltage range test condition:
CDF-AEC-Q100-002- “Human Body Model”
acceptance criteria: “Normal Performance”
to36
-0.6 to 42
V
-6 to 0.3
V
(2)
to LDO5 +0.3
V
-0.3 to Vcc +0.3
V
-0.3 to 0.3
V
-0.3 to 6
V
2.8
W
VIN
±1000
Other pins
±2000
V
1. PHASE to PGND up to -2.5 V for t VREF, Vref in
regulation, V5WS to 5 V
Ish
Operating current sunk by VIN
SHDN connected to GND,
14
18
µA
Isb
Operating current sunk by VIN
ENx to GND, V5SW to GND
190
250
µA
Shutdown section
VSHDN
Device on threshold
1.2
1.5
1.7
V
Device off threshold
0.8
0.85
0.9
V
3.5
ms
110
µA
Soft start section
Soft start ramp time
2
Current limit and zero crossing comparator
ICSENSE
12/49
Input bias current limit
90
100
Comparator offset
VCSENSE-VPGND
-6
6
mV
Zero crossing comparator offset
VPGND - VPHASE
-1
11
mV
Fixed negative current limit
threshold
VPGND - VPHASE
-120
mV
PM6680
Table 5.
Electrical characteristics
Electrical characteristics (continued)
VIN = 12 V, TA = 0 °C to 85 °C, unless otherwise specified (1)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
OUT1=1.5 V
550
650
750
OUT2=1.05 V
230
270
315
OUT1=1.5 V
375
445
515
OUT2=1.05 V
175
210
245
OUT1=1.5 V
285
340
395
OUT2=1.05 V
125
150
175
350
500
ns
1.236
1.249
V
4
mV
0.95
mV
909
mV
On time pulse width
FSEL to
GND
Ton
On time duration
FSEL to
VREF
FSEL to
LDO5
ns
OFF time
TOFFMIN
Minimum off time
Voltage reference
VREF
Voltage accuracy
4 V < VLDO5 < 5.5 V
Load regulation
-100 µA< IREF < 100 µA
Undervoltage lockout fault
threshold
Falling edge of REF
1.224
-4
Integrator
FB
Voltage accuracy
FB
Input bias current
-909
900
0.1
Normal mode
250
Pulse skip mode
60
µA
Over voltage clamp
COMP
Under voltage clamp
mV
-150
Line regulation
Both SMPS, 6 V k × fZout =
k
2π × C out × R out
where k is a design parameter greater than 3 and Rout is the ESR of the output capacitor. It
determinates the minimum integrator capacitor value CINT:
Equation 24
CINT >
gm
Vr
×
⎛ fsw
⎞ VOUT
2π × ⎜
− fZout ⎟
⎝ k
⎠
where gm = 50 us is the integrator transconductance.
In order to ensure stability it must be also verified that:
Equation 25
C INT >
gm
Vr
×
2π × fZout VOUT
37/49
Device description
PM6680
In order to reduce ground noise due to load transient on the other section, it is
recommended to add a resistor RINT and a capacitor Cfilt that, together with CINT, realize a
low pass filter (see Figure 36). The cutoff frequency fCUT must be much greater (10 or more
times) than the switching frequency of the section:
Equation 26
R INT =
2π × fCUT
1
C
× C filt
× INT
C INT + C filt
Due to the capacitive divider (CINT, Cfilt), the ripple voltage at the COMP pin is given by:
Equation 27
VRIPPLEINT = VRIPPLEout ×
CINT
= VRIPPLEout × q
CINT + Cfilt
Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple.
If the ripple is very small (lower than approximately 30 mV), a further compensation network,
named virtual ESR network, is needed. This additional part generates a triangular ripple
that is added to the ESR output voltage ripple at the input of the integrator network. The
complete control schematic is represented in Figure 37.
Figure 37. Virtual ESR network
COMP PIN
VOLTAGE
T NODE
VOLTAGE
? V1
? V1
Vr
OUTPUT
VOLTAGE
t
?V
t
CFILT
Vr
COMP
+
- PWM
t
T
RINT
Vr
C
R
OUT
L
ROUT
D
38/49
COUT
R2
R1
Comparator
gm
CINT
-
R1
FB
+
V1
PM6680
Device description
The T node voltage is the sum of the output voltage and the triangular waveform generated
by the virtual ESR network. In fact the virtual ESR network behaves like a further equivalent
ESR RESR.
A good trade-off is to design the network in order to achieve an RESR given by:
Equation 28
RESR =
VRIPPLE
− Rout
∆IL
where ∆IL is the inductor current ripple and VRIPPLE is the overall ripple of the T node
voltage. It should be chosen higher than approximately 30 mV.
The new closed loop gain depends on CINT. In order to ensure stability it must be verified
that:
Equation 29
C INT >
gm
Vr
×
2π × fZ VOUT
Where:
Equation 30
fZ =
1
2π × C out × R TOT
where RTOT is the sum of the ESR of the output capacitor Rout and the equivalent ESR
given by the virtual ESR network RESR.
Moreover CINT must meet the following condition:
Equation 31
fsw > k × fZ =
k
2π × C out × R TOT
Where k is a free design parameter greater than 3 and determines the minimum integrator
capacitor value CINT:
Equation 32
CINT >
gm
Vr
×
V
f
⎞
⎛
OUT
2π × ⎜⎜ sw − fZ ⎟⎟
k
⎠
⎝
C must be selected as shown:
Equation 33
C > 5 × C INT
39/49
Device description
PM6680
R must be chosen in order to have enough ripple voltage on integrator input:
Equation 34
R=
L
RESR × C
R1 can be selected as follows:
Equation 35
⎛
1
R × ⎜⎜
⎝ C × π × fZ
R1 =
1
R−
C × π × fZ
⎞
⎟⎟
⎠
Example:
OUT1 = 1.5 V, fSW = 290 kHz, L = 2.5 uH, Cout = 330 uF with Rout
≈ 12 mΩ.
We design RESR = 12mW. We choose CINT = 1nF by equations 30, 33 and Cfilt = 47 pF,
RINT = 1 kΩ by eq.27, 28. C = 5.6 nF by Eq.34. Then R = 36 kΩ (eq.35) and R1 = 3 kΩ
(eq.36).
7.13.7
Other parts design
●
VIN filter
A VIN pin low pass filter is suggested to reduce switching noise. The low pass filter is
shown in the next figure:
Figure 38. VIN pin filter
R
Input
voltage
VIN
C
100pF
Typical components values are: R = 3.9 Ω and C = 4.7 uF.
●
40/49
VCC filter
A VCC low pass filter helps to reject switching commutations noise:
PM6680
Device description
Figure 39. Inductor current waveforms
LDO5
R
VC C
C
Typical components values are: R=47 Ω and C = 1 uF.
●
VREF capacitor
A 10 nF to 100 nF ceramic capacitor on VREF pin must be added to ensure noise
rejection.
●
LDO5 output capacitors
Bypass the output of each linear regulator with 1 uF ceramic capacitor closer to the
LDO pin and a 4.7 uF tantalum capacitor (ESR = 2 Ω). In most applicative conditions a
4.7 uF ceramic output capacitor can be enough to ensure stability.
●
Bootstrap circuit
The external bootstrap circuit is represented in the next figure:
Figure 40. Bootstrap circuit
D
RBOOT
L
CBOOT
LDO5
BOOT
PHASE
The bootstrap circuit capacitor value CBOOT must provide the total gate charge to the high
side MOSFET during turn on phase. A typical value is 100nF.
The bootstrap diode D must charge the capacitor during the off time phases. The maximum
rated voltage must be higher than VINmax.
A resistor RBOOT on the BOOT pin could be added in order to reduce noise when the phase
node rises up, working like a gate resistor for the turn on phase of the high side MOSFET.
41/49
Device description
7.13.8
PM6680
Design example
The following design example considers an input voltage from 7 V to 16 V. The two switching
outputs are OUT1=1.5 V and OUT2=1.05 V and must deliver a maximum current of 5 A. The
selected switching frequencies are about 290 kHz for OUT1 section and about 425 kHz for
OUT2 section (see Table 7 on page 30).
1.
Inductor selection
OUT1: ILOAD = 5 A, 35 % ripple current.
Equation 36
L=
1.5V ⋅ (16V − 1.5V)
≈ 2.5µH
290KHz ⋅ 16V ⋅ 0.35 ⋅ 5
We choose standard value L = 2.5 uH.
∆IL(max) = 1.8 A @VIN =12 V
ILRMS = 5.03 A
IPEAK = 5 A + 0.9 A = 5.9 A
OUT2: ILOAD = 5 A, 30 % ripple current.
Equation 37
L=
1.05V ⋅ (16V − 1.05V)
≈ 1.6µH
425KHz ⋅ 16V ⋅ 0.3 ⋅ 5
∆IL(max) = 1.6 A @VIN = 12 V.
ILRMS = 5.02 A
IPEAK = 5 A + 0.8 A = 5.8 A
2.
Output capacitor selection
We would like to have an output ripple smaller than 25 mV.
OUT1: POSCAP 6TPB330M
OUT2: POSCAP 6TPB330M
3.
Power MOSFETS
OUT1: High side: STS12NH3LL
Low side: STS12NH3LL
OUT2:High side: STS12NH3LL
Low side: STS12NH3LL
4.
Current limit
OUT1:
Equation 38
ILvalley (min) = ILOAD (max) −
42/49
∆IL (min)
= 4.12A
2
PM6680
Device description
Equation 39
RCSENSE ≡
4.12A
⋅ 16.25mΩ ≈ 670Ω
100µA
(Let's assume the maximum temperature Tmax = 75 °C in RDSon calculation)
OUT2:
Equation 40
ILvalley (min) = ILOAD (max) −
∆IL (min)
= 4.2A
2
Equation 41
RCSENSE ≡
4 .2 A
⋅ 16.25mΩ ≈ 680Ω
100µA
(Let's assume Tmax = 75 °C in RDSon calculation)
5.
Input capacitor
Maximum input capacitor RMS current is about 2.8 A. Then ICinRMS > 2.8 A.
We put three 10 uF ceramic capacitors with Irms = 1.5 A.
6.
Synchronous rectifier
OUT1: Shottky diode STPS1L30M
OUT2: Shottky diode STPS1L30M
7.
Integrator loop
(Refer to Figure 37)
OUT1: The ripple is smaller than 40mV, then the virtual ESR network is required.
CINT = 1 nF; Cfilt = 47 pF; RINT =1 kΩ
C = 5.6 nF; R= 36 kΩ; R1 = 3 kΩ
OUT2: The ripple is smaller than 40 mV, then the virtual ESR network is required.
CINT = 1 nF; Cfilt = 110pF; RINT = 1 kΩ
C = 5.6 nF; R = 22 kΩ; R1 = 3.3 kΩ
8.
Output feedback divider
(Refer to Figure 30 on page 24)
OUT1: R1 = 10 kΩ; R2 = 6.8 kΩ
OUT2: R1 = 11 kΩ; R2 = 1.8 kΩ
9.
Layout guidelines
The layout is very important in terms of efficiency, stability and noise of the system. It is
possible to refer to the PM6680 demoboard for a complete layout example.
For good PC board layout follows these guidelines:
●
Place on the top side all the power components (inductors, input and output capacitors,
MOSFETs and diodes). Refer them to a power ground plan, PGND. If possible, reserve
a layer to PGND plan. The PGND plan is the same for both the switching sections.
●
AC current paths layout is very critical (see Figure 41 on page 44). The first priority is to
minimize their length. Trace the LS MOSFET connection to PGND plan as short as
43/49
Device description
●
●
PM6680
possible. Place the synchronous diode D near the LS MOSFET. Connect the LS
MOSFET drain to the switching node with a short trace.
Place input capacitors near HS MOSFET drain. It is recommended to use the same
input voltage plan for both the switching sections, in order to put together all input
capacitors.
Place all the sensitive analog signals (feedbacks, voltage reference, current sense
paths) on the bottom side of the board or in an inner layer. Isolate them from the power
top side with a signal ground layer, SGND. Connect the SGND and PGND plans only in
one point (a multiple vias connection is preferable to a 0 ohm resistor connection) near
the PGND device pin. Place the device on the top or on the bottom size and connect
the exposed pad and the SGND pins to the SGND plan (see Figure 41).
Figure 41. Current paths, ground connection and driver traces layout
●
●
●
●
44/49
As general rule, make the high side and low side drivers traces wide and short. The
high side driver is powered by the bootstrap circuit. It's very important to place
capacitor CBOOT and diode DBOOT as near as possible to the HGATE pin (for
example on the layer opposite to the device). Route HGATE and PHASE traces as near
as possible in order to minimize the area between them.
The Low side gate driver is powered by the 5V linear regulator output. Placing PGND
and LGATE pins near the low side MOSFETs reduces the length of the traces and the
crosstalk noise between the two sections.
The linear regulator output LDO5 is referred to SGND as long as the reference voltage
Vref. Place their output filtering capacitors as near as possible to the device.
Place input filtering capacitors near VCC and VIN pins.
It would be better if the feedback networks connected to COMP, FB and OUT pins are
"referred" to SGND in the same point as reference voltage Vref. To avoid capacitive
PM6680
Device description
●
coupling place these traces as far as possible from the gate drivers and phase
(switching) paths.
Place the current sense traces on the bottom side. If low side MOSFET RDSon sensing
is enabled, use a dedicated connection between the switching node and the current
limit resistor RCSENSE.
45/49
Package mechanical data
8
PM6680
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Table 17.
VFQFPN 5x5x1.0 32L Pitch 0.50
Databook (mm)
Dim.
Min
Typ
Max
A
0.8
0.9
1
A1
0
0.02
0.05
A3
0.2
b
0.18
0.25
D
4.85
5
D2
0.3
5.15
See exposed pad variations
E
4.85
E2
(2)
5
5.15
See exposed pad variations
e
(2)
0.5
L
0.3
0.4
0.5
ddd
Table 18.
0.05
Exposed pad variations
(1)(2)D2
E2
Min
Typ
Max
Min
Typ
Max
2.90
3.10
3.20
2.90
3.10
3.20
1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead. Very thin:
A = 1.00mm Max.
2. Dimensions D2 & E2 are not in accordance with JEDEC.
46/49
PM6680
Package mechanical data
Figure 42. Package dimensions
47/49
Revision history
9
PM6680
Revision history
Table 19.
48/49
Document revision history
Date
Revision
Changes
17-Mar-2006
1
Initial release
10-May-2006
2
Few updates
29-Jun-2006
3
Mechanical data updated
28-Jul-2006
4
Application schematic updated Figure 27 on page 16
25-Oct-2006
5
Changes electrical characteristics, added COMP value skip mode,
Order code table updated
28-Aug-2007
6
Updated: Current sensing option and Absolute Maximum Ratings
21-Jan-2008
7
Updated: Table 1 on page 1, Table 3 on page 7,
Section 4 on page 12
PM6680
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49/49
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