PM8805TR

PM8805 IEEE 802.3bt PoE-PD interface with embedded dual active bridge Datasheet - Production data Applications  High power wireless data systems  Security cameras  Access points  Public information displays  PoE lighting systems VFQFPN43 8x8mm exposed pad Description Features  Dual active bridge, hot swap MOSFETand PoE-PD interface in a system-in-package  100 V N-ch MOSFETs with 0.2 Ω total path resistance for each active bridge.  100 V, 0.1 Ω high-side N-ch hot swap MOSFET  PoE-PD single-signature interface compliant with IEEE 802.3bt / at / af  Supports 4-pair PoE applications  Supports 12 V auxiliary sources  Identifies which kind of PSE (standard or legacy) is connected with and provides successful IEEE802.3bt / at / af classification indication as a combination of the T0, T1 and T2 signals (open drain)  Smart operational modes  Programmable classification current with 3.3 ms delay.  Optional Autoclass feature The PM8805 is a system-in-package for smart power supply of Power over Ethernet (PoE) Powered Devices (PD) and it is applicable for power level up to 99.9 W. It embeds: two active bridges and their driving circuitry, a charge pump to drive the high-side MOSFETs, the hot swap MOSFET and the interface compliant with IEEE 802.3bt. The device performs the physical layer classification, providing the indication of successful PSE type identification. A 4-pair PSE is identified and the information is available by a dedicated matrix of Tx signals. The device works with power either from the Ethernet cable or from an external power source such as a wall adapter, with possible prevalence of the auxiliary source with respect to the PoE. The PM8805 is suitable to build the interface section of PoE switch mode power supplies targeting the highest conversion efficiency. It provides a PGD signal that can be used to enable a PWM controller, a DC-DC converter or an LED driver.  Advanced energy-saving MPS timings  Two-step hot swap current protection: DC with 1 ms delay and short-circuit with 10 us delay. Table 1. Device summary Part number Package Packing PM8805TR VFQFPN 8X8X1.0 43L PITCH 0.5 Tape and reel  Controlled pre-charge of the output capacitor  PGD signal (open drain) to enable an external PWM controller.  Thermal shutdown protection April 2019 This is information on a product in full production. DS12813 Rev 2 1/48 www.st.com Contents PM8805 Contents 1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 6 1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 5 2/48 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PM8805 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 Detection and DET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 Boot and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 PoE classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 Autoclass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5 Charge pump and VCP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.6 Input Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7 Hot swap, CTRL and PGD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.8 Hot swap protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.9 Interface with a DC/DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.10 Auxiliary sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.11 Operation modes and STBY, FAUX, RAUX command signals . . . . . . . . 32 4.12 Type T0, T1, T2 output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.13 Standby and MPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.14 Special operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Thermal aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2 Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DS12813 Rev 2 PM8805 Contents 6 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7 VFQFPN43 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.1 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DS12813 Rev 2 3/48 48 List of tables PM8805 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. 4/48 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Classification table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PD unbalance specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PD main parameters table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PM8805 control signals description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PM8805 type signals description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Minimum information needed for confirming requested class. . . . . . . . . . . . . . . . . . . . . . . 34 MPS current profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DS12813 Rev 2 PM8805 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Simplified application schematic for a PD using PM8805 as input stage . . . . . . . . . . . . . . . 6 PM8805 general internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DET internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Classification signals and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 CLS internal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Simplified general schematic with PM8805 and CM filter before the DC/DC . . . . . . . . . . . 29 Simplified front aux connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Simplified rear aux connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 MPS current profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2-pair power dissipation configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4-pair power dissipation configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Example of layout for PM8805 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 VFQFPN43 8x8mm 43 lead 0.5mm pitch (8x8x1.0mm ) mechanical data . . . . . . . . . . . . . 44 VFQFPN43 8x8mm 43 lead 0.5mm pitch (8x8x1.0 mm ) mechanical data 2 . . . . . . . . . . . 45 VFQFPN43 8x8mm 43 lead 0.5mm pitch (8x8x1.0 mm) mechanical data 3 . . . . . . . . . . . 45 Suggested footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DS12813 Rev 2 5/48 48 Typical application circuit and block diagram PM8805 1 Typical application circuit and block diagram 1.1 Application circuit Figure 1. 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PM8805 general internal block diagram  DS12813 Rev 2 7/48 48 Pin description and connection diagram 2 PM8805 Pin description and connection diagram Figure 3. Pin connections (top view) Table 2. Pin description Pin# Name 1, 40, 41 IN78 2 VB Internal reference voltage 5V up to 10mA; filter this pin with a ceramic capacitor of 100nF typ. connected to AGND. This voltage can be used to bias the I/O pins of PM8805, if needed. STBY A high level applied to this pin activates an internal 10 / 18mA current source to implement the MPS feature. Duty cycle is Long (.af /.at) or Short (.bt) depending on the detected PSE: Type 2, or Type 3 and 4. Use a resistor voltage divider to AGND to connect this 5V voltage rating pin: typical value for the threshold is 1.25V. If higher than 0.5V during first classification finger, Autoclass feature is enabled. Connect this pin to AGND if not used. CLS1 Classification resistor pin for first and second Class Events. Connect a 0805 classification programming resistor from this pin to AGND. The external resistor is activated with a 3.3ms typ. delay with respect to the classification event. 3 4 8/48 Function Input for the signals connected to "Spare" pairs. This signal along with IN45 signals is used to feed the 2nd internal bridge. DS12813 Rev 2 PM8805 Pin description and connection diagram Table 2. Pin description (continued) Pin# Name Function 5 CLS2 Classification resistor pin for first and second Class Events. Connect a 0805 classification programming resistor from this pin to AGND. The external resistor is activated with a 3.3ms typ. delay with respect to the classification event. 6 AGND This pin is the ground connection for the PM8805 controller. It must be connected to the other GNDxx pins with short and strong trace. T0 PSE type identification signal. T0 open drain signal assertion happens as described in Table 3. This pin is an active low signal, and can be pulled up to VB with an external resistor. T1 PSE type identification signal. T1 open drain signal assertion happens as described in Table 3. This pin is an active low signal, and can be pulled up to VB with an external resistor. T2 PSE type identification signal. T2 open drain signal assertion happens as described in Table 3. This pin is an active low signal, and can be pulled up to VB with an external resistor. FAUX This pin can be used to allow the PD to be powered with an auxiliary power source like an external wall adapter connected before the hot swap MOSFET, with voltage lower than the nominal PoE voltage range. Pulling up this pin forces the hot swap MOSFET to turn on when VIN is below the internal UVLO threshold. It may also be used to implement a UVLO override for a low-voltage PoE application. It may be used in combination with RAUX and STBY pins to perform operational modes as described in Table 4. Use a resistor voltage divider from the auxiliary voltage to AGND to connect this 5V voltage rating pin: typical value for the threshold is 1.25V. Connect this pin to AGND if not used. 11 RAUX This pin can be used to give high priority to an auxiliary power source like an external wall adapter connected after the hot swap MOSFET, without stopping the DC/DC operations. It may be used in combination with FAUX and STBY pins to perform operational modes as described in Table 4. Use a resistor voltage divider from the auxiliary voltage to AGND to connect this 5V voltage rating pin: typical value for the threshold is 1.25V. Connect this pin to AGND if not used. 12, 15, 16 IN12 7 8 9 10 Input for the signals connected to "Tx and Rx" pairs. This signal, along with IN36 signals, is used to feed the 1st internal bridge. DS12813 Rev 2 9/48 48 Pin description and connection diagram PM8805 Table 2. Pin description (continued) Pin# Name Function GND12 System low potential; it is the return of the first active bridge and it is connected to the Source of the IN12 low-side MOSFET. It must be connected to the system AGND, together with the other bridges' grounds. 17, 18, 29, 38, 39 VOB System high potential; it is the positive potential of the active bridges and it is connected to the drain of the internal bridge, high-side MOSFETs. Protect the rectified voltage with a TVS and a 100nF X7R 100V rated ceramic capacitor as per IEEE802.3 standard. 19, 20, 23 IN36 Input for the signals connected to "Tx and Rx" pairs. This signal along with IN12 signals is used to feed the 1st internal bridge. 13, 14 GND36 System low potential; it is the return of the first active bridge and it is connected to the Source of the IN36 low-side MOSFET. It must be connected to the system AGND, together with the other bridges' grounds. CTRL Protected replica of the internal gate driver for an external hot swap MOSFET. To slow down the rising edge of this signal a small value ceramic capacitor may be added between this pin and GND. 25 PGD High-voltage rating, open drain output signal to be used as Enable for a DC/DC converter feed with VOUT voltage. It is pulled down until the PoE voltage is below UVLO, or FAUX is asserted, and the hot swap MOSFET is completely closed. A 85ms delay typ. is required when receiving power from a PSE before this signal is asserted. PGD is also asserted as soon as an RAUX configuration is set. 26 NC 27, 28 VOUT 30 VDD High-voltage rating pin, it is the supply voltage input for the PM8805 controller. It must be connected to VOB. 31 DET Detection resistor, high-voltage rating pin. Connect the signature resistance between DET pin and VOB. Current flows through the resistor only during the detection phase; a typical value for it is 26.1KΩ. This pin has negligible resistance with respect to the external resistance. 32 VCP High-voltage rating pin, output of the internal charge pump. Connect a 0.5A fast switching diode and a 10nF, 50V X7R ceramic capacitor between this pin and VDD to filter this pin. 33, 36, 37 IN45 Input for the signals connected to "Spare" pairs. This signal along with IN78 signals is used to feed the 2nd internal bridge. 21,22 24 10/48 High-voltage rating spare pin. At the moment its function is undefined. Source of the high side, hot swap MOSFET. This voltage can be used as input voltage for a DC/DC converter. DS12813 Rev 2 PM8805 Pin description and connection diagram Table 2. Pin description (continued) Pin# 34, 35 42, 43 EP1 EP2 EP3 EP4 EP5 EP6 Name Function GND45 System low potential; it is the return of the second active bridge and it is connected to the Source of the IN45 low-side MOSFET. It must be connected to the system AGND, together with the other bridges' grounds. GND78 System low potential; it is the return of the second active bridge and it is connected to the Source of the IN78 low-side MOSFET. It must be connected to the system AGND, together with the other bridges' grounds. EP1 Exposed pad Connect the pad to a PCB copper plane to improve heat dissipation; it must be electrically connected to the IN78 signal. Internally the pad is connected with the drains of the lower side MOSFETs used in the 2nd bridge. EP2 Exposed pad Connect the pad to a PCB copper plane to improve heat dissipation; it must be electrically connected to the IN45 signal. Internally the pad is connected with the drains of the lower side MOSFETs used in the 2nd bridge. EP3 Exposed pad Connect the pad to a PCB copper plane to improve heat dissipation; it must be electrically connected to the IN36 signal. Internally the pad is connected with the drains of the lower side MOSFETs used in the 1st bridge. EP4 Exposed pad Connect the pad to a PCB copper plane to improve heat dissipation; it must be electrically connected to the IN12 signal. Internally the pad is connected with the drains of the lower side MOSFETs used in the 1st bridge. EP5 Main exposed pad Connect this pad to a PCB copper plane to improve heat dissipation; it must be electrically connected to VOB. Internally this pad is connected with the drain of the upper side MOSFETs used in the bridges. EP6 Exposed pad Connect the pad to a PCB copper plane to improve heat dissipation; it must be electrically connected to the VOB signal. Internally the pad is connected with EP5, the drain of the high-side MOSFET used in the hot swap section. DS12813 Rev 2 11/48 48 Electrical specifications PM8805 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings(1) Parameter V(BR)DSS VOB, VDD to AGND (2) Value Unit 100 V -0.3 to 85 V VCP to VOB -0.3 to 10 V VCP to AGND -0.3 to 95 V IN12, IN36, IN45, IN78 to AGND -0.7 to 85 V IN12, IN36, IN45, IN78 to VOB -85 to 0.7 V IN12, IN36, IN45, IN78 max. input continuous current 2.0 A -0.3 to 0.3 V VOUT to AGND -0.3 to 85 V GND12, GND36, GND45, GND78 to AGND(2) VOUT to VOB -85 to 0.7 V Max. VOUT output continuous current 3.0 A CTRL to AGND -0.3 to 95 V CTRL to VOB -85 to 10 V CTRL to VCP -95 to 0.3 V VB to AGND -0.3 to 6 V VB to VOB -85 to 0.3 V Max VB output current 10 mA DET, PGD to AGND -0.3 to 85 V DET, PGD to VOB -85 to 0.3 V PGD to VOUT -85 to 0.3 V CLS1, CLS2 to AGND -0.3 to 3.6 V FAUX, RAUX, STBY to AGND -0.3 to 6 V T0, T1, T2 to AGND -0.3 to 6 V T0, T1, T2 to VB -6 to 0.3 V ESD HBM 2 kV ESD CDM 500 V Maximum operating junction temperature (3) -40 to 150 °C Storage temperature -40 to 150 °C 1. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. VDD must be connected to VOB. GND12, GND36, GND45, GND78 must be connected to AGND. 3. Internally limited to 160°C typ. with internal overtemperature protection circuit. 12/48 DS12813 Rev 2 PM8805 3.2 Electrical specifications Recommended operating conditions Table 4. Recommended operating conditions Parameter Min. Max. Unit PoE input voltage range VOB to AGND 36(1) 57(1) V Front AUX Input voltage range to AGND 15 57 V Rear AUX Input voltage range to AGND 9 57 V Output current from VOUT signal pins 2 A Input current for each INxx signal 1 A 1. Those are the limits of the input voltage as specified in the IEEE PoE standard valid for all PD systems. DS12813 Rev 2 13/48 48 Electrical specifications 3.3 PM8805 Thermal data Table 5. Thermal data Symbol Parameter (1) Max. value Unit RTHJA Thermal resistance junction to ambient 30 °C/W RTHJB Thermal resistance junction to board(1) Pd max TA Maximum power dissipation of device 15 °C/W (2) 1.3 W (3) -40 to 85 °C Operative ambient temperature range 1. Device mounted on a 4" x 4" wide, 4-layer board (2 signal + 2 power), Cu thickness 35 micron, with: - 4 small exposed pad (EP1-4) copper areas connected to two power planes plus an external layer of 0.12"x0.12" inches minimum size; those areas are connected together with a minimum of 2x3 via holes. - a large central exposed pad (EP5) and hot swap exposed pad (EP6) copper area connected to two power planes of 1"x1" inches plus two layers with "minimum pad size shape": those areas are connected with a minimum of 3 times 2x3 via holes placed close the dissipating zone of the device. See Section 7 for more details. 2. Device mounted on the board as described in Note 1 and Tambient = 85°C. The indicated maximum power dissipation for the device has been calculated as: (TJmax -TAmax) / RTHJA. The estimated worst case device power dissipation in 4P application is: Bridge+ HotSwap+ Controller=4 x 0.15Ω x 1A2 + 0.15Ω x 2 A2 + 0.1W = 1.3W. 3. Heat sink is needed in order to not reach device thermal limitation. 14/48 DS12813 Rev 2 PM8805 3.4 Electrical specifications Electrical characteristics (VDD=VOB=48 V, 1 nF from VCP to VDD, 100 nF on VB, TA = -40°C to 85°C unless otherwise specified(a).) Table 6. Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit Vuvlo_rising UVLO release Measured between PoE inputs(1) VDD rising 38.0 41.5 V Vuvlo_falling UVLO lock-out Measured between PoE inputs VDD(1) falling 30.5 33.5 V Vuvlo_hyst UVLO hysteresis VDD falling 7.5 V Tduvlo_falling UVLO lock-out delay VDD falling 100 μs Rdson_br MOSFET Ron 30.5< VDD