PM8908TR

PM8908 Monolithic buck converter for DDR memory termination Datasheet - production data Applications • Memory termination regulator for DDR3, DDR4 and low power DDR3/DDR4 • Notebook/desktop/server • Low voltage application for 1 V to 3.5 V input rails QFN20 3.5 x 4.0 mm Description Features The PM8908 is a high efficiency monolithic stepdown switching regulator designed mainly for the DDR termination. • Integrated MOSFETs for high efficiency • Current COT architecture The IC operates from 1 V to 3.5 V input voltage (VIN). • 1 V to 3.5 V input voltage (VIN) • 5.0 V supply voltage (VCC) • Constant frequency mode • 1% output voltage accuracy • Two programmable switching frequencies (0.6 MHz or 1 MHz) • ADJ output voltage from 0.5 V to 2 V • Embedded bootstrap diode • OV/UV/OC and overtemperature protection • Soft-off with integrated discharge resistor • External tracking • Power Good output • QFN20 3.5 x 4.0 mm compact package The device uses a COT control loop that provides very good performances in terms of load and line transients. The current sense is internally thermally compensated for optimum precision. The output voltage is adjusted from 0.5 V to 2 V with ± 1% accuracy overtemperature variations. The PM8908 also provides external tracking support. The PM8908 provides positive and negative overcurrent protection as well as over/undervoltage and overtemperature protection. PGOOD output easily provides realtime information on the output voltage. The PM8908 is available in a QFN20 3.5 x 4.0 mm package. Table 1. Device summary Order code Package Packaging PM8908TR QFN20 (3.5 x 4.0 mm) Tape and reel July 2017 This is information on a product in full production. DocID027688 Rev 4 1/28 www.st.com Contents PM8908 Contents 1 2 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 4 1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 Startup and shutdown management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Soft-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 6 2/28 Output voltage monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4.2 Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4.3 Power Good (PGOOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4.5 Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Output voltage setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 Droop setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 Non-droop setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.7 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DocID027688 Rev 4 PM8908 7 Contents Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 8 QFN20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DocID027688 Rev 4 3/28 28 Typical application circuit and block diagram PM8908 1 Typical application circuit and block diagram 1.1 Application circuit Figure 1. Typical application circuit VCC = 5 V 20 CVCC RPGOOD 6 VCC VIN GND PGND VIN = 1 V to 3.5 V 4, 5 CVIN 1, 2, 3 PM8908 19 17 18 PGOOD EN CBOOT L REFIN 7 REF PHASE R1 R2 16 MODE 9 RM BOOT COMP VOUT 11, 12, 13, 14, 15 COUT VOUT 10 8 CP CF CREF RF Figure 2. Typical memory termination application circuit VCC = 5 V RPGOOD 20 CVCC 6 VCC VIN GND PGND VDDQ = 1.2 V 4, 5 CVIN 1, 2, 3 PM8908 19 17 18 RM PGOOD EN REFIN 7 REF COMP 8 CP R2 CREF 4/28 CBOOT L PHASE R1 R1=R2 16 MODE 9 VDDQ BOOT CF RF DocID027688 Rev 4 VOUT 11, 12, 13, 14, 15 10 VOUT = 0.6 V COUT PM8908 1.2 Typical application circuit and block diagram Block diagram Figure 3. Block diagram PGOOD VCC MODE REFIN -16% Hy VOUT Delay VCC UVLO VIN Hy PM8908 REFIN +16% BOOT REFIN -30% UV VOUT EN COT CONTROL LOGIC, PROTECTIONS & ADAPTIVE DEAD TIMES OV SS REFIN +20% REFIN PHASE DEAD TIMES VCC VOUT COMP REF Voltage Reference K THERMAL MONITOR PHASE PGND CL GND PGND Discharge DocID027688 Rev 4 Current Limit 5/28 28 Pin description and connection diagrams 2 PM8908 Pin description and connection diagrams VCC PGOOD MODE EN BOOT Figure 4. Pin connection (top view) 20 19 18 17 16 PGND 1 15 PHASE PGND 2 14 PHASE PGND 3 13 PHASE VIN 4 12 PHASE VIN 5 11 PHASE 7 8 9 REF COMP REFIN 10 VOUT 6 GND PM8908 Pin description Table 2. Pin description Pin Function No. Name 1 2 PGND Power ground connection, connected to the embedded low-side MOSFET source. Connect to the PGND PCB plane. See Figure 1. 3 4 VIN Power input voltage, connected to the embedded high-side MOS drain. Supply range is from 1 V to 3.5 V. Bypass VIN pins to PGND pins close to the IC package with high quality MLCC capacitors. See Figure 1. 6 GND All the internal references are referred to this pin. Connect to the PCB signal ground. 7 REF Reference output. Connect a 1 µF MLCC capacitor to GND. See Figure 1. 8 COMP Error amplifier output. Connect with RF - CF to the REF pin for loop compensation. See Figure 1. 9 REFIN Reference input. Apply a voltage between 0.5 to 2.0 V. Filter with at least 0.01 µF MLCC capacitors to GND. 10 VOUT Output voltage sense. 5 6/28 DocID027688 Rev 4 PM8908 Pin description and connection diagrams Table 2. Pin description (continued) Pin Function No. Name 11 12 PHASE Output inductor connection. The pins are connected to the embedded MOSFETs (high-side source and low-side drain). Connect directly to the output inductor. See Figure 1. 16 BOOT Bootstrap pin. It provides power supply for the floating high-side MOS driver. Connect with 0.1 µF to PHASE. See Figure 1. 17 EN 18 MODE Switching frequency and the OCL programming pin. See Table 6 on page 14. This pin must not be left floating. 19 PGOOD Power Good pin. Open drain output set free after SS has finished and pulled low when VOUT is out of the PGOOD window or any protection is triggered. Pull up to VCC, if not used it can be left floating. 20 VCC 13 14 15 Thermal pad Enable. Device power supply. Operative voltage is 5.0 V. Filter with at least 1 µF MLCC vs. GND. The thermal pad of the device. Connect to the PCB ground plane with multiple VIAS. DocID027688 Rev 4 7/28 28 Thermal data 3 PM8908 Thermal data Table 3. Thermal data Symbol 8/28 Parameter Value Unit RthJA Thermal resistance junction to ambient (Device soldered on demonstration board) 40 °C/W TMAX Maximum junction temperature 150 °C TSTG Storage temperature range -55 to 150 °C TJ Junction temperature range -40 to 150 °C DocID027688 Rev 4 PM8908 Electrical specifications 4 Electrical specifications 4.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol Parameter Value(1) Unit VCC To PGND, GND -0.3 to 7 V VIN To PGND, GND -0.3 to 4 V To PGND, GND -0.3 to 11 BOOT To PGND, GND, t < 10 ns To PHASE To PGND, GND PHASE To PGND, GND, t < 10 ns -0.3 to 12.2 (2) V V -0.3 to 7 V -2 to 4 V -2.2 to 7.5(2) V PGOOD To PGND, GND -0.3 to 7 V EN To PGND, GND -0.3 to 7 V VOUT To PGND, GND -1.0 to 3.6 V To GND -0.3 to 3.6 V REFIN, COMP, REF, MODE 1. All voltages need to be lower than V CC under any condition. 2. Regardless of application configuration, it is mandatory not to exceed the AMR voltage value on the BOOT and PHASE pins. Note: Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal. DocID027688 Rev 4 9/28 28 Electrical specifications 4.2 PM8908 Electrical characteristics VCC = 5.0 V ± 5%, TA = 70°C (unless otherwise specified). Table 5. Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit 0.3 5 µA Supply current and undervoltage lockout IIN VIN shutdown current Shutdown, EN = 0 V ICC VCC supply current EN = H, VBOOT = 4.5 V, VCC = 4.5 V, VIN = 3.5 V, VM = GND 2 3.6 mA VCC shutdown current Shutdown, EN = 0 V 4 10 µA IBSS Boot input current VBOOT = 9 V, VPHASE = 3.5 V, VCC = 5.5 V 150 µA VCC VCC supply voltage ICCSD VCC UVLO REF UVLO VCC turn-on VCC rising 4.5 5.0 5.5 V 4.2 4.37 4.5 V Hysteresis VREF turn-on REF rising Hysteresis 440 mV 1.8 V 100 mV Oscillator, off-time and on-time fSW tOFF-min Oscillator accuracy Minimum off-time RM = 100 kΩ 1 RM = 47 kΩ 0.6 VIN = 1.5 V, VOUT = 0.9 V, VREFIN = 1 V, fSW = 1 MHz / 0.6 MHz 170 MHz ns Reference and GM amplifier ∆VOUT VREF Output voltage accuracy VREFIN = 1 V, no droop Voltage reference IREF = 0 -1 1.95 (1) 2.0 +1 % 2.05 V GM Transconductance ICSK COMP pin maximum sinking current ICSR COMP pin maximum sourcing current VCM Common mode input voltage range(1) 0 2 V VDM Differential mode input voltage range(1) 0 80 mV VOSet Input offset mS VCOMP = 2 V, VREFIN - VOUT = -80 mV 80 µA VCOMP = 2 V, VREFIN - VOUT = 80 mV -80 µA 0 frequency(1) F-3dB -3 dB ACS Current sense gain 10/28 1.00 4.5 Gain from the current of the LS to PWM comp when PWM = OFF DocID027688 Rev 4 47.3 6.0 mV 7.5 MHz 59.3 mV/A PM8908 Electrical specifications Table 5. Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit 51 Ω Soft-end RDS Phase discharge resistance Overcurrent protection IOCL Positive overcurrent threshold LS sourcing, RM = 47 kΩ IOCLN Negative overcurrent threshold LS sourcing, RM = 47 kΩ 4 7.6 11 A -11 - 7.6 -4 A 12.6 Ω 123 % VREFIN Bootstrap switch RBSS Boot switch on-resistance IBOOT = 10 mA, TA = 25 °C Over and undervoltage protection OVP OVP threshold VOUT rising tOVPd OVP delay Time from the VOUT pinout of + 20% of REFIN to OVP fault UVP UVP threshold VOUT falling tUVPd UVP delay Time from the VOUT pinout of -30% of REFIN to UVP fault 256 µs Time from EN = H to undervoltage ready 2.4 ms External tracking Time from EN = H to undervoltage ready 9 ms Thermal shutdown threshold(1) 145 °C Thermal shutdown hysteresis(1) 10 °C Undervoltage fault enable delay 117 120 µs 10 65 68 71 % VREFIN Overtemperature protection OTP PGOOD Upper threshold VOUT rising 116 Hysteresis 8 VOUT falling 84 Hysteresis 8 % VREFIN PGOOD Lower threshold VPGOOD,L PGOOD voltage low impedance IPGOOD_SINK = 4 mA, VCC = 4.5 V IPGOOD,H PGOOD leakage high impedance VPGOOD = 5.5 V tPGd PGOOD startup delay time External tracking Time from EN = H to PGOOD high tPGHd PGOOD high delay time Rising edge tPGLd PGOOD low delay time Falling edge(2) DocID027688 Rev 4 0.338 V 1 µA 10 0.8 1 10 ms 1.2 ms µs 11/28 28 Electrical specifications PM8908 Table 5. Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit ENABLE Input logic high EN rising 2 V Input logic low EN falling 0.5 V EN input current VEN = 5 V 3 µA Mode current VMODE from GND to 2.4 V 15 µA EN IEN MODE IM SOFT-START tSS Soft-start time From EN = H to VOUT 2.4 ms td Delay soft-start time From EN = H to VOUT ramp starts 750 µs 1. Guaranteed by design, not subject to test. 2. Delay time not valid if the UVLO or EN shutdown events are occurring. 12/28 DocID027688 Rev 4 PM8908 5 Device description Device description The PM8908 is a high efficiency synchronous step-down monolithic switching regulator capable to deliver or sink the current. The power input voltage (VIN) can range from 1 V to 3.5 V, the signal input voltage (VCC) can range from 4.5 V to 5.5 V. The output voltage is regulated to the REFIN voltage which comes from an external reference voltage. The output voltage accuracy is better than ± 1% over the line, load and temperature. The PM8908 embeds low RDS(on) N-channel MOSFETs for both HS (high-side) and LS (lowside). The high-switching frequency selectable in two values - 600 kHz or 1 MHz and the small package allows very compact VR solutions. In the COT the tON is function of VIN, VOUT and switching frequency (fSW), as shown in Equation 1: Equation 1 V OUT t ON = ----------------------V IN ⋅ f SW The PM8908 features a full set of protections and output voltage monitoring: • Precise and accurate overcurrent limit (internally compensated against temperature variations) • Over and undervoltage protection • Overtemperature protection • Undervoltage lockout on analog supply (VCC) • Power Good open drain output easily provides real-time information about the output voltage. The dedicated ENABLE pin (EN) offers easy control on the power sequencing. Forcing the EN low, the device enters the shutdown state and absorbs a total quiescent current from VCC and VIN less than 15 µA. 5.1 Power section The PM8908 integrates two low RDS(on) N-channel MOSFETs as low-side and high-side switches, optimized for fast switching transition and high efficiency over the entire load range. The HS MOSFET drain is connected to the VIN pins (power input), the LS MOSFET source is connected to the PGND pins (power ground), and the HS MOSFET source and LS MOSFET drain are connected together and to the PHASE pins (see Figure 1 on page 4). The driving section is supplied from the VCC pins that assure the proper driving voltage over all the VIN range. DocID027688 Rev 4 13/28 28 Device description PM8908 To properly supply the power section is advised following: Caution: • Bypass VIN pins to PGND pins as close as possible to the IC package with high quality MLCC capacitors. • Connect the bootstrap capacitor (typically a 100 nF ceramic capacitor rated to stand VIN voltage) from the BOOT pin to the PHASE pin to supply the HS driver. Do not connect an external bootstrap diode. The IC already integrates an active bootstrap switch to charge the bootstrap capacitor, saving the cost of this external component. The PM8908 embodies the anti shoot-through and adaptive deadtime control to minimize low-side body diode conduction time and consequently to reduce power losses: 5.2 • When the gate driving voltage of the HS drops (to check high-side MOSFET turn-off), the LS MOSFET is suddenly switched on • When the gate driving voltage of the LS drops (to check low-side MOSFET turn-off), the HS MOSFET is suddenly switched on. Device configuration The PM8908 has a programming pin - MODE (pin 18) - which allows choosing the regulator switching frequency and the OCL threshold. This programming feature is performed by selecting the proper resistor, to be mounted between the pin 18 to ground, as summarized in Table 6. Table 6. Switching frequency and OCL (see Figure 1 on page 4) RM fSW [kHz] OCL (A) 47 kΩ 600 7.6 68 kΩ 600 5.4 100 kΩ 1000 5.4 Note: The MODE pin must not be left floating. 5.3 Startup and shutdown management The IC monitors the supply voltage on the VCC pin. Once VCC voltage is above the UVLO (undervoltage lockout) threshold and the EN pin is above the turn-on threshold: • If the IC is configured for tracking application (see Figure 2 on page 4), the output voltage is regulated to the REFIN voltage. In order to discriminate between the nontracking and the tracking, there is a delay time of 750 µs required between the EN or the VCC UVLO threshold and REFIN voltage. REFIN voltage must be applied within 9 ms (typ.) from the EN high (see Figure 5). • If the IC is configured for non-tracking application, the output voltage is regulated to the REFIN voltage, and the device provides a precise 2.4 ms soft-start time (see Figure 6). The power input (VIN) does not have a undervoltage protection function. 14/28 DocID027688 Rev 4 PM8908 Device description Figure 5. PM8908 turn-on (tracking startup) Vcc VCC UVLO EN EN thr REFIN 300mV td VOUT=REFIN PGOOD tPGd Figure 6. PM8908 turn-on (non-tracking startup) Vcc VCC UVLO EN EN thr REFIN 300mV tdc VOUT=REFIN PGOOD td tSS tPGHd DocID027688 Rev 4 15/28 28 Device description PM8908 Figure 7. PM8908 startup time diagram EN 0 Case 2 PM8908 will not perform SS by itself. Step transition observable at the end of the Grey region If REFIN>300mV, PM8908 will perform SS by itself in 2.4 ms (typ) Case 1 tdc= 550 us(typ) Case 3 PM8908 will not perform any SS by itself but will follow REFIN as it is observable on REFIN pin. REFIN need to have an external SS. td=750 us(typ) PM8908 Latches UVP 9 ms(typ) Soft-off The PM8908 implements the soft-off sequence turning off both the HS and LS MOSFETs and connecting the integrated discharge resistor (47 Ω) between the PHASE and PGND pin. The PM8908 begins the soft-off sequence, and remains in a latched state, if one of the following conditions occurs: • VCC voltage falls below UVLO threshold • OVP (overvoltage protection) • UVP (undervoltage protection) • EN pin is pulled low. The cycling VCC and EN the IC recover from the latched state with a new soft-start sequence. 5.4 Output voltage monitoring and protection The PM8908 monitors the output voltage status through the VOUT pin and compares the voltage on this pin with the REFIN voltage in order to provide over and undervoltage protection as well as the PGOOD signal. 5.4.1 Overvoltage protection Overvoltage protection is active as soon as the device is enabled, the VCC is above the respective undervoltage lockout level and REFIN is higher than 300 mV. 16/28 DocID027688 Rev 4 PM8908 Device description The protection is triggered when the voltage sensed on the VOUT pin rises over the OVP threshold and the device acts as follows: • De-asserts the PGOOD signal • The HS MOSFET is suddenly forced OFF • The LS MOSFET is turned on (to discharge the output and protect the load). When VOUT drops below the UVP threshold the LS MOSFET is turned off and the discharge resistor is on. If VOUT recrosses the UVP threshold, the LS is turned on again and the discharge resistor is off. In the overvoltage protection state the negative overcurrent limit (OCLN) is masked. This protection is latched, cycled EN or VCC to recover. 5.4.2 Undervoltage protection If VOUT falls below the UVP threshold for at least 256 µs the IC stops switching and starts a soft-off sequence. The device acts as follows: • De-asserts the PGOOD signal • The HS MOSFET and LS MOSFET are forced OFF • The discharge resistor is on. This protection is latched, cycled EN or VCC to recover. The UVP protection is enabled after the soft-start end. 5.4.3 Power Good (PGOOD) The PGOOD is an open drain output. During the startup, the PGOOD goes high after 1 ms from the threshold detected. The PGOOD is forced low, to communicate that the output voltage is no longer in regulation, if one of the following conditions is verified: 5.4.4 • The voltage of the VOUT pin exits from the PGOOD window • The device is disabled, EN is forced low • VCC voltage is below the UVLO threshold • Any protection is triggered (OVP, UVP, OTP). Overcurrent protection Overcurrent protection is active as soon as the device is enabled and VCC voltage is above the UVLO level. The overcurrent function protects the converter from a shorted output or overload by sensing the output current information across the low-side integrated MOSFET. • Positive OCL If the monitored current information is bigger than the overcurrent thresholds, an overcurrent event is detected. The IC delays the next tON until the current drops below the positive OCL limit. DocID027688 Rev 4 17/28 28 Device description PM8908 The maximum available load current, with the valley current limit technique, is equal to Equation 2: Equation 2 1 I LOADmax = IOCL + --- ⋅ ∆ I 2 It is the sum of the valley current limit plus the half of the inductor current ripple. During the overcurrent event the Vout drops until the UVP threshold, de-asserts the PGOOD pin and then enters into the latch state. • Negative OCL The negative OCL circuit operates when the converter is sinking the current from the output load. The IC trigs the next tON until the current drops below the negative OCL limit. During the overcurrent event the Vout goes up until the OVP threshold, de-asserts the PGOOD pin and then enters into the latch state. 5.4.5 Overtemperature protection It is recommended that the device never exceeds the maximum allowable junction temperature. This temperature increase is mainly caused by the total power dissipated from the integrated power MOSFETs. To avoid any damage to the device when reaching high temperature, the PM8908 implements a thermal shutdown feature: when the junction temperature reaches 145 °C the device turns off both MOSFETs. When the junction temperature drops to 135 °C, the device restarts with a new soft-start sequence. 18/28 DocID027688 Rev 4 PM8908 Application information 6 Application information 6.1 Output voltage setting The PM8908 integrates a 2 V internal reference (VREF), with the total accuracy of ± 1%. The output voltage, in non-tracking configuration, can be easily programmed connecting the R1 and R2 resistors as follows (see also Figure 8). • Connect the REFIN to the REF pin through the R1 resistor • Connect the REFIN pin to the GND through the R2 resistor Therefore, the output voltage setting is easily achieved using Equation 3 to select the value of the ROS resistor: Equation 3 V REF V OUT = -------------------------------1 + ( R1 ⁄ R2 ) Figure 8. Resistor divider configuration R2 6.2 9 REFIN 7 VREF R1 Droop setting In order to reduce the necessary output capacitance amount, the PM8908 can perform the load dependent behavior if the compensation network capacitor, CC, is avoided. The sensed current is used for reference voltage, in the PWM comparator inverting input. So doing, the programmed output voltage is: Equation 4 VOUT = V REFIN – V DROOP where: A CS ⋅ ILOAD V DROOP = -----------------------------------R DROOP ⋅ G M DocID027688 Rev 4 19/28 28 Application information PM8908 with: • RDROOP is the resistor between the COMP pin and the REF pin (see also Figure 9) • ILOAD is the output current • GM is the transconductance of the amplifier (1 mS) • ACS is the current sense gain (53 mV/A) Figure 9. Typical application with droop configuration VCC = 5 V RPGOOD 20 CVCC 6 VCC GND PGND VIN = 1 V to 3.5 V 4, 5 VIN CVIN 1, 2, 3 PM8908 19 17 18 REFIN 7 REF R1 CREF 16 CBOOT L PHASE COMP 11, 12, 13, 14, 15 VOUT COUT VOUT 10 8 CP 6.3 BOOT MODE 9 RM R2 PGOOD EN RDROOP Non-droop setting The advantage of a non-droop configuration is that the load regulation is flat. It can be implemented by connecting a resistor (RC) and a capacitor (CC) between the COMP pin and the REF pin (see also Figure 1 on page 4). 6.4 Inductor design The inductance value is defined by a compromise between the dynamic response time, the efficiency, the cost, and the size. The inductor must be calculated to maintain the ripple current (∆IL) between 20% and 30% of the maximum output current (typ.). The inductance value can be calculated with the following relationship: Equation 5 V IN – V OUT V OUT L = ------------------------------ ⋅ -------------F SW ⋅ ∆ I L VIN where fSW is the switching frequency, VIN is the input voltage, and VOUT is the output voltage. 20/28 DocID027688 Rev 4 PM8908 6.5 Application information Output capacitors The output capacitors are basic components to define the ripple voltage across the output and for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. During steady-state conditions, the output voltage ripple is influenced by both the ESR and the capacitive value of the output capacitors as follows: Equation 6 ∆ V OUT_ESR = ∆ I L ⋅ ESR Equation 7 1 ∆ V OUT_C = ∆ IL ⋅ --------------------------------------8 ⋅ C OUT ⋅ F SW where ∆IL is the inductor current ripple. In particular, the expression that defines ∆VOUT_C takes into consideration the output capacitor charge and discharge as a consequence of the inductor current ripple. 6.6 Input capacitors The input capacitor bank is designed considering, mainly, the input RMS current that depends on the output deliverable current (IOUT) and the duty cycle (D) for the regulation as follows: Equation 8 I rms = I OUT ⋅ D ⋅ ( 1 – D ) The equation reaches its maximum value, IOUT/2, with D = 0.5. The losses depend on the input capacitor ESR and, in the worst case, are: Equation 9 P = ESR ⋅ ( I OUT ⁄ 2 ) DocID027688 Rev 4 2 21/28 28 Application information 6.7 PM8908 Compensation network The PM8908 device implements a constant on-time control loop. The compensation network is shown in Figure 10. Figure 10. Compensation network 9 REFIN 7 REF COMP 8 CP CF CREF RF The following procedure shall be followed in order to calculate the best network external components value. • Select RF value in order to obtain the desired closed loop regulator bandwidth according to Equation 10: Equation 10 R F = 2 π ⋅ f T ⋅ C OUT  R CS  ESR ⋅ C OUT f ⋅ 1 + 2π ⋅ T ⋅ f gM  5 1 − 2 π ⋅ T ⋅ ESR ⋅ C OUT  5        where: • – fT is the crossover frequency, it should be less than about 1/10 of the switching frequency – RCS = 53 mΩ Select CF according to Equation 11: Equation 11 C • F ≥ 1 f 2π ⋅ T ⋅ R 5 F Select CP according to Equation 12: Equation 12 CP = • 22/28 ESR ⋅ C OUT f   R C ⋅  1 − 2 π ⋅ T ⋅ ESR ⋅ C OUT  5   Check the phase margin obtained and repeat the whole procedure if necessary. DocID027688 Rev 4 PM8908 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DocID027688 Rev 4 23/28 28 Package information 7.1 PM8908 QFN20 package information Figure 11. QFN20 3.5 x 4 x 1.0 mm package outline ". 24/28 DocID027688 Rev 4 PM8908 Package information Table 7. QFN20 3.5 x 4 x 1.0 mm package mechanical data Dimensions (mm) Symbol Min. Typ. Max. A 0.90 0.95 1.00 A1 0.00 0.02 0.05 A3 0.152 b 0.18 0.25 0.30 D 3.4 3.5 3.6 D2 2.00 2.10 2.20 E 3.9 4.0 4.1 E2 2.50 2.60 2.70 e 0.50 L 0.35 K 0.20 0.40 0.45 Figure 12. Recommended footprint ". DocID027688 Rev 4 25/28 28 Package information PM8908 Figure 13. QFN20 3.5 x 4 x 1.0 mm tape and reel ". Figure 14. QFN20 3.5 x 4 x 1.0 mm winding direction 26/28 DocID027688 Rev 4 PM8908 8 Revision history Revision history Table 8. Document revision history Date Revision Changes 30-Mar-2015 1 Initial release. 22-Oct-2015 2 – Added footnote 2 to Table 4. – Added minimum and maximum dimension values for symbols D and E in Table 7. 09-Nov-2015 3 First public release. 25-Jul-2017 4 Updated: ACS, RDS, RBSS and VPGOOD,L values in Table 5. DocID027688 Rev 4 27/28 28 PM8908 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 28/28 DocID027688 Rev 4