PSD834F3VA-70JT

PSD8XXFX Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V Features ■ ■ Flash in-system programmable (ISP) peripheral for 8-bit MCUs Dual bank Flash memories – Up to 2 Mbit of primary Flash memory (8 uniform sectors, 32K x8) – Up to 256 Kbit secondary Flash memory (4 uniform sectors) – Concurrent operation: read from one memory while erasing and writing the other Up to 256 Kbit SRAM 27 reconfigurable I/Oports Enhanced JTAG serial port PLD with macrocells – Over 3000 gates of PLD: CPLD and DPLD – CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs) – DPLD - user defined internal chip select decoding 27 individually configurable I/O port pins They can be used for the following functions: – MCU I/Os – PLD I/Os – Latched MCU address output – Special function I/Os. – 16 of the I/O ports may be configured as open-drain outputs. In-system programming (ISP) with JTAG – Built-in JTAG compliant serial port allows full-chip in-system programmability – Efficient manufacturing allow easy product testing and programming – Use low cost FlashLINK cable with PC Page register – Internal page register that can be used to expand the microcontroller address space by a factor of 256 ■ ■ PQFP52 (M) ■ ■ ■ ■ PLCC52 (J) TQFP64 (U) ■ Programmable power management Packages are ECOPACK® Device summary Part number PSD813F2 PSD813F4 PSD813F5 PSD8XXFX PSD833F2 PSD834F2 PSD853F2 PSD854F2 Table 1. Reference ■ ■ May 2009 Doc ID 7833 Rev 7 1/128 www.st.com 1 Contents PSD8XXFX Contents 1 2 3 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 5 6 Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PSD register description and address offset . . . . . . . . . . . . . . . . . . . . 24 Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 6.2 6.3 Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Description of primary Flash memory and secondary Flash memory . . . 27 Memory block select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3.1 6.3.2 Ready/Busy (PC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Read Primary Flash Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Read Memory Sector Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Reading the Erase/Program Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Data Polling flag (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2/128 Doc ID 7833 Rev 7 PSD8XXFX Contents 7.8 7.9 7.10 Toggle flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Error flag (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Erase timeout flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 8.2 8.3 Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x, PSD854F2x) . . 36 9 Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1 9.2 9.3 9.4 Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.1 10.2 10.3 Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Reset (RESET) signal (on the PSD83xF2 and PSD85xF2) . . . . . . . . . . . 41 11 12 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.1 12.2 12.3 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Memory select configuration for MCUs with separate program and data spaces 43 Configuration modes for MCUs with separate program and data spaces 44 12.3.1 12.3.2 Separate Space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Combined Space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 13 14 Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 14.1 14.2 14.3 The Turbo Bit in PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Doc ID 7833 Rev 7 3/128 Contents PSD8XXFX 14.4 14.5 14.6 14.7 14.8 14.9 Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Loading and reading the Output macrocells (OMC) . . . . . . . . . . . . . . . . . 54 The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15 MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 PSD interface to a multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . 60 PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 60 Data Byte Enable reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 16 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Data port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 16.10 Port configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16.11 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16.12 Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16.13 Drive Select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16.14 Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16.15 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16.16 Data Out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4/128 Doc ID 7833 Rev 7 PSD8XXFX Contents 16.17 OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16.18 Input macro (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16.19 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 16.20 Ports A and B – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . 75 16.21 Port C – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 16.22 Port D – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 16.23 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.1 17.2 17.3 17.4 17.5 17.6 17.7 Automatic Power-down (APD) Unit and Power-down mode . . . . . . . . . . . 80 For users of the HC11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 PSD Chip Select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18 Reset timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . . . 85 18.1 18.2 18.3 18.4 Power-up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 I/O pin, register and PLD status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . 85 Reset of Flash memory erase and program cycles (on the PSD834Fx) . 85 19 Programming in-circuit using the JTAG serial interface . . . . . . . . . . . 87 19.1 19.2 19.3 Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20 21 22 23 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 AC/DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Doc ID 7833 Rev 7 5/128 Contents PSD8XXFX 24 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Appendix A PQFP52 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Appendix B PLCC52 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Appendix C TQFP64 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6/128 Doc ID 7833 Rev 7 PSD8XXFX List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Product range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PLCC52 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 JTAG SIgnals on port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Methods for programming different functional blocks of the PSD. . . . . . . . . . . . . . . . . . . . 22 I/O port latched address output assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Register address offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Sector Protection/Security Bit definition – Flash Protection register. . . . . . . . . . . . . . . . . . 41 Sector Protection/Security Bit definition – PSD/EE Protection register . . . . . . . . . . . . . . . 41 VM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DPLD and CPLD inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Output macrocell port and data bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 MCUs and their control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8-bit data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 80C251 configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Port operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 I/O port Latched address output assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Port configuration registers (PCR)t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Port Pin Direction Control, Output Enable P.T. not defined . . . . . . . . . . . . . . . . . . . . . . . . 73 Port Pin Direction Control, Output Enable P.T. defined . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Port Direction assignment example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Drive register pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Power-down mode’s effect on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 PSD timing and standby current during Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . 81 Power Management mode registers PMMR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Power Management mode registers PMMR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 APD counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Status during Power-on reset, Warm reset and Power-down mode. . . . . . . . . . . . . . . . . . 86 JTAG port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 JTAG Enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Example of PSD typical power calculation at VCC=5.0 V (Turbo mode on) . . . . . . . . . . . . 93 Example of PSD typical power calculation at VCC = 5.0 V (Turbo mode off) . . . . . . . . . . . 94 Operating conditions (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Operating conditions (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 AC signal letters for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 AC signal behavior symbols for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 DC characteristics (5 V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DC Characteristics (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 CPLD combinatorial timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Doc ID 7833 Rev 7 7/128 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. PSD8XXFX CPLD combinatorial timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 CPLD macrocell Synchronous clock mode timing (5 V devices) . . . . . . . . . . . . . . . . . . . 101 CPLD macrocell synchronous clock mode timing (3 V devices). . . . . . . . . . . . . . . . . . . . 102 CPLD macrocell asynchronous clock mode timing (5 V devices). . . . . . . . . . . . . . . . . . . 103 CPLD macrocell Asynchronous clock mode timing (3 V devices) . . . . . . . . . . . . . . . . . . 104 Input macrocell timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 input macrocell timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 READ timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 READ timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 WRITE timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 WRITE timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Program, WRITE and Erase times (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Program, WRITE and Erase times (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Port A Peripheral Data mode READ timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . 111 Port A Peripheral Data mode READ timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . 112 Port A Peripheral Data mode WRITE timing (5 V devices). . . . . . . . . . . . . . . . . . . . . . . . 112 Port A Peripheral Data mode WRITE timing (3 V devices). . . . . . . . . . . . . . . . . . . . . . . . 113 Reset (RESET) timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Reset (RESET) timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 ISC timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 ISC timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Power-down timing (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Power-down timing (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 PQFP52 - 52-pin plastic quad flat package mechanical dimensions . . . . . . . . . . . . . . . . 117 PLCC52-52-lead plastic lead chip carrier mechanical dimensions . . . . . . . . . . . . . . . . . . 118 TQFP64 - 64-lead thin quad flatpack, package mechanical data . . . . . . . . . . . . . . . . . . . 119 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 PQFP52 connections (see Features) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 PLCC52 connections (see Features) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 TQFP64 connections (see Features) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8/128 Doc ID 7833 Rev 7 PSD8XXFX List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. PQFP52 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PLCC52 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TQFP64 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PSD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PSDsoft Express development tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Data Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Priority level of memory and I/O components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8031 memory modules – separate space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8031 memory modules – combined space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PLD diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DPLD logic array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Macrocell and I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 CPLD Output macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Input macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Handshaking communication using input macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 An example of a typical 8-bit multiplexed bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 An example of a typical 8-bit non-multiplexed bus interface. . . . . . . . . . . . . . . . . . . . . . . . 61 Interfacing the PSD with an 80C31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Interfacing the PSD with the 80C251, with One READ input . . . . . . . . . . . . . . . . . . . . . . . 63 Interfacing the PSD with the 80C251, with RD and PSEN inputs. . . . . . . . . . . . . . . . . . . . 64 Interfacing the PSD with the 80C51X, 8-bit data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Interfacing the PSD with a 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 General I/O port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Port A and port B structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Port C structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Port D structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Port D external Chip Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 APD unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Enable Power-down flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PLD ICC /frequency consumption (5 V range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PLD ICC /frequency consumption (3 V range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Switching waveforms – key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Input to output disable / enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Synchronous clock mode timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Asynchronous Reset / Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Asynchronous Clock mode Timing (product term clock). . . . . . . . . . . . . . . . . . . . . . . . . . 103 Input macrocell timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Peripheral I/O READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Peripheral I/O WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Doc ID 7833 Rev 7 9/128 List of figures Figure 49. Figure 50. Figure 51. Figure 52. PSD8XXFX ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 PQFP52 - 52-pin plastic quad flat package mechanical drawing . . . . . . . . . . . . . . . . . . . 117 PLCC52 - 52-lead plastic lead chip carrier package mechanical drawing . . . . . . . . . . . . 118 TQFP64 - 64-lead thin quad flatpack, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10/128 Doc ID 7833 Rev 7 PSD8XXFX Summary description 1 Summary description The PSD8XXFX family of memory systems for microcontrollers (MCUs) brings in-systemprogrammability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. Table 2 summarizes all the devices. The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices. The PSD device includes a JTAG serial programming interface, to allow in-system programming (ISP) of the entire device. This feature reduces development time, simplifies the manufacturing flow, and dramatically lowers the cost of field upgrades. Using ST’s special Fast-JTAG programming, a design can be rapidly programmed into the PSD in as little as seven seconds. The innovative PSD8XXFX family solves key problems faced by designers when managing discrete Flash memory devices, such as: ● ● ● First-time in-system programming (ISP) Complex address decoding Simultaneous read and write to the device. The JTAG Serial Interface block allows in-system programming (ISP), and eliminates the need for an external Boot EPROM, or an external programmer. To simplify Flash memory updates, program execution is performed from a secondary Flash memory while the primary Flash memory is being updated. This solution avoids the complicated hardware and software overhead necessary to implement IAP. ST makes available a software development tool, PSDsoft™ Express, that generates ANSIC compliant code for use with your target MCU. This code allows you to manipulate the nonvolatile memory (NVM) within the PSD. Code examples are also provided for: ● ● ● Flash memory IAP via the UART of the host MCU Memory paging to execute code across several PSD memory pages Loading, reading, and manipulation of PSD macrocells by the MCU. Table 2. Part Product range Primary Flash memory (8 sectors) Secondary Flash memory (4 sectors) 256 Kbit 256 Kbit none 256 Kbit 256 Kbit 16 Kbit none none 64 Kbit 64 Kbit SRAM I/O ports 27 27 27 27 27 Number of macrocells Input 24 24 24 24 24 Output 16 16 16 16 16 Serial ISP JTAG/ISC port yes yes yes yes yes Turbo mode yes yes yes yes yes number(1) PSD813F2 PSD813F4 PSD813F5 PSD833F2 PSD834F2 1 Mbit 1 Mbit 1 Mbit 1 Mbit 2 Mbit Doc ID 7833 Rev 7 11/128 Summary description Table 2. Product range (continued) (1) PSD8XXFX Part number Primary Flash memory (8 sectors) Secondary Flash memory (4 sectors) 256 Kbit 256 Kbit SRAM I/O ports 27 27 Number of macrocells Input Output 16 16 Serial ISP JTAG/ISC port yes yes Turbo mode yes yes PSD853F2 PSD854F2 1 Mbit 2 Mbit 256 Kbit 256 Kbit 24 24 1. All products support: JTAG serial ISP, MCU parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power Management Unit (PMU), Automatic Power-down (APD) Figure 1. PQFP52 connections PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 6 PC4 7 VCC 8 GND 9 PC3 10 PC2 11 PC1 12 PC0 13 40 CNTLO 41 RESET 43 CNTL1 42 CNTL2 46 GND 52 PB0 51 PB1 50 PB2 49 PB3 48 PB4 47 PB5 45 PB6 44 PB7 39 AD15 38 AD14 37 AD13 36 AD12 35 AD11 34 AD10 33 AD9 32 AD8 31 VCC 30 AD7 29 AD6 28 AD5 27 AD4 PA7 14 PA6 15 PA5 16 PA4 17 PA3 18 GND 19 PA2 20 PA1 21 PA0 22 AD0 23 AD1 24 AD2 25 AD3 26 AI02858 12/128 Doc ID 7833 Rev 7 PSD8XXFX Figure 2. PLCC52 connections CNTL2 RESET 48 CNTL1 CNTL0 47 Summary description PB0 PB1 PB2 PB3 PB4 PB5 GND PB6 52 PB7 51 4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 5 3 2 50 49 6 1 PD2 PD1 PD0 PC7 PC6 PC5 PC4 VCC GND PC3 PC2 PC1 PC0 46 45 44 43 42 41 40 39 38 37 36 35 34 22 23 24 25 26 27 28 29 31 32 30 33 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 VCC AD7 AD6 AD5 AD4 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 AD1 AD2 GND AD0 AD3 AI02857 Doc ID 7833 Rev 7 13/128 Summary description Figure 3. TQFP64 connections 50 RESET 52 CNTL1 51 CNTL2 56 GND 55 GND 62 PB0 61 PB1 60 PB2 59 PB3 58 PB4 57 PB5 54 PB6 53 PB7 64 NC 63 NC 49 NC PSD8XXFX PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 6 PC4 7 VCC 8 VCC 9 GND 10 GND 11 PC3 12 PC2 13 PC1 14 PC0 15 NC 16 48 CNTL0 47 AD15 46 AD14 45 AD13 44 AD12 43 AD11 42 AD10 41 AD9 40 AD8 39 VCC 38 VCC 37 AD7 36 AD6 35 AD5 34 AD4 33 AD3 NC 17 NC 18 PA7 19 PA6 20 PA5 21 PA4 22 PA3 23 GND 24 GND 25 PA2 26 PA1 27 PA0 28 AD0 29 AD1 30 ND 31 AD2 32 AI09645b 14/128 Doc ID 7833 Rev 7 PSD8XXFX Pin description 2 Table 3. Pin name Pin description PLCC52 pin description (1) Pin Type Description This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port. If your MCU does not have a multiplexed address/data bus, or you are using an 80C251 in page mode, connect A0-A7 to this port. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect A8-A15 to this port. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port. If you are using an 80C251 in page mode, connect AD8-AD15 to this port. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. The following control signals can be connected to this port, based on your MCU: WR – active low Write Strobe input. R_W – active high READ/active low write input. This port is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. The following control signals can be connected to this port, based on your MCU: RD – active low Read Strobe input. E – E clock input. DS – active low Data Strobe input. PSEN – connect PSEN to this port when it is being used as an active low READ signal. For example, when the 80C251 outputs more than 16 address bits, PSEN is actually the READ signal. This port is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. This port can be used to input the PSEN (Program Select Enable) signal from any MCU that uses this signal for code exclusively. If your MCU does not output a Program Select Enable signal, this port can be used as a generic input. This port is connected to the PLDs. Resets I/O ports, PLD macrocells and some of the Configuration registers. Must be low at Power-up. ADIO0-7 30-37 I/O ADIO8-15 39-46 I/O CNTL0 47 I CNTL1 50 I CNTL2 49 I Reset 48 I Doc ID 7833 Rev 7 15/128 Pin description Table 3. Pin name PSD8XXFX PLCC52 pin description (1) (continued) Pin Type Description These pins make up port A. These port pins are configurable and can have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellAB0-7) outputs. Inputs to the PLDs. Latched address outputs (see Table 7). Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA in burst mode. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs. D0/A16-D3/A19 in M37702M2 mode. Peripheral I/O mode. Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However, PA4-PA7 can be configured as CMOS or Open Drain outputs. These pins make up port B. These port pins are configurable and can have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs. Inputs to the PLDs. Latched address outputs (see Table 7). Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However, PB4-PB7 can be configured as CMOS or Open Drain outputs. PC0 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC0) output. Input to the PLDs. TMS input(2) for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. PC1 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC1) output. Input to the PLDs. TCK input(2) for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. PC2 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC2) output. Input to the PLDs. This pin can be configured as a CMOS or Open Drain output. PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 29 28 27 25 24 23 22 21 I/O PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 7 6 5 4 3 2 52 51 I/O PC0 20 I/O PC1 19 I/O PC2 18 I/O 16/128 Doc ID 7833 Rev 7 PSD8XXFX Table 3. Pin name Pin description PLCC52 pin description (1) (continued) Pin Type Description PC3 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC3) output. Input to the PLDs. TSTAT output(2) for the JTAG Serial Interface. Ready/Busy output for parallel in-system programming (ISP). This pin can be configured as a CMOS or Open Drain output. PC4 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC4) output. Input to the PLDs. TERR output(2) for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. PC5 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC5) output. Input to the PLDs. TDI input(2) for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. PC6 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC6) output. Input to the PLDs. TDO output(2) for the JTAG Serial Interface. This pin can be configured as a CMOS or Open Drain output. PC7 pin of port C. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellBC7) output. Input to the PLDs. DBE – active low Data Byte Enable input from 68HC912 type MCUs. This pin can be configured as a CMOS or Open Drain output. PD0 pin of port D. This port pin can be configured to have the following functions: ALE/AS input latches address output from the MCU. MCU I/O – write or read from a standard output or input port. Input to the PLDs. CPLD output (External Chip Select). PD1 pin of port D. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Input to the PLDs. CPLD output (External Chip Select). CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and the CPLD AND Array. PC3 17 I/O PC4 14 I/O PC5 13 I/O PC6 12 I/O PC7 11 I/O PD0 10 I/O PD1 9 I/O Doc ID 7833 Rev 7 17/128 Pin description Table 3. Pin name PSD8XXFX PLCC52 pin description (1) (continued) Pin Type Description PD2 pin of port D. This port pin can be configured to have the following functions: MCU I/O - write to or read from a standard output or input port. Input to the PLDs. CPLD output (External Chip Select). PSD Chip Select input (CSI). When low, the MCU can access the PSD memory and I/O. When high, the PSD memory blocks are disabled to conserve power. Supply voltage Ground pins PD2 8 I/O VCC GND 15, 38 1, 16, 26 1. The pin numbers in this table are for the PLCC package only. See the package information from Table 73 onwards, for pin numbers on other package types. 2. These functions can be multiplexed with other functions. 18/128 Doc ID 7833 Rev 7 Figure 4. PSD8XXFX ADDRESS/DATA/CONTROL BUS PLD INPUT BUS PAGE REGISTER EMBEDDED ALGORITHM 8 SECTORS 1 OR 2 MBIT PRIMARY FLASH MEMORY PSD block diagram 8 CNTL0, CNTL1, CNTL2 SECTOR SELECTS FLASH DECODE PLD (DPLD) 73 SECTOR SELECTS SRAM SELECT PERIP I/O MODE SELECTS CSIOP ADIO PORT 73 FLASH ISP CPLD (CPLD) 3 EXT CS TO PORT D 16 OUTPUT MACROCELLS PORT A ,B & C 24 INPUT MACROCELLS CLKIN PORT A ,B & C RUNTIME CONTROL AND I/O REGISTERS 256 KBIT SRAM PROG. MCU BUS INTRF. 256 KBIT SECONDARY NON-VOLATILE MEMORY (BOOT OR DATA) 4 SECTORS PROG. PORT PORT A PA0 – PA7 AD0 – AD15 Doc ID 7833 Rev 7 GLOBAL CONFIG. & SECURITY CLKIN MACROCELL FEEDBACK OR PORT INPUT CLKIN (PD1) PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PROG. PORT PORT B PB0 – PB7 PROG. PORT PORT C PC0 – PC7 PROG. PORT PORT D PD0 – PD2 Pin description AI02861f 19/128 PSD architectural overview PSD8XXFX 3 PSD architectural overview PSD devices contain several major functional blocks. Figure 4 shows the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. 3.1 Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in Section 6.1: Memory blocks. The 1 Mbit or 2 Mbit (128K x 8, or 256K x 8) Flash memory is the primary memory of the PSD. It is divided into 8 equally-sized sectors that are individually selectable. The optional 256 Kbit (32K x 8) secondary Flash memory is divided into 4 equally-sized sectors. Each sector is individually selectable. The optional SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. Each sector of memory can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time. 3.2 Page register The 8-bit Page register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page register can also be used to change the address mapping of sectors of the Flash memories into different memory spaces for IAP. 3.3 PLDs The device contains two PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 4, each optimized for a different function. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The DPLD is used to decode addresses and to generate Sector Select signals for the PSD internal memory and registers. The DPLD has combinatorial outputs. The CPLD has 16 Output macrocells (OMC) and 3 combinatorial outputs. The PSD also has 24 input macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD input bus and are differentiated by their output destinations, number of product terms, and macrocells. The PLDs consume minimal power. The speed and power consumption of the PLD is controlled by the Turbo Bit in PMMR0 and other bits in the PMMR2. These registers are set by the MCU at run-time. There is a slight penalty to PLD propagation time when invoking the power management features. 20/128 Doc ID 7833 Rev 7 PSD8XXFX PSD architectural overview 3.4 I/O ports The PSD has 27 individually configurable I/O pins distributed over the four ports (Port A, B, C, and D). Each I/O pin can be individually configured for different functions. ports can be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using multiplexed address/data buses. The JTAG pins can be enabled on port C for in-system programming (ISP). Ports A and B can also be configured as a data port for a non-multiplexed bus. 3.5 MCU bus interface PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU control signals, which are also used as inputs to the PLDs. For examples, please see Section 15.4: MCU bus interface examples. Table 4. PLD I/O Name Decode PLD (DPLD) Complex PLD (CPLD) 73 73 Inputs 17 19 Outputs Product terms 42 140 3.6 JTAG port In-system programming (ISP) can be performed through the JTAG signals on port C. This serial interface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on port C. Table 5 indicates the JTAG pin assignments. 3.7 In-system programming (ISP) Using the JTAG signals on port C, the entire PSD device can be programmed or erased without the use of the MCU. The primary Flash memory can also be programmed in-system by the MCU executing the programming algorithms out of the secondary memory, or SRAM. The secondary memory can be programmed the same way by executing out of the primary Flash memory. The PLD or other PSD configuration blocks can be programmed through the JTAG port or a device programmer. Table 6 indicates which programming methods can program different functional blocks of the PSD. 3.8 Power management unit (PMU) The power management unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD unit has a Power-down mode that helps reduce power consumption. Doc ID 7833 Rev 7 21/128 PSD architectural overview PSD8XXFX The PSD also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches its outputs and goes to sleep until the next transition on its inputs. Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD to reduce power consumption. Please see Section 17: Power management for more details. Table 5. JTAG SIgnals on port C Port C pins PC0 PC1 PC3 PC4 PC5 PC6 TMS TCK TSTAT TERR TDI TDO JTAG signal Table 6. Methods for programming different functional blocks of the PSD Functional block JTAG programming Yes Yes Yes Yes Device programmer Yes Yes Yes Yes Yes Yes No No IAP Primary Flash memory Secondary Flash memory PLD array (DPLD and CPLD) PSD configuration 22/128 Doc ID 7833 Rev 7 PSD8XXFX Development system 4 Development system The PSD8XXFX family is supported by PSDsoft Express, a Windows-based software development tool. A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 5. PSDsoft Express is available from our web site (the address is given on the back page of this data sheet) or other distribution channels. PSDsoft Express directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/representative, or directly from our web site using a credit card. The PSD is also supported by third party device programmers. See our web site for the current list. Figure 5. PSDsoft Express development tool PSDabel PLD DESCRIPTION MODIFY ABEL TEMPLATE FILE OR GENERATE NEW FILE PSD Configuration CONFIGURE MCU BUS INTERFACE AND OTHER PSD ATTRIBUTES PSD TOOLS GENERATE C CODE SPECIFIC TO PSD FUNCTIONS PSD Fitter LOGIC SYNTHESIS AND FITTING ADDRESS TRANSLATION AND MEMORY MAPPING FIRMWARE HEX OR S-RECORD FORMAT USER'S CHOICE OF MICROCONTROLLER COMPILER/LINKER *.OBJ FILE PSD Simulator PSDsilos III DEVICE SIMULATION (OPTIONAL) PSD Programmer PSDPro, or FlashLINK (JTAG) *.OBJ AND *.SVF FILES AVAILABLE FOR 3rd PARTY PROGRAMMERS (CONVENTIONAL or JTAG-ISC) AI04918 Doc ID 7833 Rev 7 23/128 PSD register description and address offset PSD8XXFX 5 PSD register description and address offset Table 7 shows the offset addresses to the PSD registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal PSD registers. Table 8 provides brief descriptions of the registers in CSIOP space. The following section gives a more detailed description. Table 7. I/O port latched address output assignments(1)(2) Port A MCU Port A (3:0) 8051XA (8-bit) 80C251 (page mode) All other 8-bit multiplexed 8-bit non-multiplexed bus N/A N/A Address a3-a0 N/A Port A (7:4) Address a7-a4 N/A Address a7-a4 N/A Port B (3:0) Address a11-a8 Address a11-a8 Address a3-a0 Address a3-a0 Port B (7:4) N/A Address a15a12 Address a7-a4 Address a7-a4 Port B 1. See Section 16: I/O ports, on how to enable the Latched Address Output function. 2. N/A = Not Applicable Table 8. Register name Data In Control Data Out Direction Drive Select Input macrocell Enable Out Output macrocells AB Output macrocells BC Register address offset Port A Port B Port C Port D 00 02 04 06 08 01 03 05 07 09 12 14 16 13 15 17 10 11 Other (1) Description Reads port pin as input, MCU I/O input mode Selects mode between MCU I/O or Address Out Stores data for output to port pins, MCU I/O output mode Configures port pin as input or output Configures port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins. Reads input macrocells 0A 0C 0B 0D 18 1A 1B Reads the status of the output enable to the I/O port driver READ – reads output of macrocells AB WRITE – loads macrocell flip-flops READ – reads output of macrocells BC WRITE – loads macrocell flip-flops 20 20 21 21 24/128 Doc ID 7833 Rev 7 PSD8XXFX Table 8. Register name Mask macrocells AB Mask macrocells BC Primary Flash Protection Secondary Flash memory Protection JTAG Enable PMMR0 PMMR2 Page VM 1. Other registers that are not part of the I/O ports. PSD register description and address offset Register address offset (continued) Port A Port B Port C Port D Other (1) Description Blocks writing to the Output macrocells AB Blocks writing to the Output macrocells BC 22 22 23 23 C0 Read only – Primary Flash Sector Protection Read only – PSD Security and Secondary Flash memory Sector Protection Enables JTAG port Power Management register 0 Power Management register 2 Page register Places PSD memory areas in program and/or data space on an individual basis. C2 C7 B0 B4 E0 E2 Doc ID 7833 Rev 7 25/128 Detailed operation PSD8XXFX 6 Detailed operation As shown in Figure 4, the PSD consists of six major types of functional blocks: ● ● ● ● ● ● Memory blocks PLD blocks MCU bus interface I/O ports Power management unit (PMU) JTAG interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. 6.1 Memory blocks The PSD has the following memory blocks: ● ● ● Primary Flash memory Optional Secondary Flash memory Optional SRAM The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are user-defined in PSDsoft Express. Table 9. Memory block size and organization Primary Flash memory Sector number Sector select signal FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 8 sectors 64 4 sectors 256 Secondary Flash memory Sector size (Kbytes) 16 16 16 16 Sector select signal CSBOOT0 CSBOOT1 CSBOOT2 CSBOOT3 SRAM SRAM select signal RS0 Sector size (Kbytes) 32 32 32 32 32 32 32 32 512 SRAM size (Kbytes) 256 0 1 2 3 4 5 6 7 Total 26/128 Doc ID 7833 Rev 7 PSD8XXFX Detailed operation 6.2 Description of primary Flash memory and secondary Flash memory The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors. Each sector of either memory block can be separately protected from Program and Erase cycles. Flash memory may be erased on a sector-by-sector basis. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading. During a program or erase cycle in Flash memory, the status can be output on Ready/Busy (PC3). This pin is set up using PSDsoft Express Configuration. 6.3 Memory block select signals The DPLD generates the Select signals for all the internal memory blocks (see Section 14: PLDS). Each of the eight sectors of the primary Flash memory has a Select signal (FS0FS7) which can contain up to three product terms. Each of the four sectors of the secondary Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in different areas of system memory. When using a MCU with separate program and data space, these flexible Select signals allow dynamic re-mapping of sectors from one memory space to the other. 6.3.1 Ready/Busy (PC3) This signal can be used to output the Ready/Busy status of the PSD. The output on Ready/Busy (PC3) is a 0 (Busy) when Flash memory is being written to, or when Flash memory is being erased. The output is a 1 (Ready) when no WRITE or Erase cycle is in progress. 6.3.2 Memory operation The primary Flash memory and secondary Flash memory are addressed through the MCU bus interface. The MCU can access these memories in one of two ways: ● ● The MCU can execute a typical bus WRITE or READ operation just as it would if accessing a RAM or ROM device using standard bus cycles. The MCU can execute a specific instruction that consists of several WRITE and READ operations. This involves writing specific data patterns to special addresses within the Flash memory to invoke an embedded algorithm. These instructions are summarized in Table 10. Typically, the MCU can read Flash memory using READ operations, just as it would read a ROM device. However, Flash memory can only be altered using specific Erase and Program instructions. For example, the MCU cannot write a single byte directly to Flash memory as it would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a Program instruction, then test the status of the Program cycle. This status test is achieved by a READ operation or polling Ready/Busy (PC3). Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID). Doc ID 7833 Rev 7 27/128 Detailed operation Table 10. Instructions (1)(2)(3) FS0-FS7 or CSBOOT0CSBOOT3 (4) PSD8XXFX Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 READ(5) Read Main Flash ID(6) Read Sector Protection(6)(7) (8) 1 1 “READ” RD @ RA AAh@ X555h AAh@ X555h AAh@ X555h AAh@ X555h AAh@ X555h B0h@ XXXXh 30h@ XXXXh F0h@ XXXXh AAh@ X555h A0h@ XXXXh 90h@ XXXXh 55h@ XAAAh PD@ PA 00h@ XXXXh 20h@ X555h 55h@ XAAAh 55h@ XAAAh 55h@ XAAAh 55h@ XAAAh 55h@ XAAAh 90h@ X555h 90h@ X555h A0h@ X555h 80h@ X555h 80h@ X555h Read identifier (A6,A1,A0 = 0,0,1) Read identifier (A6,A1,A0 = 0,1,0) PD@ PA AAh@ X555h AAh@ X555h 55h@ XAAAh 55h@ XAAAh 30h@ SA 10h@ X555h 30h7@ next SA 1 Program a Flash Byte(8) Flash Sector Erase(9)(8) Flash Bulk Erase(8) Suspend Sector Erase(10) Resume Sector Erase(11) Reset(6) Unlock Bypass Unlock Bypass Program(12) Unlock Bypass Reset(13) 1 1 1 1 1 1 1 1 1 1. All bus cycles are WRITE bus cycles, except the ones with the “READ” label 2. All values are in hexadecimal: X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses RA = Address of the memory location to be read RD = Data read from location RA during the READ cycle PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0). PA is an even address for PSD in word programming mode. PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR, CNTL0) SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be erased, or verified, must be Active (high). 3. Only address bits A11-A0 are used in instruction decoding. 4. Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active high, and are defined in PSDsoft Express. 5. No Unlock or instruction cycles are required when the device is in the READ mode 6. The Reset instruction is required to return to the READ mode after reading the Flash ID, or after reading the Sector Protection Status, or if the Error flag bit (DQ5/DQ13) goes high. 7. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0)=(1,0) 28/128 Doc ID 7833 Rev 7 PSD8XXFX Detailed operation 8. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory. 9. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80 µs. 10. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle. 11. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 12. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 13. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode. Doc ID 7833 Rev 7 29/128 Instructions PSD8XXFX 7 Instructions An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the timeout period. Some instructions are structured to include READ operations after the initial WRITE operations. The instruction must be followed exactly. Any invalid combination of instruction bytes or timeout between two consecutive bytes while addressing Flash memory resets the device logic into READ mode (Flash memory is read like a ROM device). The PSD supports the instructions summarized in Table 10: Flash memory: ● ● ● ● ● ● ● Erase memory by chip or sector Suspend or resume sector erase Program a Byte Reset to READ mode Read primary Flash Identifier value Read Sector Protection Status Bypass (on the PSD833F2, PSD834F2, PSD853F2 and PSD854F2) These instructions are detailed in Table 10. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cycles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cycle. Address signals A15-A12 are Don’t Care during the instruction WRITE cycles. However, the appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) must be selected. The primary and secondary Flash memories have the same instruction set (except for Read Primary Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is selected if any one of Sector Select (FS0-FS7) is high, and the secondary Flash memory is selected if any one of Sector Select (CSBOOT0-CSBOOT3) is high. 7.1 Power-up mode The PSD internal logic is reset upon Power-up to the READ mode. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must be held low, and Write Strobe (WR, CNTL0) high, during Power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of Write Strobe (WR, CNTL0). Any WRITE cycle initiation is locked when VCC is below VLKO. 7.2 READ Under typical conditions, the MCU may read the primary Flash memory or the secondary Flash memory using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a program or erase 30/128 Doc ID 7833 Rev 7 PSD8XXFX Instructions cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these READ functions. 7.3 Read memory contents Primary Flash memory and secondary Flash memory are placed in the READ mode after Power-up, chip reset, or a Reset Flash instruction (see Table 10). The MCU can read the memory contents of the primary Flash memory or the secondary Flash memory by using READ operations any time the READ operation is not part of an instruction. 7.4 Read Primary Flash Identifier The primary Flash memory identifier is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 10). During the READ operation, address bits A6, A1, and A0 must be '0,0,1,' respectively, and the appropriate Sector Select (FS0-FS7) must be high. The identifier for the PSD813F2/3/4/5 is E4h, and for the PSD83xF2 or PSD85xF2 it is E7h. 7.5 Read Memory Sector Protection status The primary Flash memory Sector Protection Status is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 10). During the READ operation, address Bits A6, A1, and A0 must be '0,1,0,' respectively, while Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) designates the Flash memory sector whose protection has to be verified. The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (primary Flash memory or secondary Flash memory) can also be read by the MCU accessing the Flash Protection registers in PSD I/O space. See Section 10.1: Flash Memory Sector Protect for register definitions. 7.6 Reading the Erase/Program Status bits The PSD provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 11. The status bits can be read as many times as needed. For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See Section 8: Programming Flash memory for details. Doc ID 7833 Rev 7 31/128 Instructions Table 11. Status bits(1)(2)(3) FS0FS7/CSBOOT0CSBOOT3 VIH DQ7 Data Polling DQ6 Toggle flag DQ5 Error flag DQ4 DQ3 Erase X timeout DQ2 PSD8XXFX Functional block Flash memory DQ1 DQ0 X X X 1. X = Not guaranteed value, can be read either '1' or ’0.’ 2. DQ7-DQ0 represent the data bus bits, D7-D0. 3. FS0-FS7 and CSBOOT0-CSBOOT3 are active high. 7.7 Data Polling flag (DQ7) When erasing or programming in Flash memory, the Data Polling flag bit (DQ7) outputs the complement of the bit being entered for programming/writing on the DQ7 Bit. Once the Program instruction or the WRITE operation is completed, the true logic value is read on the Data Polling flag bit (DQ7, in a READ operation). ● Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. During an Erase cycle, the Data Polling flag bit (DQ7) outputs a ’0.’ After completion of the cycle, the Data Polling flag bit (DQ7) outputs the last bit programmed (it is a '1' after erasing). If the byte to be programmed is in a protected Flash memory sector, the instruction is ignored. If all the Flash memory sectors to be erased are protected, the Data Polling flag bit (DQ7) is reset to '0' for about 100µs, and then returns to the previous addressed byte. No erasure is performed. ● ● ● 7.8 Toggle flag (DQ6) The PSD offers another way for determining when the Flash memory Program cycle is completed. During the internal WRITE operation and when either the FS0-FS7 or CSBOOT0-CSBOOT3 is true, the Toggle flag bit (DQ6) toggles from '0' to '1' and '1' to '0' on subsequent attempts to read any byte of the memory. When the internal cycle is complete, the toggling stops and the data read on the data bus D0-D7 is the addressed memory byte. The device is now accessible for a new READ or WRITE operation. The cycle is finished when two successive READs yield the same output data. ● ● ● The Toggle flag bit (DQ6) is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). If the byte to be programmed belongs to a protected Flash memory sector, the instruction is ignored. If all the Flash memory sectors selected for erasure are protected, the Toggle flag bit (DQ6) toggles to '0' for about 100µs and then returns to the previous addressed byte. 32/128 Doc ID 7833 Rev 7 PSD8XXFX Instructions 7.9 Error flag (DQ5) During a normal program or erase cycle, the Error flag bit (DQ5) is to ’0.’ This bit is set to '1' when there is a failure during Flash memory Byte Program, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Error flag bit (DQ5) indicates the attempt to program a Flash memory bit from the programmed state, ’0,’ to the erased state, '1,' which is not valid. The Error flag bit (DQ5) may also indicate a timeout condition while attempting to program a byte. In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash memory sector in which the error occurred or to which the programmed byte belongs must no longer be used. Other Flash memory sectors may still be used. The Error flag bit (DQ5) is reset after a Reset Flash instruction. 7.10 Erase timeout flag (DQ3) The Erase timeout flag bit (DQ3) reflects the timeout period allowed between two consecutive Sector Erase instructions. The Erase timeout flag bit (DQ3) is reset to '0' after a Sector Erase cycle for a time period of 100µs + 20% unless an additional Sector Erase instruction is decoded. After this time period, or when the additional Sector Erase instruction is decoded, the Erase timeout flag bit (DQ3) is set to '1.' Doc ID 7833 Rev 7 33/128 Programming Flash memory PSD8XXFX 8 Programming Flash memory Flash memory must be erased prior to being programmed. A byte of Flash memory is erased to all 1s (FFh), and is programmed by setting selected bits to ’0.’ The MCU may erase Flash memory all at once or by-sector, but not byte-by-byte. However, the MCU may program Flash memory byte-by-byte. The primary and secondary Flash memories require the MCU to send an instruction to program a byte or to erase sectors (see Table 10). Once the MCU issues a Flash memory Program or Erase instruction, it must check for the status bits for completion. The embedded algorithms that are invoked inside the PSD support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy (PC3). 8.1 Data Polling Polling on the Data Polling flag bit (DQ7) is a method of checking whether a program or erase cycle is in progress or has completed. Figure 6 shows the Data Polling algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status. The Data Polling flag bit (DQ7) of this location becomes the complement of b7 of the original data byte to be programmed. The MCU continues to poll this location, comparing the Data Polling flag bit (DQ7) and monitoring the Error flag bit (DQ5). When the Data Polling flag bit (DQ7) matches b7 of the original data, and the Error flag bit (DQ5) remains ’0,’ the embedded algorithm is complete. If the Error flag bit (DQ5) is '1,' the MCU should test the Data Polling flag bit (DQ7) again since the Data Polling flag bit (DQ7) may have changed simultaneously with the Error flag bit (DQ5, see Figure 6). The Error flag bit (DQ5) is set if either an internal timeout occurred while the embedded algorithm attempted to program the byte or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte that was written to the Flash memory with the byte that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 6 still applies. However, the Data Polling flag bit (DQ7) is '0' until the Erase cycle is complete. A 1 on the Error flag bit (DQ5) indicates a timeout condition on the Erase cycle; a 0 indicates no error. The MCU can read any location within the sector being erased to get the Data Polling flag bit (DQ7) and the Error flag bit (DQ5). PSDsoft Express generates ANSI C code functions which implement these Data Polling algorithms. 34/128 Doc ID 7833 Rev 7 PSD8XXFX Figure 6. Data Polling flowchart START Programming Flash memory READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA NO NO YES DQ5 =1 YES READ DQ7 DQ7 = DATA NO FAIL YES PASS AI01369B 8.2 Data Toggle Checking the Toggle flag bit (DQ6) is a method of determining whether a program or erase cycle is in progress or has completed. Figure 7 shows the Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status. The Toggle flag bit (DQ6) of this location toggles each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking the Toggle flag bit (DQ6) and monitoring the Error flag bit (DQ5). When the Toggle flag bit (DQ6) stops toggling (two consecutive reads yield the same value), and the Error flag bit (DQ5) remains ’0,’ the embedded algorithm is complete. If the Error flag bit (DQ5) is '1,' the MCU should test the Toggle flag bit (DQ6) again, since the Toggle flag bit (DQ6) may have changed simultaneously with the Error flag bit (DQ5, see Figure 7). The Error flag bit (DQ5) is set if either an internal timeout occurred while the embedded algorithm attempted to program the byte, or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte that was written to Flash memory with the byte that was intended to be written. When using the Data Toggle method after an Erase cycle, Figure 7 still applies. the Toggle flag bit (DQ6) toggles until the Erase cycle is complete. A '1' on the Error flag bit (DQ5) indicates a timeout condition on the Erase cycle; a '0' indicates no error. The MCU can read Doc ID 7833 Rev 7 35/128 Programming Flash memory PSD8XXFX any location within the sector being erased to get the Toggle flag bit (DQ6) and the Error flag bit (DQ5). PSDsoft Express generates ANSI C code functions which implement these Data Toggling algorithms. 8.3 Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x, PSD854F2x) The Unlock Bypass instructions allow the system to program bytes to the Flash memories faster than using the standard Program instruction. The Unlock Bypass mode is entered by first initiating two Unlock cycles. This is followed by a third WRITE cycle containing the Unlock Bypass code, 20h (as shown in Table 10). The Flash memory then enters the Unlock Bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the Unlock Bypass Program code, A0h. The second cycle contains the program address and data. Additional data is programmed in the same manner. These instructions dispense with the initial two Unlock cycles required in the standard Program instruction, resulting in faster total Flash memory programming. During the Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset Flash instructions are valid. To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset Flash instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are Don’t Care for both cycles. The Flash memory then returns to READ mode. 36/128 Doc ID 7833 Rev 7 PSD8XXFX Figure 7. Data Toggle flowchart START Programming Flash memory READ DQ5 & DQ6 DQ6 = TOGGLE YES NO NO DQ5 =1 YES READ DQ6 DQ6 = TOGGLE YES FAIL NO PASS AI01370B Doc ID 7833 Rev 7 37/128 Erasing Flash memory PSD8XXFX 9 9.1 Erasing Flash memory Flash Bulk Erase The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in Table 10. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory status. During a Bulk Erase, the memory status may be checked by reading the Error flag bit (DQ5), the Toggle flag bit (DQ6), and the Data Polling flag bit (DQ7), as detailed in Section 8: Programming Flash memory. The Error flag bit (DQ5) returns a '1' if there has been an Erase Failure (maximum number of Erase cycles have been executed). It is not necessary to program the memory with 00h because the PSD automatically does this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory does not accept any instructions. 9.2 Flash Sector Erase The Sector Erase instruction uses six WRITE operations, as described in Table 10. Additional Flash Sector Erase codes and Flash memory sector addresses can be written subsequently to erase other Flash memory sectors in parallel, without further coded cycles, if the additional bytes are transmitted in a shorter time than the timeout period of about 100µs. The input of a new Sector Erase code restarts the timeout period. The status of the internal timer can be monitored through the level of the Erase timeout flag bit (DQ3). If the Erase timeout flag bit (DQ3) is ’0,’ the Sector Erase instruction has been received and the timeout period is counting. If the Erase timeout flag bit (DQ3) is '1,' the timeout period has expired and the PSD is busy erasing the Flash memory sector(s). Before and during Erase timeout, any instruction other than Suspend Sector Erase and Resume Sector Erase instructions abort the cycle that is currently in progress, and reset the device to READ mode. It is not necessary to program the Flash memory sector with 00h as the PSD does this automatically before erasing (byte = FFh). During a Sector Erase, the memory status may be checked by reading the Error flag bit (DQ5), the Toggle flag bit (DQ6), and the Data Polling flag bit (DQ7), as detailed in Section 8: Programming Flash memory. During execution of the Erase cycle, the Flash memory accepts only Reset and Suspend Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed. 9.3 Suspend Sector Erase When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any address when an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is high. (See Table 10). This allows reading of data from another Flash memory sector after the Erase cycle has been suspended. Suspend Sector Erase is accepted only during an Erase cycle and defaults to READ mode. 38/128 Doc ID 7833 Rev 7 PSD8XXFX Erasing Flash memory A Suspend Sector Erase instruction executed during an Erase timeout period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle flag bit (DQ6) stops toggling when the PSD internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle flag bit (DQ6) stops toggling between 0.1µs and 15µs after the Suspend Sector Erase instruction has been executed. The PSD is then automatically set to READ mode. If an Suspend Sector Erase instruction was executed, the following rules apply: ● ● ● ● Attempting to read from a Flash memory sector that was being erased outputs invalid data. Reading from a Flash sector that was not being erased is valid. The Flash memory cannot be programmed, and only responds to Resume Sector Erase and Reset Flash instructions (READ is an operation and is allowed). If a Reset Flash instruction is received, data in the Flash memory sector that was being erased is invalid. 9.4 Resume Sector Erase If a Suspend Sector Erase instruction was previously executed, the erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any address while an appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) is high. (See Table 10.) Doc ID 7833 Rev 7 39/128 Specific features PSD8XXFX 10 10.1 Specific features Flash Memory Sector Protect Each primary and secondary Flash memory sector can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all program or erase cycles. This mode can be activated through the JTAG port or a device programmer. Sector protection can be selected for each sector using the PSDsoft Express Configuration program. This automatically protects selected sectors when the device is programmed through the JTAG port or a device programmer. Flash memory sectors can be unprotected to allow updating of their contents using the JTAG port or a device programmer. The MCU can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash memory sector is ignored by the device. The Verify operation results in a READ of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can be read by the MCU through the Flash memory protection and PSD/EE protection registers (in the CSIOP block). See Table 12 and Table 13. 10.2 Reset Flash The Reset Flash instruction consists of one WRITE cycle (see Table 10). It can also be optionally preceded by the standard two WRITE decoding cycles (writing AAh to 555h and 55h to AAAh). It must be executed after: ● ● Reading the Flash Protection Status or Flash ID An Error condition has occurred (and the device has set the Error flag bit (DQ5) to '1') during a Flash memory program or erase cycle. On the PSD813F2/3/4/5, the Reset Flash instruction puts the Flash memory back into normal READ mode. It may take the Flash memory up to a few milliseconds to complete the Reset cycle. The Reset Flash instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ mode within a few milliseconds. On the PSD83xF2 or PSD85xF2, the Reset Flash instruction puts the Flash memory back into normal READ mode. If an Error condition has occurred (and the device has set the Error flag bit (DQ5) to '1') the Flash memory is put back into normal READ mode within 25μs of the Reset Flash instruction having been issued. The Reset Flash instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to the normal READ mode within 25μs. 40/128 Doc ID 7833 Rev 7 PSD8XXFX Specific features 10.3 Reset (RESET) signal (on the PSD83xF2 and PSD85xF2) A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash memory to the READ mode. When the reset occurs during a program or erase cycle, the Flash memory takes up to 25μs to return to the READ mode. It is recommended that the Reset (RESET) pulse (except for Power On Reset, as described in Section 18: Reset timing and device status at reset) be at least 25 µs so that the Flash memory is always ready for the MCU to fetch the bootstrap instructions after the Reset cycle is complete. Table 12. Bit 7 Sector Protection/Security Bit definition – Flash Protection register(1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot 1. Bit Definitions: Sec_Prot 1 = Primary Flash memory or secondary Flash memory Sector is write protected. Sec_Prot 0 = Primary Flash memory or secondary Flash memory Sector is not write protected. Table 13. Bit 7 Sector Protection/Security Bit definition – PSD/EE Protection register(1) Bit 6 Bit 5 not used Bit 4 not used Bit 3 Bit 2 Bit 1 Bit 0 Security_B not used it Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot 1. Bit Definitions: Sec_Prot 1 = Secondary Flash memory Sector is write protected. Sec_Prot 0 = Secondary Flash memory Sector is not write protected. Security_Bit 0 = Security Bit in device has not been set. 1 = Security Bit in device has been set. Doc ID 7833 Rev 7 41/128 SRAM PSD8XXFX 11 SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is high. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. SRAM Select (RS0) is configured using PSDsoft Express Configuration. 42/128 Doc ID 7833 Rev 7 PSD8XXFX Sector Select and SRAM Select 12 Sector Select and SRAM Select Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of the DPLD. They are setup by writing equations for them in PSDabel. The following rules apply to the equations for these signals: 1. 2. 3. 4. 5. 6. Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size. Any primary Flash memory sector must not be mapped in the same memory space as another Flash memory sector. A secondary Flash memory sector must not be mapped in the same memory space as another secondary Flash memory sector. SRAM, I/O, and Peripheral I/O spaces must not overlap. A secondary Flash memory sector may overlap a primary Flash memory sector. In case of overlap, priority is given to the secondary Flash memory sector. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is given to the SRAM, I/O, or Peripheral I/O. 12.1 Example FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any address greater than 9FFFh accesses the primary Flash memory segment 0. You can see that half of the primary Flash memory segment 0 and one-fourth of secondary Flash memory segment 0 cannot be accessed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 8 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest. 12.2 Memory select configuration for MCUs with separate program and data spaces The 8031 and compatible family of MCUs, which includes the 80C51, 80C151, 80C251, and 80C51XA, have separate address spaces for program memory (selected using Program Select Enable (PSEN, CNTL2)) and data memory (selected using Read Strobe (RD, CNTL1)). Any of the memories within the PSD can reside in either space or both spaces. This is controlled through manipulation of the VM register that resides in the CSIOP space. The VM register is set using PSDsoft Express to have an initial value. It can subsequently be changed by the MCU so that memory mapping can be changed on-the-fly. For example, you may wish to have SRAM and primary Flash memory in the data space at Boot-up, and secondary Flash memory in the program space at Boot-up, and later swap the primary and secondary Flash memories. This is easily done with the VM register by using Doc ID 7833 Rev 7 43/128 Sector Select and SRAM Select PSD8XXFX PSDsoft Express Configuration to configure it for Boot-up and having the MCU change it when desired. Table 14 describes the VM register. Figure 8. Priority level of memory and I/O components Highest Priority Level 1 SRAM, I/O, or Peripheral I/O Level 2 Secondary Non-Volatile Memory Level 3 Primary Flash Memory Lowest Priority AI02867D 12.3 12.3.1 Configuration modes for MCUs with separate program and data spaces Separate Space modes Program space is separated from data space. For example, Program Select Enable (PSEN, CNTL2) is used to access the program code from the primary Flash memory, while Read Strobe (RD, CNTL1) is used to access data from the secondary Flash memory, SRAM and I/O port blocks. This configuration requires the VM register to be set to 0Ch (see Figure 9). 12.3.2 Combined Space modes The program and data spaces are combined into one memory space that allows the primary Flash memory, secondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to configure the primary Flash memory in Combined space, Bits b2 and b4 of the VM register are set to '1' (see Figure 10). Figure 9. 8031 memory modules – separate space DPLD RS0 CSBOOT0-3 FS0-FS7 Primary Flash Memory Secondary Flash Memory SRAM CS OE CS OE CS OE PSEN RD AI02869C 44/128 Doc ID 7833 Rev 7 PSD8XXFX Figure 10. 8031 memory modules – combined space Sector Select and SRAM Select DPLD RS0 CSBOOT0-3 FS0-FS7 Primary Flash Memory Secondary Flash Memory SRAM RD CS OE CS OE CS OE VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 RD VM REG BIT 0 AI02870C Table 14. Bit 7 PIO_EN VM register Bit 4 Bit 6 Bit 5 Primary FL_Data 0 = RD cannot access Flash memory Bit 3 econdary EE_Data 0 = RD can’t access secondary Flash memory 1 = RD access secondary Flash memory Bit 2 Primary FL_Code 0 = PSEN cannot access Flash memory 1 = PSEN access Flash memory Bit 1 Secondary EE_Code 0 = PSEN can’t access secondary Flash memory 1 = PSEN access secondary Flash memory Bit 0 SRAM_Code 0 = disable PIO mode not used not used 0 = PSEN cannot access SRAM 1 = PSEN access SRAM 1= enable PIO mode not used not used 1 = RD access Flash memory Doc ID 7833 Rev 7 45/128 Page register PSD8XXFX 13 Page register The 8-bit Page register increases the addressing capability of the MCU by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations. If memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the CPLD for general logic. See Application Note AN1154. Figure 11 shows the Page register. The eight flip-flops in the register are connected to the internal data bus D0-D7. The MCU can write to or read from the Page register. The Page register can be accessed at address location CSIOP + E0h. Figure 11. Page register RESET D0 D1 D0 - D7 D2 D3 D4 D5 D6 R/ W D7 Q0 Q1 Q2 Q3 Q4 Q5 PGR0 PGR1 PGR2 PGR3 PGR4 PGR5 PGR6 DPLD AND CPLD INTERNAL SELECTS AND LOGIC Q6 PGR7 Q7 PAGE REGISTER PLD AI02871B 46/128 Doc ID 7833 Rev 7 PSD8XXFX PLDS 14 PLDS The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs using the PSDabel tool in PSDsoft Express, the logic is programmed into the device and available upon Power-up. The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in Section 14.2: Decode PLD (DPLD), and Section 14.3: Complex PLD (CPLD). Figure 12 shows the configuration of the PLDs. The DPLD performs address decoding for Select signals for internal components, such as memory, registers, and I/O ports. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. These logic functions can be constructed using the 16 Output macrocells (OMC), 24 input macrocells (IMC), and the AND Array. The CPLD can also be used to generate External Chip Select (ECS0-ECS2) signals. The AND Array is used to form product terms. These product terms are specified using PSDabel. An input bus consisting of 73 signals is connected to the PLDs. The signals are shown in Table 15. 14.1 The Turbo Bit in PSD The PLDs in the PSD can minimize power consumption by switching off when inputs remain unchanged for an extended time of about 70ns. Resetting the Turbo Bit to '0' (Bit 3 of PMMR0) automatically places the PLDs into standby if no inputs are changing. Turning the Turbo mode off increases propagation delays while reducing power consumption. See Section 17: Power management on how to set the Turbo Bit. Additionally, five bits are available in PMMR2 to block MCU control signals from entering the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations. Each of the two PLDs has unique characteristics suited for its applications. They are described in the following sections. Table 15. DPLD and CPLD inputs Input source MCU address bus(1) MCU control signals Reset Power-down Port A input macrocells Port B input macrocells Port C input macrocells Port D inputs Input name A15-A0 CNTL2-CNTL0 RST PDN PA7-PA0 PB7-PB0 PC7-PC0 PD2-PD0 Number of signals 16 3 1 1 8 8 8 3 Doc ID 7833 Rev 7 47/128 PLDS Table 15. DPLD and CPLD inputs (continued) Input source Page register Macrocell AB feedback Macrocell BC feedback Secondary Flash memory Program Status Bit 1. The address inputs are A19-A4 in 80C51XA mode. PSD8XXFX Input name PGR7-PGR0 MCELLAB.FB7-FB0 MCELLBC.FB7-FB0 Ready/Busy Number of signals 8 8 8 1 48/128 Doc ID 7833 Rev 7 PSD8XXFX 8 DATA BUS PAGE REGISTER Figure 12. PLD diagram DECODE PLD PRIMARY FLASH MEMORY SELECTS SECONDARY NON-VOLATILE MEMORY SELECTS SRAM SELECT CSIOP SELECT PERIPHERAL SELECTS JTAG SELECT 73 4 1 1 2 1 8 PLD INPUT BUS 16 OUTPUT MACROCELL FEEDBACK DIRECT MACROCELL ACCESS FROM MCU DATA BUS I/O PORTS Doc ID 7833 Rev 7 CPLD 16 OUTPUT MACROCELL PT ALLOC. 24 INPUT MACROCELL (PORT A,B,C) 73 DIRECT MACROCELL INPUT TO MCU DATA BUS 24 INPUT MACROCELL & INPUT PORTS 3 PORT D INPUTS MACROCELL ALLOC. MCELLAB TO PORT A OR B MCELLBC TO PORT B OR C 8 8 3 EXTERNAL CHIP SELECTS TO PORT D AI02872C PLDS 49/128 PLDS PSD8XXFX 14.2 Decode PLD (DPLD) The DPLD, shown in Figure 13, is used for decoding the address for internal and external components. The DPLD can be used to generate the following decode signals: ● ● ● ● ● ● 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each) 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) 1 internal SRAM Select (RS0) signal (two product terms) 1 internal CSIOP Select (PSD Configuration register) signal 1 JTAG Select signal (enables JTAG on port C) 2 internal Peripheral Select signals (Peripheral I/O mode). Figure 13. DPLD logic array 3 3 3 3 (INPUTS) I /O PORTS (PORT A,B,C) MCELLAB.FB [7:0] (FEEDBACKS) MCELLBC.FB [7:0] (FEEDBACKS) PGR0 - PGR7 A[15:0] * PD[2:0] (ALE,CLKIN,CSI) PDN (APD OUTPUT) CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) RESET RD_BSY (24) 3 (8) 3 (8) 3 (8) 3 (16) 3 (3) 3 (1) 3 (3) (1) 2 (1) 1 1 1 1 CSIOP PSEL0 PSEL1 JTAGSEL AI02873D CSBOOT 0 CSBOOT 1 CSBOOT 2 CSBOOT 3 3 FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 8 PRIMARY FLASH MEMORY SECTOR SELECTS RS0 SRAM SELECT I/O DECODER SELECT PERIPHERAL I/O MODE SELECT 50/128 Doc ID 7833 Rev 7 PSD8XXFX PLDS 14.3 Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate three External Chip Select (ECS0-ECS2), routed to port D. Although External Chip Select (ECS0-ECS2) can be produced by any Output macrocell (OMC), these three External Chip Select (ECS0-ECS2) on port D do not consume any Output macrocells (OMC). As shown in Figure 12, the CPLD has the following blocks: ● ● ● ● ● ● 24 input macrocells (IMC) 16 Output macrocells (OMC) Macrocell Allocator Product Term Allocator AND Array capable of generating up to 137 product terms Four I/O ports. Each of the blocks are described in the sections that follow. The input macrocells (IMC) and Output macrocells (OMC) are connected to the PSD internal data bus and can be directly accessed by the MCU. This enables the MCU software to load data into the Output macrocells (OMC) or read data from both the input and Output macrocells (IMC and OMC). This feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the AND Array as required in most standard PLD macrocell architectures. Doc ID 7833 Rev 7 51/128 PLDS PLD INPUT BUS AND ARRAY PR DI LD D/T Q COMB. /REG SELECT MACROCELL TO I/O PORT ALLOC. WR PT CLEAR CPLD OUTPUT PDR INPUT MUX D/T/JK FF SELECT CK CL PT CLOCK GLOBAL CLOCK SELECT MUX PLD INPUT BUS PT INPUT LATCH GATE/CLOCK MUX ALE/AS MUX 52/128 PRODUCT TERMS FROM OTHER MACROCELLS TO OTHER I/O PORTS MCU ADDRESS / DATA BUS CPLD MACROCELLS I/O PORTS MCU DATA IN MCU LOAD D Q MUX WR UP TO 10 PRODUCT TERMS MACROCELL OUT TO MCU CPLD OUTPUT DATA DATA LOAD CONTROL LATCHED ADDRESS OUT PT PRESET PRODUCT TERM ALLOCATOR Figure 14. Macrocell and I/O port I/O PIN POLARITY SELECT Doc ID 7833 Rev 7 CLOCK SELECT PT OUTPUT ENABLE (OE) MACROCELL FEEDBACK I/O PORT INPUT D Q DIR REG. INPUT MACROCELLS QD QD G AI02874 PSD8XXFX PSD8XXFX PLDS 14.4 Output macrocell (OMC) Eight of the Output macrocells (OMC) are connected to ports A and B pins and are named as McellAB0-McellAB7. The other eight macrocells are connected to ports B and C pins and are named as McellBC0-McellBC7. If an McellAB output is not assigned to a specific pin in PSDabel, the macrocell Allocator block assigns it to either port A or B. The same is true for a McellBC output on port B or C. Table 16 shows the macrocells and port assignment. The Output macrocell (OMC) architecture is shown in Figure 15. As shown in the figure, there are native product terms available from the AND Array, and borrowed product terms available (if unused) from other Output macrocells (OMC). The polarity of the product term is controlled by the XOR gate. The Output macrocell (OMC) can implement either sequential logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs. The flip-flop in the Output macrocell (OMC) block can be configured as a D, T, JK, or SR type in the PSDabel program. The flip-flop’s clock, preset, and clear inputs may be driven from a product term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset and clear are active high inputs. Each clear input can use up to two product terms. Table 16. Output macrocell McellAB0 McellAB1 McellAB2 McellAB3 McellAB4 McellAB5 McellAB6 McellAB7 McellBC0 McellBC1 McellBC2 McellBC3 McellBC4 McellBC5 McellBC6 McellBC7 Output macrocell port and data bit assignments Port assignment Port A0, B0 Port A1, B1 Port A2, B2 Port A3, B3 Port A4, B4 Port A5, B5 Port A6, B6 Port A7, B7 Port B0, C0 Port B1, C1 Port B2, C2 Port B3, C3 Port B4, C4 Port B5, C5 Port B6, C6 Port B7, C7 Native product terms 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 Maximum borrowed product terms 6 6 6 6 6 6 6 6 5 5 5 5 6 6 6 6 Data bit for loading or reading D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Doc ID 7833 Rev 7 53/128 PLDS PSD8XXFX 14.5 Product Term Allocator The CPLD has a Product Term Allocator. The PSDabel compiler uses the Product Term Allocator to borrow and place product terms from one macrocell to another. The following list summarizes how product terms are allocated: ● ● ● McellAB0-McellAB7 all have three native product terms and may borrow up to six more McellBC0-McellBC3 all have four native product terms and may borrow up to five more McellBC4-McellBC7 all have four native product terms and may borrow up to six more. Each macrocell may only borrow product terms from certain other macrocells. Product terms already in use by one macrocell are not available for another macrocell. If an equation requires more product terms than are available to it, then “external” product terms are required, which consume other Output macrocells (OMC). If external product terms are used, extra delay is added for the equation that required the extra product terms. This is called product term expansion. PSDsoft Express performs this expansion as needed. 14.6 Loading and reading the Output macrocells (OMC) The Output macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP block (see Section 16: I/O ports). The flip-flops in each of the 16 Output macrocells (OMC) can be loaded from the data bus by a MCU. Loading the Output macrocells (OMC) with data from the MCU takes priority over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be overridden by the MCU. The ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. Data can be loaded to the Output macrocells (OMC) on the trailing edge of Write Strobe (WR, CNTL0) (edge loading) or during the time that Write Strobe (WR, CNTL0) is active (level loading). The method of loading is specified in PSDsoft Express Configuration. 14.7 The OMC Mask register There is one Mask register for each of the two groups of eight Output macrocells (OMC). The Mask registers can be used to block the loading of data to individual Output macrocells (OMC). The default value for the Mask registers is 00h, which allows loading of the Output macrocells (OMC). When a given bit in a Mask register is set to a 1, the MCU is blocked from writing to the associated Output macrocells (OMC). For example, suppose McellAB0McellAB3 are being used for a state machine. You would not want a MCU write to McellAB to overwrite the state machine registers. Therefore, you would want to load the Mask register for McellAB (Mask macrocell AB) with the value 0Fh. 14.8 The Output Enable of the OMC The Output macrocells (OMC) block can be connected to an I/O port pin as a PLD output. The output enable of each port pin driver is controlled by a single product term from the AND Array, ORed with the Direction register output. The pin is enabled upon Power-up if no output enable equation is defined and if the pin is declared as a PLD output in PSDsoft Express. 54/128 Doc ID 7833 Rev 7 PSD8XXFX PLDS If the Output macrocell (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, the port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND Array. Figure 15. CPLD Output macrocell I/O PIN AI02875B DIRECTION REGISTER INTERNAL DATA BUS MACROCELL ALLOCATOR D [ 7:0] DIN PR LD ENABLE (.OE) PRESET(.PR) IN CLEAR (.RE) CLR PROGRAMMABLE FF (D/T/JK /SR) COMB/REG SELECT MUX Q MUX FEEDBACK (.FB) MACROCELL CS MASK REG. PT ALLOCATOR PT PT POLARITY SELECT RD WR PT CLK Doc ID 7833 Rev 7 CLKIN PLD INPUT BUS PT PORT INPUT INPUT MACROCELL PORT DRIVER AND ARRAY 55/128 PLDS PSD8XXFX 14.9 Input macrocells (IMC) The CPLD has 24 input macrocells (IMC), one for each pin on ports A, B, and C. The architecture of the input macrocells (IMC) is shown in Figure 16. The input macrocells (IMC) are individually configurable, and can be used as a latch, register, or to pass incoming port signals prior to driving them onto the PLD input bus. The outputs of the input macrocells (IMC) can be read by the MCU through the internal data bus. The enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each product term output is used to latch or clock four input macrocells (IMC). port inputs 3-0 can be controlled by one product term and 7-4 by another. Configurations for the input macrocells (IMC) are specified by equations written in PSDabel (see Application Note AN1171). outputs of the input macrocells (IMC) can be read by the MCU via the IMC buffer (see Section 16: I/O ports). Input macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher than A15. Any latched addresses are routed to the PLDs as inputs. Input macrocells (IMC) are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox. Figure 17 shows a typical configuration where the Master MCU writes to the port A Data Out register. This, in turn, can be read by the Slave MCU via the activation of the “Slave-Read” output enable product term. The Slave can also write to the port A input macrocells (IMC) and the Master can then read the input macrocells (IMC) directly. Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are derived from the Slave MCU inputs Read Strobe (RD, CNTL1), Write Strobe (WR, CNTL0), and Slave_CS. 56/128 Doc ID 7833 Rev 7 PSD8XXFX INTERNAL DATA BUS D [ 7:0] Figure 16. Input macrocell INPUT MACROCELL _ RD DIRECTION REGISTER ENABLE ( .OE ) PT OUTPUT MACROCELLS BC AND MACROCELL AB I/O PIN AND ARRAY Doc ID 7833 Rev 7 PLD INPUT BUS PT MUX Q D MUX D FF FEEDBACK Q D G LATCH PT PORT DRIVER ALE/AS INPUT MACROCELL AI02876B PLDS 57/128 PLDS 58/128 PSD SLAVE– CS RD WR SLAVE – READ PORT A DATA OUT REGISTER MCU-RD D MCU-WR Q MASTER MCU SLAVE – WR D [ 7:0] PORT A INPUT MACROCELL Q MCU-RD D MCU-WR CPLD D [ 7:0] PORT A Figure 17. Handshaking communication using input macrocells SLAVE MCU Doc ID 7833 Rev 7 AI02877C PSD8XXFX PSD8XXFX MCU bus interface 15 MCU bus interface The “no-glue logic” MCU bus interface block can be directly connected to most popular MCUs and their control signals. Key 8-bit MCUs, with their bus types and control signals, are shown in Table 17. The interface type is specified using the PSDsoft Express Configuration. Table 17. MCU 8031 MCUs and their control signals Data bus width 8 8 8 8 8 8 8 8 8 8 8 CNTL0 WR WR WR WR WR R/W R/W WR R/W R/W R/W CNTL1 RD RD PSEN RD RD E E RD DS DS E CNTL2 PSEN PSEN (2) PC7 (2) (2) (2) (2) (2) (2) PD0(1) ALE ALE ALE ALE ALE AS AS (2) ADIO0 A0 A4 A0 A0 A0 A0 A0 A0 A0 A0 A0 PA3-PA0 (2) PA7-PA3 (2) (2) (2) (2) (2) (2) (2) 80C51XA 80C251 80C251 80198 68HC11 68HC912 Z80 Z8 68330 M37702M2 A3-A0 (2) (2) (2) (2) (2) PSEN (2) (2) (2) (2) (2) (2) (2) DBE (2) (2) (2) (2) D3-D0 (2) (2) D7-D4 (2) (2) AS AS ALE D3-D0 D7-D4 1. ALE/AS input is optional for MCUs with a non-multiplexed bus 2. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be configured for other I/O functions. Doc ID 7833 Rev 7 59/128 MCU bus interface PSD8XXFX 15.1 PSD interface to a multiplexed 8-bit bus Figure 18 shows an example of a system using a MCU with an 8-bit multiplexed bus and a PSD. The ADIO port on the PSD is connected directly to the MCU address/data bus. Address Strobe (ALE/AS, PD0) latches the address signals internally. Latched addresses can be brought out to port A or B. The PSD drives the ADIO data bus only when one of its internal resources is accessed and Read Strobe (RD, CNTL1) is active. Should the system address bus exceed sixteen bits, ports A, B, C, or D may be used as additional address inputs. Figure 18. An example of a typical 8-bit multiplexed bus interface MCU AD [ 7:0] PSD PORT A A [ 7: 0] (OPTIONAL) A[ 15:8] ADIO PORT PORT B WR RD BHE WR (CNTRL0) RD (CNTRL1) BHE (CNTRL2) RST ALE ALE (PD0) PORT D RESET A [ 15: 8] (OPTIONAL) PORT C AI02878C 15.2 PSD interface to a non-multiplexed 8-bit bus Figure 19 shows an example of a system using a MCU with an 8-bit non-multiplexed bus and a PSD. The address bus is connected to the ADIO port, and the data bus is connected to port A. port A is in tri-state mode when the PSD is not accessed by the MCU. Should the system address bus exceed sixteen bits, ports B, C, or D may be used for additional address inputs. 15.3 Data Byte Enable reference MCUs have different data byte orientations. Table 18 shows how the PSD interprets byte/word operations in different bus WRITE configurations. Even-byte refers to locations with address A0 equal to '0' and odd byte as locations with A0 equal to ’1.’ 60/128 Doc ID 7833 Rev 7 PSD8XXFX MCU bus interface 15.4 MCU bus interface examples Figure 20, Figure 21, Figure 22, Figure 23, and Figure 24 show examples of the basic connections between the PSD and some popular MCUs. The PSD Control input pins are labeled as to the MCU function for which they are configured. The MCU bus interface is specified using the PSDsoft Express Configuration. Table 18. 8-bit data bus BHE X X A0 0 1 Even byte Odd byte D7-D0 Figure 19. An example of a typical 8-bit non-multiplexed bus interface MCU D [ 7:0] PSD PORT A D [ 7:0] ADIO PORT A [ 15:0] PORT B WR RD BHE WR (CNTRL0) RD (CNTRL1) BHE (CNTRL2) RST A[ 23:16] (OPTIONAL) PORT C ALE ALE (PD0) PORT D RESET AI02879C Doc ID 7833 Rev 7 61/128 MCU bus interface PSD8XXFX 15.5 80C31 Figure 20 shows the bus interface for the 80C31, which has an 8-bit multiplexed address/data bus. The lower address byte is multiplexed with the data bus. The MCU control signals Program Select Enable (PSEN, CNTL2), Read Strobe (RD, CNTL1), and Write Strobe (WR, CNTL0) may be used for accessing the internal memory and I/O ports blocks. Address Strobe (ALE/AS, PD0) latches the address. Figure 20. Interfacing the PSD with an 80C31 AD7-AD0 AD[ 7:0] 80C31 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 EA/VP X1 X2 RESET INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE/P TXD RXD 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15 RD WR PSEN ALE AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 30 31 32 33 34 35 36 37 PSD ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 29 28 27 25 24 23 22 21 RESET 39 40 41 42 43 44 45 46 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11 47 50 49 10 9 8 48 CNTL0 (WR) CNTL1(RD) CNTL2 (PSEN) PD0-ALE PD1 PD2 RESET RESET RESET AI02880C 62/128 Doc ID 7833 Rev 7 PSD8XXFX MCU bus interface 15.6 80C251 The Intel 80C251 MCU features a user-configurable bus interface with four possible bus configurations, as shown in Table 19. The first configuration is 80C31-compatible, and the bus interface to the PSD is identical to that shown in Figure 20. The second and third configurations have the same bus connection as shown in Figure 21. There is only one Read Strobe (PSEN) connected to CNTL1 on the PSD. The A16 connection to PA0 allows for a larger address input to the PSD. The fourth configuration is shown in Figure 22. Read Strobe (RD) is connected to CNTL1 and Program Select Enable (PSEN) is connected to CNTL2. The 80C251 has two major operating modes: Page mode and Non-page mode. In Nonpage mode, the data is multiplexed with the lower address byte, and Address Strobe (ALE/AS, PD0) is active in every bus cycle. In Page mode, data (D7-D0) is multiplexed with address (A15-A8). In a bus cycle where there is a Page hit, Address Strobe (ALE/AS, PD0) is not active and only addresses (A7-A0) are changing. The PSD supports both modes. In Page mode, the PSD bus timing is identical to Non-Page mode except the address hold time and setup time with respect to Address Strobe (ALE/AS, PD0) is not required. The PSD access time is measured from address (A7-A0) valid to data in valid. Figure 21. Interfacing the PSD with the 80C251, with One READ input 80C251SB 2 3 4 5 6 7 8 9 21 20 11 13 14 15 16 17 PSD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 A0 A1 A2 A3 A4 A5 A6 A7 30 31 32 33 34 35 36 37 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 X1 X2 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 RST EA ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 29 28 27 25 24 23 22 21 A161 A171 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 39 40 41 42 43 44 45 46 47 50 49 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 CNTL0 ( WR) CNTL1( RD) CNTL 2(PSEN) PD0-ALE PD1 PD2 RESET 7 6 5 4 3 2 52 51 RESET 10 ALE PSEN WR RD/A16 33 32 18 19 ALE RD WR A16 35 10 9 8 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 20 19 18 17 14 13 12 11 RESET RESET 48 AI02881C 1. The A16 and A17 connections are optional. 2. In non-Page-mode, AD7-AD0 connects to ADIO7-ADIO0. Doc ID 7833 Rev 7 63/128 MCU bus interface Figure 22. Interfacing the PSD with the 80C251, with RD and PSEN inputs 80C251SB 2 3 4 5 6 7 8 9 21 20 11 13 14 15 16 17 PSD8XXFX PSD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 A0 A1 A2 A3 A4 A5 A6 A7 30 31 32 33 34 35 36 37 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 X1 X2 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 RST EA ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 29 28 27 25 24 23 22 21 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 39 40 41 42 43 44 45 46 47 50 49 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 CNTL0 ( WR) CNTL1( RD) CNTL 2(PSEN) PD0-ALE PD1 PD2 RESET 7 6 5 4 3 2 52 51 RESET 10 ALE PSEN WR RD/A16 33 32 18 19 ALE RD WR PSEN 35 10 9 8 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 20 19 18 17 14 13 12 11 RESET RESET 48 AI02882C Table 19. 80C251 configurations 80C251 READ/WRITE pins WR RD PSEN WR PSEN only WR PSEN only WR RD PSEN Connecting to PSD pins CNTL0 CNTL1 CNTL2 CNTL0 CNTL1 CNTL0 CNTL1 CNTL0 CNTL1 CNTL2 Page mode Configuration 1 Non-Page mode, 80C31 compatible A7-A0 multiplex with D7-D0 Non-Page mode A7-A0 multiplex with D7-D0 Page mode A15-A8 multiplex with D7-D0 Page mode A15-A8 multiplex with D7-D0 2 3 4 64/128 Doc ID 7833 Rev 7 PSD8XXFX MCU bus interface 15.7 80C51XA The Philips 80C51XA MCU family supports an 8- or 16-bit multiplexed bus that can have burst cycles. Address bits (A3-A0) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4) are multiplexed with data bits (D7-D0). The 80C51XA can be configured to operate in eight-bit data mode (as shown in Figure 23). The 80C51XA improves bus throughput and performance by executing burst cycles for code fetches. In Burst mode, address A19-A4 are latched internally by the PSD, while the 80C51XA changes the A3-A0 signals to fetch up to 16 bytes of code. The PSD access time is then measured from address A3-A0 valid to data in valid. The PSD bus timing requirement in Burst mode is identical to the normal bus cycle, except the address setup and hold time with respect to Address Strobe (ALE/AS, PD0) does not apply. Figure 23. Interfacing the PSD with the 80C51X, 8-bit data bus 80C51XA 21 20 XTAL1 XTAL2 A0/WRH A1 A2 A3 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12D8 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 2 3 4 5 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12 A13 A14 A15 A16 A17 A18 A19 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 30 31 32 33 34 35 36 37 PSD ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 A0 A1 A2 A3 11 13 6 7 RXD0 TXD0 RXD1 TXD1 9 8 16 T2EX T2 T0 RESET 10 14 15 RST INT0 INT1 A12 A13 A14 A15 A16 A17 A18 A19 39 ADIO8 40 ADIO9 41 ADIO10 42 ADIO11 43 AD1012 44 AD1013 45 ADIO14 46 ADIO15 47 50 35 17 32 19 18 33 PSEN RD WR ALE 49 10 8 9 48 CNTL0 (WR) CNTL1(RD) CNTL 2 (PSEN) PD0-ALE PD1 PD2 RESET EA/WAIT BUSW PSEN RD WRL ALE PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 20 19 18 17 14 13 12 11 RESET AI02883C Doc ID 7833 Rev 7 65/128 MCU bus interface PSD8XXFX 15.8 68HC11 Figure 24 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit multiplexed mode with E and R/W settings. The DPLD can be used to generate the READ and WR signals for external devices. Figure 24. Interfacing the PSD with a 68HC11 AD7-AD0 AD7-AD0 PSD 68HC11 8 7 RESET 17 19 18 2 34 33 32 XT EX RESET IRQ XIRQ MODB PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 31 30 29 28 27 42 41 40 39 38 37 36 35 9 10 11 12 13 14 15 16 20 21 22 23 24 25 3 5 4 6 E AS R/ W AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 MODA E AS R/W PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 43 44 45 46 47 48 49 50 52 51 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 VRH VRL 47 50 49 10 9 8 48 CNTL0 (R _W) CNTL1(E) CNTL 2 PD0 – AS PD1 PD2 RESET RESET AI02884C 66/128 Doc ID 7833 Rev 7 PSD8XXFX I/O ports 16 I/O ports There are four programmable I/O ports: ports A, B, C, and D. Each of the ports is eight bits except port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Express Configuration or by the MCU writing to on-chip registers in the CSIOP space. The topics discussed in this section are: ● ● ● ● ● General port architecture Port operating modes Port configuration registers (PCR) Port Data registers Individual port functionality. 16.1 General port architecture The general architecture of the I/O port block is shown in Figure 25. Individual port architectures are shown in Figure 27, Figure 28, Figure 29, and Figure 30. In general, once the purpose for a port pin has been defined, that pin is no longer available for other purposes. Exceptions are noted. As shown in Figure 25, the ports contain an output multiplexer whose select signals are driven by the configuration bits in the Control registers (Ports A and B only) and PSDsoft Express Configuration.Inputs to the multiplexer include the following: ● ● ● ● Output data from the Data Out register Latched address outputs CPLD macrocell output External Chip Select (ECS0-ECS2) from the CPLD. The port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The port Data Buffer (PDB) is connected to the Internal data bus for feedback and can be read by the MCU. The Data Out and macrocell outputs, Direction and Control registers, and port pin input are all connected to the port data buffer (PDB). The port pin’s tri-state output driver enable is controlled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in the PSDabel file, then the Direction register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the MCU. The port Data Buffer (PDB) feedback path allows the MCU to check the contents of the registers. Ports A, B, and C have embedded input macrocells (IMC). The input macrocells (IMC) can be configured as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by Address Strobe (ALE/AS, PD0) or a product term from the PLD AND Array. The outputs from the input macrocells (IMC) drive the PLD input bus and can be read by the MCU (see Figure 16: Input macrocell). Doc ID 7833 Rev 7 67/128 I/O ports PSD8XXFX 16.2 Port operating modes The I/O ports have several modes of operation. Some modes can be defined using PSDabel, some by the MCU writing to the Control registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft Express must be programmed into the device and cannot be changed unless the device is reprogrammed. The modes that can be changed by the MCU can be done so dynamically at run-time. The PLD I/O, Data port, Address input, and Peripheral I/O modes are the only modes that must be defined before programming the device. All other modes can be changed by the MCU at run-time. See Application Note AN1171 for more detail. Table 20 summarizes which modes are available on each port. Table 23 shows how and where the different modes are configured. Each of the port operating modes are described in the following sections. Figure 25. General I/O port architecture DATA OUT REG. D WR ADDRESS ALE D G Q ADDRESS OUTPUT MUX PORT PIN Q DATA OUT MACROCELL OUTPUTS EXT CS INTERNAL DATA BUS READ MUX P D B DATA IN OUTPUT SELECT CONTROL REG. D WR DIR REG. D WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL CPLD-INPUT AI02885 Q ENABLE OUT Q 68/128 Doc ID 7833 Rev 7 PSD8XXFX I/O ports 16.3 MCU I/O mode In the MCU I/O mode, the MCU uses the I/O ports block to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD are mapped into the MCU address space. The addresses of the ports are listed in Table 8. A port pin can be put into MCU I/O mode by writing a 0 to the corresponding bit in the Control register. The MCU I/O direction may be changed by writing to the corresponding bit in the Direction register, or by the output enable product term (see Section 16.8: Peripheral I/O mode). When the pin is configured as an output, the content of the Data Out register drives the pin. When configured as an input, the MCU can read the port input through the Data In buffer (see Figure 25). Ports C and D do not have Control registers, and are in MCU I/O mode by default. They can be used for PLD I/O if equations are written for them in PSDabel. 16.4 PLD I/O mode The PLD I/O mode uses a port as an input to the CPLD’s input macrocells (IMC), and/or as an output from the CPLD’s Output macrocells (OMC). The output can be tri-stated with a control signal. This output enable control signal can be defined by a product term from the PLD, or by resetting the corresponding bit in the Direction register to ’0.’ The corresponding bit in the Direction register must not be set to '1' if the pin is defined for a PLD input signal in PSDabel. The PLD I/O mode is specified in PSDabel by declaring the port pins, and then writing an equation assigning the PLD I/O to a port. 16.5 Address Out mode For MCUs with a multiplexed address/data bus, Address Out mode can be used to drive latched addresses on to the port pins. These port pins can, in turn, drive external devices. Either the output enable or the corresponding bits of both the Direction register and Control register must be set to a 1 for pins to use Address Out mode. This must be done by the MCU at run-time. See Table 22 for the address output pin assignments on ports A and B for various MCUs. For non-multiplexed 8-bit bus mode, address signals (A7-A0) are available to port B in Address Out mode. Note: Do not drive address signals with Address Out mode to an external memory device if it is intended for the MCU to Boot from the external device. The MCU must first Boot from PSD memory so the Direction and Control register bits can be set. Table 20. Port operating modes Port A Yes Yes No No Yes Port B Yes Yes Yes No Yes Port C Yes No Yes No Yes Port D Yes No No Yes Yes Port mode MCU I/O PLD I/O McellAB outputs McellBC outputs Additional Ext. CS outputs PLD inputs Doc ID 7833 Rev 7 69/128 I/O ports Table 20. Port operating modes (continued) Port A Yes (A7 – 0) Yes Yes (D7 – 0) Yes No Port B Yes (A7 – 0) or (A15 – 8) Yes No No No Port C No Yes No No Yes(1) PSD8XXFX Port mode Address Out Address In Data port Peripheral I/O JTAG ISP Port D No Yes No No No 1. Can be multiplexed with other I/O functions. Table 21. Mode Port operating mode settings Defined in PSDabel Defined in PSD configuration N/A(1) N/A Specify bus type N/A N/A N/A JTAG Configuration Control register setting 0 N/A N/A 1 N/A N/A N/A Direction register setting 1 = output, 0 = input(2) (2) VM register setting N/A N/A N/A N/A N/A PIO bit = 1 N/A JTAG Enable MCU I/O PLD I/O Data port (Port A) Address Out (Port A,B) Address In (Port A,B,C,D) Peripheral I/O (Port A) JTAG ISP(3) 1. N/A = Not Applicable Declare pins only Logic equations N/A Declare pins only Logic for equation input macrocells Logic equations (PSEL0 & 1) JTAGSEL N/A N/A N/A N/A N/A N/A JTAG_Enable N/A 1(2) N/A N/A N/A 2. The direction of the port A,B,C, and D pins are controlled by the Direction register ORed with the individual output enable product term (.oe) from the CPLD AND Array. 3. Any of these three methods enables the JTAG pins on port C. Table 22. MCU I/O port Latched address output assignments Port A (PA3-PA0) N/A(1) N/A Address a3-a0 N/A Port A (PA7-PA4) Address a7-a4 N/A Address a7-a4 N/A Port B (PB3-PB0) Address a11-a8 Address a11-a8 Address a3-a0 Address a3-a0 Port B (PB7-PB4) N/A Address a15-a12 Address a7-a4 Address a7-a4 8051XA (8-Bit) 80C251 (Page mode) All Other 8-Bit Multiplexed 8-Bit Non-Multiplexed bus 1. N/A = Not Applicable 70/128 Doc ID 7833 Rev 7 PSD8XXFX I/O ports 16.6 Address In mode For MCUs that have more than 16 address signals, the higher addresses can be connected to port A, B, C, and D. The address input can be latched in the input macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is included in the DPLD equations for the SRAM, or primary or secondary Flash memory is considered to be an address input. 16.7 Data port mode Port A can be used as a data bus port for a MCU with a non-multiplexed address/data bus. The Data port is connected to the data bus of the MCU. The general I/O functions are disabled in port A if the port is configured as a Data port. 16.8 Peripheral I/O mode Peripheral I/O mode can be used to interface with external peripherals. In this mode, all of port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is enabled by setting Bit 7 of the VM register to a ’1.’ Figure 26 shows how port A acts as a bidirectional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for PSEL0 and/or PSEL1 must be written in PSDabel. The buffer is tri-stated when PSEL0 or PSEL1 is not active. Figure 26. Peripheral I/O mode RD PSEL0 PSEL PSEL1 D0 - D7 DATA BUS VM REGISTER BIT 7 PA0 - PA7 WR AI02886 16.9 JTAG in-system programming (ISP) Port C is JTAG compliant, and can be used for in-system programming (ISP). You can multiplex JTAG operations with other functions on port C because in-system programming (ISP) is not performed in normal operating mode. For more information on the JTAG port, see Section 19: Programming in-circuit using the JTAG serial interface. Doc ID 7833 Rev 7 71/128 I/O ports PSD8XXFX 16.10 Port configuration registers (PCR) Each port has a set of port configuration registers (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given in Table 8. The addresses in Table 8 are the offsets in hexadecimal from the base of the CSIOP register. The pins of a port are individually configurable and each bit in the register controls its respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three port configuration registers (PCR), shown in Table 23, are used for setting the port configurations. The default Power-up state for each register in Table 23 is 00h. 16.11 Control register Any bit reset to '0' in the Control register sets the corresponding port pin to MCU I/O mode, and a '1' sets it to Address Out mode. The default mode is MCU I/O. Only ports A and B have an associated Control register. 16.12 Direction register The Direction register, in conjunction with the output enable (except for port D), controls the direction of data flow in the I/O ports. Any bit set to '1' in the Direction register causes the corresponding pin to be an output, and any bit set to '0' causes it to be an input. The default mode for all port pins is input. Figure 27 and Figure 28 show the port architecture diagrams for ports A/B and C, respectively. The direction of data flow for ports A, B, and C are controlled not only by the direction register, but also by the output enable product term from the PLD AND Array. If the output enable product term is not active, the Direction register has sole control of a given pin’s direction. An example of a configuration for a port with the three least significant bits set to output and the remainder set to input is shown in Table 26. Since port D only contains three pins (shown in Figure 30), the Direction register for port D has only the three least significant bits active. 16.13 Drive Select register The Drive Select register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should be used for pins configured as Open Drain. A pin can be configured as Open Drain if its corresponding bit in the Drive Select register is set to a ’1.’ The default pin drive is CMOS. Note that the slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when the corresponding bit in the Drive register is set to ’1.’ The default rate is slow slew. Table 27 shows the Drive register for ports A, B, C, and D. It summarizes which pins can be configured as Open Drain outputs and which pins the slew rate can be set for. 72/128 Doc ID 7833 Rev 7 PSD8XXFX Table 23. Port configuration registers (PCR)t Port A,B A,B,C,D (1) I/O ports Register name Control Direction Drive Select MCU access WRITE/READ WRITE/READ WRITE/READ A,B,C,D 1. See Table 27 for Drive register bit definition. Table 24. Port Pin Direction Control, Output Enable P.T. not defined Direction register bit 0 1 Port Pin mode Input Output Table 25. Port Pin Direction Control, Output Enable P.T. defined Output Enable P.T. 0 1 0 1 Port Pin mode Input Output Output Output Direction register Bit 0 0 1 1 Table 26. Bit 7 0 Port Direction assignment example Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 1 Bit 1 1 Bit 0 1 Table 27. Drive register Port A Port B Port C Port D Drive register pin assignment Bit 7 Open Drain Open Drain Open Drain NA(1) Bit 6 Open Drain Open Drain Open Drain NA(1) Bit 5 Open Drain Open Drain Open Drain NA(1) Bit 4 Open Drain Open Drain Open Drain NA(1) Bit 3 Slew Rate Slew Rate Open Drain NA(1) Bit 2 Slew Rate Slew Rate Open Drain Slew Rate Bit 1 Slew Rate Slew Rate Open Drain Slew Rate Bit 0 Slew Rate Slew Rate Open Drain Slew Rate 1. NA = Not Applicable. Doc ID 7833 Rev 7 73/128 I/O ports PSD8XXFX 16.14 Port Data registers The port Data registers, shown in Table 28, are used by the MCU to write data to or read data from the ports. Table 28 shows the register name, the ports having each register type, and MCU access for each register type. The registers are described below. 16.15 Data In Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input is read through the Data In buffer. 16.16 Data Out register Stores output data written by the MCU in the MCU I/O output mode. The contents of the register are driven out to the pins if the Direction register or the output enable product term is set to ’1.’ The contents of the register can also be read back by the MCU. Output macrocells (OMC) The CPLD Output macrocells (OMC) occupy a location in the MCU’s address space. The MCU can read the output of the Output macrocells (OMC). If the OMC Mask register bits are not set, writing to the macrocell loads data to the macrocell flip-flops (see Section 14: PLDS). 16.17 OMC Mask register Each OMC Mask register bit corresponds to an Output macrocell (OMC) flip-flop. When the OMC Mask register bit is set to a 1, loading data into the Output macrocell (OMC) flip-flop is blocked. The default value is 0 or unblocked. Table 28. Port Data registers Port A,B,C,D A,B,C,D A,B,C A,B,C A,B,C A,B,C READ – input on pin WRITE/READ READ – outputs of macrocells WRITE – loading macrocells flip-flop WRITE/READ – prevents loading into a given macrocell READ – outputs of the input macrocells READ – the output enable control of the port driver MCU access Register name Data In Data Out Output macrocell Mask macrocell Input macrocell Enable Out 16.18 Input macro (IMC) The input macrocells (IMC) can be used to latch or store external inputs. The outputs of the input macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU (see Section 14: PLDS). 74/128 Doc ID 7833 Rev 7 PSD8XXFX I/O ports 16.19 Enable Out The Enable Out register can be read by the MCU. It contains the output enable values for a given port. A 1 indicates the driver is in output mode. A 0 indicates the driver is in tri-state and the pin is in input mode. 16.20 Ports A and B – functionality and structure Ports A and B have similar functionality and structure, as shown in Figure 27. The two ports can be configured to perform one or more of the following functions: ● ● ● ● ● ● ● ● ● MCU I/O mode CPLD Output – macrocells McellAB7-McellAB0 can be connected to port A or port B. McellBC7-McellBC0 can be connected to port B or port C. CPLD input – Via the input macrocells (IMC). Latched Address output – Provide latched address output as per Table 22. Address In – Additional high address inputs using the input macrocells (IMC). Open Drain/Slew Rate – pins PA3-PA0 and PB3-PB0 can be configured to fast slew rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain mode. Data port – port A to D7-D0 for 8 bit non-multiplexed bus Multiplexed Address/Data port for certain types of MCU bus interfaces. Peripheral mode – port A only Figure 27. Port A and port B structure DATA OUT REG. D WR ADDRESS ALE D G Q ADDRESS A[ 7:0] OR A[15:8] OUTPUT MUX PORT A OR B PIN Q DATA OUT MACROCELL OUTPUTS READ MUX P D B CONTROL REG. D WR DIR REG. D WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL Q Q ENABLE OUT DATA IN OUTPUT SELECT INTERNAL DATA BUS CPLD - INPUT AI02887 Doc ID 7833 Rev 7 75/128 I/O ports PSD8XXFX 16.21 Port C – functionality and structure Port C can be configured to perform one or more of the following functions (see Figure 28): ● ● ● ● ● MCU I/O mode CPLD Output – McellBC7-McellBC0 outputs can be connected to port B or port C. CPLD input – via the input macrocells (IMC) Address In – Additional high address inputs using the input macrocells (IMC). In-system programming (ISP) – JTAG port can be enabled for programming/erase of the PSD device (see Section 19: Programming in-circuit using the JTAG serial interface for more information on JTAG programming). Open Drain – port C pins can be configured in Open Drain mode ● Port C does not support Address Out mode, and therefore no Control register is required. Pin PC7 may be configured as the DBE input in certain MCU bus interfaces. Figure 28. Port C structure DATA OUT REG. D WR 1 SPECIAL FUNCTION PORT C PIN OUTPUT MUX Q DATA OUT MCELLBC[ 7:0] READ MUX INTERNAL DATA BUS P D B DATA IN OUTPUT SELECT ENABLE OUT DIR REG. D WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL Q CPLD-INPUT SPECIAL FUNCTION CONFIGURATION AI02888B BIT 16.22 Port D – functionality and structure Port D has three I/O pins. See Figure 29 and Figure 30. This port does not support Address Out mode, and therefore no Control register is required. port D can be configured to perform one or more of the following functions: ● ● ● ● MCU I/O mode CPLD Output – External Chip Select (ECS0-ECS2) CPLD input – direct input to the CPLD, no input macrocells (IMC) Slew rate – pins can be set up for fast slew rate 76/128 Doc ID 7833 Rev 7 PSD8XXFX I/O ports Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions: ● ● ● Address Strobe (ALE/AS, PD0) CLKIN (PD1) as input to the macrocells flip-flops and APD counter PSD Chip Select input (CSI, PD2). Driving this signal high disables the Flash memory, SRAM and CSIOP. Figure 29. Port D structure DATA OUT REG. DATA OUT D WR PORT D PIN OUTPUT MUX ECS[ 2:0] READ MUX Q INTERNAL DATA BUS P D B DATA IN OUTPUT SELECT DIR REG. D WR Q CPLD - INPUT ENABLE PRODUCT TERM (.OE) AI02889 16.23 External Chip Select The CPLD also provides three External Chip Select (ECS0-ECS2) outputs on port D pins that can be used to select external devices. Each External Chip Select (ECS0-ECS2) consists of one product term that can be configured active high or low. The output enable of the pin is controlled by either the output enable product term or the Direction register (see Figure 30). Doc ID 7833 Rev 7 77/128 I/O ports Figure 30. Port D external Chip Select signals ENABLE (.OE) PSD8XXFX DIRECTION REGISTER PT0 ECS0 POLARITY BIT ENABLE (.OE) DIRECTION REGISTER PD0 PIN CPLD AND ARRAY PLD INPUT BUS PT1 ECS1 POLARITY BIT ENABLE (.OE) DIRECTION REGISTER PD1 PIN PT2 ECS2 PD2 PIN POLARITY BIT AI02890 78/128 Doc ID 7833 Rev 7 PSD8XXFX Power management 17 Power management All PSD devices offer configurable power saving options. These options may be used individually or in combinations, as follows: ● All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory “wakes up”, changes and latches its outputs, then goes back to Standby. The designer does not have to do anything special to achieve memory Standby mode when no inputs are changing—it happens automatically. The PLD sections can also achieve Standby mode when its inputs are not changing, as described in the sections on the Power Management mode registers (PMMR). As with the Power Management mode, the Automatic Power Down (APD) block allows the PSD to reduce to standby current automatically. The APD Unit can also block MCU address/data signals from reaching the memories and PLDs. This feature is available on all the devices of the PSD family. The APD Unit is described in more detail in Section 17.1: Automatic Power-down (APD) Unit and Power-down mode. Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity for a certain time period (MCU is asleep), the APD Unit initiates Power-down mode (if enabled). Once in Power-down mode, all address/data signals are blocked from reaching PSD memory and PLDs, and the memories are deselected internally. This allows the memory and PLDs to remain in Standby mode even if the address/data signals are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states keeps the PLD out of Standby mode, but not the memories. PSD Chip Select input (CSI, PD2) can be used to disable the internal memories, placing them in Standby mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD Unit. There is a slight penalty in memory access time when PSD Chip Select input (CSI, PD2) makes its initial transition from deselected to selected. The PMMRs can be written by the MCU at run-time to manage power. All PSD supports “blocking bits” in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figure 34 and Figure 35). Significant power savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations. PSD devices have a Turbo Bit in PMMR0. This bit can be set to turn the Turbo mode off (the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo mode is on. When the Turbo mode is on, there is a significant DC current component and the AC component is higher. ● ● ● Doc ID 7833 Rev 7 79/128 Power management PSD8XXFX 17.1 Automatic Power-down (APD) Unit and Power-down mode The APD Unit, shown in Figure 31, puts the PSD into Power-down mode by monitoring the activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on Address Strobe (ALE/AS, PD0) stops, a four bit counter starts counting. If Address Strobe (ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down (PDN) goes high, and the PSD enters Power-down mode, as discussed next. Power-down mode By default, if you enable the APD Unit, Power-down mode is automatically enabled. The device enters Power-down mode if Address Strobe (ALE/AS, PD0) remains inactive for fifteen periods of CLKIN (PD1). The following should be kept in mind when the PSD is in Power-down mode: ● If Address Strobe (ALE/AS, PD0) starts pulsing again, the PSD returns to normal operating mode. The PSD also returns to normal operating mode if either PSD Chip Select input (CSI, PD2) is low or the Reset (RESET) input is high. The MCU address/data bus is blocked from all memory and PLDs. Various signals can be blocked (prior to Power-down mode) from entering the PLDs by setting the appropriate bits in the PMMR registers. The blocked signals include MCU control signals and the common CLKIN (PD1). Note that blocking CLKIN (PD1) from the PLDs does not block CLKIN (PD1) from the APD Unit. All PSD memories enter Standby mode and are drawing standby current. However, the PLD and I/O ports blocks do not go into Standby mode because you don’t want to have to wait for the logic and I/O to “wake up” before their outputs can change. See Table 29 for Power-down mode effects on PSD ports. Typical standby current is of the order of microamperes. These standby current values assume that there are no transitions on any PLD input. Power-down mode’s effect on ports Port function Pin level No change No change Undefined Tri-state Tri-state ● ● ● ● Table 29. MCU I/O PLD Out Address Out Data port Peripheral I/O 80/128 Doc ID 7833 Rev 7 PSD8XXFX Figure 31. APD unit APD EN PMMR0 BIT 1=1 TRANSITION DETECTION ALE CLR PD DISABLE BUS INTERFACE Power management RESET CSI CLKIN EDGE DETECT APD COUNTER PD PLD EEPROM SELECT FLASH SELECT SRAM SELECT POWER DOWN (PDN) SELECT DISABLE FLASH/EEPROM/SRAM AI02891 Table 30. Mode Power-down PSD timing and standby current during Power-down mode PLD propagation delay Normal tPD(1) Memory access time No access Access recovery time to normal access tLVDV Typical standby current 5 V VCC 75 µA(2) 3 V VCC 25 µA(2) 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit. 2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is ’0.’ 17.2 For users of the HC11 (or compatible) The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11 (or compatible) in your design, and you wish to use the Power-down mode, you must not connect the E clock to CLKIN (PD1). You should instead connect a crystal oscillator to CLKIN (PD1). The crystal oscillator frequency must be less than 15 times the frequency of AS. The reason for this is that if the frequency is greater than 15 times the frequency of AS, the PSD keeps going into Power-down mode. 17.3 Other power saving options The PSD offers other reduced power saving options that are independent of the Powerdown mode. Except for PSD Chip Select input (CSI, PD2) features, they are enabled by setting bits in PMMR0 and PMMR2. Doc ID 7833 Rev 7 81/128 Power management Figure 32. Enable Power-down flowchart RESET PSD8XXFX Enable APD Set PMMR0 Bit 1 = 1 OPTIONAL Disable desired inputs to PLD by setting PMMR0 bits 4 and 5 and PMMR2 bits 2 through 6. No ALE/AS idle for 15 CLKIN clocks? Yes PSD in Power Down Mode AI02892 17.4 PLD power management The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0. By setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified standby current when the inputs are not switching for an extended time of 70ns. The propagation delay time is increased by 10ns after the Turbo Bit is set to '1' (turned off) when the inputs change at a composite frequency of less than 15 MHz. When the Turbo Bit is reset to '0' (turned on), the PLDs run at full power and speed. The Turbo Bit affects the PLD’s DC power, AC power, and propagation delay. Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power consumption. Table 31. Bit Bit 0 X Power Management mode registers PMMR0(1) Name 0 0= off Description Not used, and should be set to zero. Automatic Power-down (APD) is disabled. Automatic Power-down (APD) is enabled. Not used, and should be set to zero. PLD Turbo mode is on PLD Turbo mode is off, saving power. Bit 1 APD Enable 1= on Bit 2 X 0 0= on Bit 3 PLD Turbo 1= off 82/128 Doc ID 7833 Rev 7 PSD8XXFX Table 31. Bit Power management Power Management mode registers PMMR0(1) (continued) Name 0= on Description CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN (PD1) Powers-up the PLD when Turbo Bit is ’0.’ CLKIN (PD1) input to PLD AND Array is disconnected, saving power. CLKIN (PD1) input to the PLD macrocells is connected. CLKIN (PD1) input to PLD macrocells is disconnected, saving power. Not used, and should be set to zero. Not used, and should be set to zero. Bit 4 PLD Array clk 1= off 0= on Bit 5 PLD MCell clk 1= off Bit 6 Bit 7 X X 0 0 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers. Table 32. Bit Bit 0 Bit 1 Bit 2 X X Power Management mode registers PMMR2(1) Name 0 0 Description Not used, and should be set to zero. Not used, and should be set to zero. PLD Array CNTL0 PLD Array CNTL1 PLD Array CNTL2 PLD Array ALE PLD Array DBE X 0 = on Cntl0 input to the PLD AND Array is connected. 1 = off Cntl0 input to PLD AND Array is disconnected, saving power. 0 = on Cntl1 input to the PLD AND Array is connected. 1 = off Cntl1 input to PLD AND Array is disconnected, saving power. 0 = on Cntl2 input to the PLD AND Array is connected. 1 = off Cntl2 input to PLD AND Array is disconnected, saving power. 0 = on ALE input to the PLD AND Array is connected. 1 = off ALE input to PLD AND Array is disconnected, saving power. 0 = on DBE input to the PLD AND Array is connected. 1 = off DBE input to PLD AND Array is disconnected, saving power. 0 Not used, and should be set to zero. Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers. Doc ID 7833 Rev 7 83/128 Power management PSD8XXFX 17.5 PSD Chip Select input (CSI, PD2) PD2 of port D can be configured in PSDsoft Express as PSD Chip Select input (CSI). When low, the signal selects and enables the internal Flash memory, EEPROM, SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A high on PSD Chip Select input (CSI, PD2) disables the Flash memory, EEPROM, and SRAM, and reduces the PSD power consumption. However, the PLD and I/O signals remain operational when PSD Chip Select input (CSI, PD2) is high. There may be a timing penalty when using PSD Chip Select input (CSI, PD2) depending on the speed grade of the PSD that you are using. See the timing parameter tSLQV in Table 62 or Table 63. 17.6 Input clock The PSD provides the option to turn off CLKIN (PD1) to the PLD to save AC power consumption. CLKIN (PD1) is an input to the PLD AND Array and the Output macrocells (OMC). During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from the PLD AND Array or the macrocells block by setting Bits 4 or 5 to a 1 in PMMR0. 17.7 Input control signals The PSD provides the option to turn off the input control signals (CNTL0, CNTL1, CNTL2, Address Strobe (ALE/AS, PD0) and DBE) to the PLD to save AC power consumption. These control signals are inputs to the PLD AND Array. During Power-down mode, or, if any of them are not being used as part of the PLD logic equation, these control signals should be disabled to save AC power. They are disconnected from the PLD AND Array by setting Bits 2, 3, 4, 5, and 6 to a 1 in PMMR2. Table 33. APD counter operation ALE PD polarity X X 1 0 ALE level X Pulsing 1 0 Not counting Not counting Counting (generates PDN after 15 clocks) Counting (generates PDN after 15 clocks) APD counter APD Enable bit 0 1 1 1 84/128 Doc ID 7833 Rev 7 PSD8XXFX Reset timing and device status at reset 18 18.1 Reset timing and device status at reset Power-up reset Upon Power-up, the PSD requires a Reset (RESET) pulse of duration tNLNH-PO after VCC is steady. During this period, the device loads internal configurations, clears some of the registers and sets the Flash memory into operating mode. After the rising edge of Reset (RESET), the PSD remains in the Reset mode for an additional period, tOPR, before the first memory access is allowed. The Flash memory is reset to the READ mode upon Power-up. Sector Select (FS0-FS7 and CSBOOT0-CSBOOT3) must all be low, Write Strobe (WR, CNTL0) high, during Power On Reset for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of Write Strobe (WR, CNTL0). Any Flash memory WRITE cycle initiation is prevented automatically when VCC is below VLKO. 18.2 Warm reset Once the device is up and running, the device can be reset with a pulse of a much shorter duration, tNLNH. The same tOPR period is needed before the device is operational after warm reset. Figure 33 shows the timing of the Power-up and warm reset. 18.3 I/O pin, register and PLD status at Reset Table 34 shows the I/O pin, register and PLD status during Power On Reset, warm reset and Power-down mode. PLD outputs are always valid during warm reset, and they are valid in Power On Reset once the internal PSD Configuration bits are loaded. This loading of PSD is completed typically long before the VCC ramps up to operating level. Once the PLD is active, the state of the outputs are determined by the PSDabel equations. 18.4 Reset of Flash memory erase and program cycles (on the PSD834Fx) A Reset (RESET) also resets the internal Flash memory state machine. During a Flash memory program or erase cycle, Reset (RESET) terminates the cycle and returns the Flash memory to the Read mode within a period of tNLNH-A. Doc ID 7833 Rev 7 85/128 Reset timing and device status at reset Figure 33. Reset (RESET) timing PSD8XXFX VCC VCC(min) tNLNH tNLNH-A Warm Reset tNLNH-PO Power-On Reset tOPR tOPR RESET AI02866b Table 34. Status during Power-on reset, Warm reset and Power-down mode Power-on reset Input mode Valid after internal PSD configuration bits are loaded Tri-stated Tri-stated Tri-stated Warm reset Input mode Valid Tri-stated Tri-stated Tri-stated Power-down mode Unchanged Depends on inputs to PLD (addresses are blocked in PD mode) Not defined Tri-stated Tri-stated Port configuration MCU I/O PLD Output Address Out Data port Peripheral I/O Register PMMR0 and PMMR2 Macrocells flip-flop status Power-on reset Cleared to '0' Cleared to '0' by internal Power-On Reset Initialized, based on the selection in PSDsoft Configuration menu Cleared to '0' Warm reset Unchanged Depends on .re and .pr equations Initialized, based on the selection in PSDsoft Configuration menu Cleared to '0' Power-down mode Unchanged Depends on .re and .pr equations Unchanged Unchanged VM register(1) All other registers 1. The SR_cod and Periphmode bits in the VM register are always cleared to '0' on Power-on reset or Warm reset. 86/128 Doc ID 7833 Rev 7 PSD8XXFX Programming in-circuit using the JTAG serial interface 19 Programming in-circuit using the JTAG serial interface The JTAG Serial Interface block can be enabled on port C (see Table 35). All memory blocks (primary and secondary Flash memory), PLD logic, and PSD Configuration register bits may be programmed through the JTAG Serial Interface block. A blank device can be mounted on a printed circuit board and programmed using JTAG. The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional signals, TSTAT and TERR, are optional JTAG extensions used to speed up Program and Erase cycles. Note: By default, on a blank PSD (as shipped from the factory or after erasure), four pins on port C are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO. See Application Note AN1153 for more details on JTAG in-system programming (ISP). 19.1 Standard JTAG signals The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are inputs, waiting for a JTAG serial command from an external JTAG controller device (such as FlashLINK or Automated Test Equipment). When the enabling command is received, TDO becomes an output and the JTAG channel is fully functional inside the PSD. The same command that enables the JTAG channel may optionally enable the two additional JTAG signals, TSTAT and TERR. The following symbolic logic equation specifies the conditions enabling the four basic JTAG signals (TMS, TCK, TDI, and TDO) on their respective port C pins. For purposes of discussion, the logic label JTAG_ON is used. When JTAG_ON is true, the four pins are enabled for JTAG. When JTAG_ON is false, the four pins can be used for general PSD I/O. JTAG_ON = PSDsoft_enabled + /* An NVM configuration bit inside the PSD is set by the designer in the PSDsoft Express Configuration utility. This dedicates the pins for JTAG at all times (compliant with IEEE 1149.1 */ Microcontroller_enabled + /* The microcontroller can set a bit at run-time by writing to the PSD register, JTAG Enable. This register is located at address CSIOP + offset C7h. Setting the JTAG_ENABLE bit in this register will enable the pins for JTAG use. This bit is cleared by a PSD reset or the microcontroller. See Table 36 for bit definition. */ PSD_product_term_enabled; /* A dedicated product term (PT) inside the PSD can be used to enable the JTAG pins. This PT has the reserved name JTAGSEL. Once defined as a node in PSDabel, the designer can write an equation for JTAGSEL. This method is used when the port C JTAG pins are multiplexed with other I/O signals. It is recommended to logically tie the node JTAGSEL to the JEN\ signal on the Flashlink cable when multiplexing JTAG signals. See Application Note 1153 for details. */ The state of the PSD Reset (RESET) signal does not interrupt (or prevent) JTAG operations if the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft Express). However, Doc ID 7833 Rev 7 87/128 Programming in-circuit using the JTAG serial interface PSD8XXFX Reset (RESET) will prevent or interrupt JTAG operations if the JTAG enable register is used to enable the JTAG pins. The PSD supports JTAG In-System-Configuration (ISC) commands, but not Boundary Scan. The PSDsoft Express software tool and FlashLINK JTAG programming cable implement the JTAG In-System-Configuration (ISC) commands. A definition of these JTAG In-System-Configuration (ISC) commands and sequences is defined in a supplemental document available from ST. This document is needed only as a reference for designers who use a FlashLINK to program their PSD. 19.2 JTAG extensions TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed Program and Erase cycles by indicating status on PSD signals instead of having to scan the status out serially using the standard JTAG channel. See Application Note AN1153. TERR indicates if an error has occurred when erasing a sector or programming a byte in Flash memory. This signal goes low (active) when an Error condition occurs, and stays low until an “ISC_CLEAR” command is executed or a chip Reset (RESET) pulse is received after an “ISC_DISABLE” command. TSTAT behaves the same as Ready/Busy described in Section 6.3.1: Ready/Busy (PC3). TSTAT is high when the PSD device is in READ mode (primary and secondary Flash memory contents can be read). TSTAT is low when Flash memory program or erase cycles are in progress, and also when data is being written to the secondary Flash memory. TSTAT and TERR can be configured as open-drain type signals during an “ISC_ENABLE” command. This facilitates a wired-OR connection of TSTAT signals from multiple PSD devices and a wired-OR connection of TERR signals from those same devices. This is useful when several PSD devices are “chained” together in a JTAG environment. 19.3 Security and Flash memory protection When the security bit is set, the device cannot be read on a device programmer or through the JTAG port. When using the JTAG port, only a Full Chip Erase command is allowed. All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the part to a non-secured blank state. The Security bit can be set in PSDsoft Express configuration. All primary and secondary Flash memory sectors can individually be sector protected against erasures. The sector protect bits can be set in PSDsoft Express configuration. 88/128 Doc ID 7833 Rev 7 PSD8XXFX Table 35. JTAG port signals Programming in-circuit using the JTAG serial interface Port C pin PC0 PC1 PC3 PC4 PC5 PC6 TMS TCK TSTAT TERR TDI TDO JTAG signals mode Select Clock Status Error flag Description Serial Data In Serial Data Out Doc ID 7833 Rev 7 89/128 Initial delivery state PSD8XXFX 20 Initial delivery state When delivered from ST, the PSD device has all bits in the memory and PLDs set to ’1.’ The PSD Configuration register bits are set to ’0.’ The code, configuration, and PLD logic are loaded using the programming procedure. Information for programming the device is available directly from ST. Please contact your local sales representative. Table 36. Bit JTAG Enable register(1) Name 0= off JTAG port is disabled. JTAG port is enabled. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Description Bit 0 JTAG_Enable 1= on Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 X X X X X X X 0 0 0 0 0 0 0 1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Configuration bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is used to enable the JTAG signals. 90/128 Doc ID 7833 Rev 7 PSD8XXFX Maximum rating 21 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 37. Symbol TSTG TLEAD VIO VCC VPP VESD Storage temperature Lead temperature during soldering (20 seconds max.)(1) Input and output voltage (Q = VOH or Hi-Z) Supply voltage Device programmer supply voltage Electrostatic discharge voltage (human body model) (2) Absolute maximum ratings Parameter Min. –65 Max. 125 235 –0.6 –0.6 –0.6 –2000 7.0 7.0 14.0 2000 Unit °C °C V V V V 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) Doc ID 7833 Rev 7 91/128 AC/DC parameters PSD8XXFX 22 AC/DC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device: ● ● DC electrical specifications AC timing specifications – PLD timings Combinatorial timings Synchronous clock mode Asynchronous clock mode Input macrocell timings – MCU timings READ timings WRITE timings Peripheral mode timings Power-down and Reset timings The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. The following are issues concerning the parameters presented: ● In the DC specification the supply current is given for different modes of operation. Before calculating the total power consumption, determine the percentage of time that the PSD is in each mode. Also, the supply power is considerably different if the Turbo Bit is ’0.’ The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figure 34 and Figure 35 show the PLD mA/MHz as a function of the number of Product Terms (PT) used. In the PLD timing parameters, add the required delay when Turbo Bit is ’0.’ ● ● 92/128 Doc ID 7833 Rev 7 PSD8XXFX Figure 34. PLD ICC /frequency consumption (5 V range) 110 100 90 80 ICC – (mA) 70 FF O AC/DC parameters VCC = 5V ON BO TUR (100 %) 60 TU RB 50 40 30 20 10 0 0 5 TU O ON RBO (25% ) TU O RB OF F PT 100% PT 25% 10 15 20 25 AI02894 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) Figure 35. PLD ICC /frequency consumption (3 V range) 60 VCC = 3V 50 ICC – (mA) 40 T O URB ON ( 100% ) FF 30 O TU 20 10 TURB RB (2 O ON 5%) O TU 0 0 RB 5 O OF F PT 100% PT 25% 10 15 20 25 AI03100 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) Table 38. Example of PSD typical power calculation at VCC=5.0 V (Turbo mode on) (1) Conditions Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory access % SRAM access % I/O access Operational modes % Normal % Power-down mode = 10% = 90% = 8 MHz = 4 MHz = 80% = 15% = 5% (no additional power above base) Doc ID 7833 Rev 7 93/128 AC/DC parameters Table 38. PSD8XXFX Example of PSD typical power calculation at VCC=5.0 V (Turbo mode on) (1) Conditions Number of product terms used (from fitter report) % of total product terms Turbo mode = 45 PT = 45/182 = 24.7% = ON Calculation (using typical values) ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE + %SRAM x 1.5 mA/MHz x Freq ALE + % PLD x 2 mA/MHz x Freq PLD + #PT x 400 µA/PT) = 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz + 2 mA/MHz x 8 MHz + 45 x 0.4 mA/PT) = 45 µA + 0.1 x (8 + 0.9 + 16 + 18 mA) = 45 µA + 0.1 x 42.9 = 45 µA + 4.29 mA = 4.34 mA 1. This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based on IOUT = 0 mA. Table 39. Example of PSD typical power calculation at VCC = 5.0 V (Turbo mode off) (1) Conditions Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory access % SRAM access % I/O access Operational modes % Normal % Power-down mode Number of product terms used = 10% = 90% = 8 MHz = 4 MHz = 80% = 15% = 5% (no additional power above base) 94/128 Doc ID 7833 Rev 7 PSD8XXFX Table 39. AC/DC parameters Example of PSD typical power calculation at VCC = 5.0 V (Turbo mode off) Conditions (from fitter report) % of total product terms Turbo mode = 45 PT = 45/182 = 24.7% = Off Calculation (using typical values) ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE + %SRAM x 1.5mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD)) = 50 µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4 MHz + 0.15 x 1.5mA/MHz x 4 MHz + 24mA) = 45 µA + 0.1 x (8 + 0.9 + 24) = 45 µA + 0.1 x 32.9 = 45 µA + 3.29mA = 3.34mA 1. This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based on IOUT = 0 mA. Table 40. Symbol VCC TA Operating conditions (5 V devices) Parameter Supply voltage Ambient operating temperature (industrial) Ambient operating temperature (commercial) Min. 4.5 –40 0 Max. 5.5 85 70 Unit V °C °C Table 41. Symbol VCC TA Operating conditions (3 V devices) Parameter Supply voltage Ambient operating temperature (industrial) Ambient operating temperature (commercial) Min. 3.0 –40 0 Max. 3.6 85 70 Unit V °C °C Doc ID 7833 Rev 7 95/128 AC/DC parameters Table 42. AC signal letters for PLD timing(1) Signal description Address input CEout output Input data E output Internal WDOG_ON signal Interrupt input ALE input RESET input or output Port signal output Output data WR, UDS, LDS, DS, IORD, PSEN inputs Chip Select input R/W input Internal PDN signal Output macrocell PSD8XXFX Letter A C D E G I L N P Q R S T W M 1. Example: tAVLX = time from address valid to ALE invalid. Table 43. AC signal behavior symbols for PLD timing(1) AC signal description Time Logic level low or ALE Logic level high Valid No longer a valid logic level(2) Float Pulse width Letter t L H V X Z PW 1. Example: tAVLX = time from address valid to ALE invalid. 2. Output Hi-Z is defined as the point where data out is no longer driven. Table 44. Symbol CL AC measurement conditions Parameter Load capacitance Min. 30 Max. Unit pF 96/128 Doc ID 7833 Rev 7 PSD8XXFX Table 45. Symbol CIN COUT CVPP AC/DC parameters Capacitance(1) Parameter Input capacitance (for input pins) Output capacitance (for input/output pins) Capacitance (for CNTL2/VPP) Test condition VIN = 0V VOUT = 0V VPP = 0V Typ.(2) 4 8 18 Max. 6 12 25 Unit pF pF pF 1. Sampled only, not 100% tested. 2. Typical values are for TA = 25°C and nominal supply voltages. Figure 36. AC measurement I/O waveform 3.0V Test Point 0V AI03103b 1.5V Figure 37. AC measurement load circuit 2.01 V 195 Ω Device Under Test CL = 30 pF (Including Scope and Jig Capacitance) AI03104b Figure 38. Switching waveforms – key 2.01 V 195 Ω Device Under Test CL = 30 pF (Including Scope and Jig Capacitance) AI03104b Doc ID 7833 Rev 7 97/128 AC/DC parameters Table 46. Symbol PSD8XXFX DC characteristics (5 V devices) Test condition Parameter (in addition to those in Table 40) 4.5 V < VCC < 5.5 V 4.5 V < VCC < 5.5 V (1) (1) Min. Typ. Max. Unit VIH VIL VIH1 VIL1 VHYS VLKO VOL Input high voltage Input low voltage Reset high level input voltage Reset low level input voltage Reset pin hysteresis VCC (min) for Flash Erase and Program Output low voltage 2 –0.5 0.8VCC –0.5 0.3 2.5 VCC +0.5 0.8 VCC +0.5 0.2VCC – 0.1 V V V V V 4.2 0.01 0.25 0.1 0.45 V V V V V IOL = 20 µA, VCC = 4.5 V IOL = 8 mA, VCC = 4.5 V VOH ISB ILI ILO Output high voltage Standby supply current for Power-down mode input leakage current Output leakage current IOH = –20 µA, VCC = 4.5 V IOH = –2 mA, VCC = 4.5 V CSI >VCC –0.3 V(2)(3) VSS < VIN < VCC 0.45 < VOUT < VCC PLD_TURBO = off, f = 0 MHz(4) 4.4 2.4 4.49 3.9 50 200 1 10 µA µA µA µA/PT –1 –10 ±0.1 ±5 0 400 15 0 0 PLD only ICC (DC)(4) Operating supply current Flash memory PLD_TURBO = on, f = 0 MHz During Flash memory WRITE/Erase only Read only, f = 0 MHz SRAM PLD AC adder ICC (AC)(4) Flash memory AC adder SRAM AC adder 2.5 1.5 f = 0 MHz 700 30 0 0 (5) µA/PT mA mA mA 3.5 3.0 mA/MHz mA/MHz 1. Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC. 2. CSI deselected or internal Power-down mode is active. 3. PLD is in non-Turbo mode, and none of the inputs are switching. 4. IOUT = 0 mA 5. Please see Figure 34 for the PLD current calculation. 98/128 Doc ID 7833 Rev 7 PSD8XXFX Table 47. Symbol VIH VIL VIH1 VIL1 VHYS VLKO VOL AC/DC parameters DC Characteristics (3 V devices) Parameter Conditions 3.0 V < VCC < 3.6 V 3.0 V < VCC < 3.6 V (1) (1) Min. 0.7VCC –0.5 0.8VCC –0.5 0.3 1.5 Typ. Max. VCC +0.5 0.8 VCC +0.5 0.2VCC – 0.1 Unit V V V V V High level input voltage Low level input voltage Reset high level input voltage Reset low level input voltage Reset pin hysteresis VCC (min) for Flash Erase and Program Output low voltage 2.2 0.01 0.15 0.1 0.45 V V V V V IOL = 20 µA, VCC = 3.0 V IOL = 4 mA, VCC = 3.0 V VOH ISB ILI ILO Output high voltage Standby supply current for Power-down mode Input leakage current Output leakage current IOH = –20 µA, VCC = 3.0 V IOH = –1 mA, VCC = 3.0 V CSI >VCC –0.3 V(2)(3) VSS < VIN < VCC 0.45 < VIN < VCC PLD_TURBO = off, f = 0 MHz(3) 2.9 2.7 2.99 2.8 25 100 1 10 µA µA µA µA/PT –1 –10 ±0.1 ±5 0 200 10 0 0 (5) PLD only ICC (DC)(4) Operating supply current Flash memory PLD_TURBO = on, f = 0 MHz During Flash memory WRITE/Erase only Read only, f = 0 MHz SRAM PLD AC adder ICC (AC)(4) Flash memory AC adder SRAM AC adder f = 0 MHz 400 25 0 0 µA/PT mA mA mA 1.5 0.8 2.0 1.5 mA/MHz mA/MHz 1. Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC. 2. CSI deselected or internal Power-down mode is active. 3. PLD is in non-Turbo mode, and none of the inputs are switching. 4. IOUT = 0 mA 5. Please see Figure 35 for the PLD current calculation. Doc ID 7833 Rev 7 99/128 AC/DC parameters Figure 39. Input to output disable / enable INPUT PSD8XXFX tER INPUT TO OUTPUT ENABLE/DISABLE tEA AI02863 Table 48. Symbol CPLD combinatorial timing (5 V devices) -70 Parameter CPLD input pin/feedback to CPLD combinatorial output CPLD input to CPLD output enable CPLD input to CPLD output disable CPLD register clear or preset delay CPLD register clear or preset pulse width CPLD array delay Any macrocell 10 11 Conditions Min Max Min Max Min Max -90 -15 Fast PT Aloc Turbo off Slew rate (1) Unit tPD 20 25 32 +2 + 10 –2 ns tEA tER tARP tARPW tARD 21 21 21 20 26 26 26 29 16 32 32 33 + 10 + 10 + 10 + 10 –2 –2 –2 ns ns ns ns ns 22 +2 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. Table 49. Symbol CPLD combinatorial timing (3 V devices) -12 Parameter CPLD input pin/feedback to CPLD combinatorial output CPLD input to CPLD output enable CPLD input to CPLD output disable CPLD register clear or preset delay Conditions Min Max Min Max Min Max -15 -20 PT Turbo Aloc off Slew rate (1) Unit tPD 40 45 50 +4 + 20 –6 ns tEA tER tARP 43 43 40 45 45 43 50 50 48 + 20 + 20 + 20 –6 –6 –6 ns ns ns 100/128 Doc ID 7833 Rev 7 PSD8XXFX Table 49. Symbol AC/DC parameters CPLD combinatorial timing (3 V devices) (continued) -12 Parameter Conditions Min Max Min Max Min Max -15 -20 PT Turbo Aloc off + 20 33 +4 Slew rate (1) Unit tARPW tARD CPLD register clear or preset pulse width CPLD array delay Any macrocell 25 25 30 29 35 ns ns 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. Figure 40. Synchronous clock mode timing – PLD tCH tCL CLKIN tS INPUT tH tCO REGISTERED OUTPUT AI02860 Table 50. Symbol CPLD macrocell Synchronous clock mode timing (5 V devices) -70 Parameter Conditions Min Maximum frequency External feedback Max Min Max Min Max -90 -15 Fast Turbo Slew PT rate off (1) Aloc Unit 1/(tS+tCO) 40.0 30.30 25.00 MHz fMAX Maximum frequency Internal feedback (fCNT) Maximum frequency Pipelined data 1/(tS+tCO–10) 66.6 43.48 31.25 MHz 1/(tCH+tCL) 12 0 Clock input Clock input Clock input 6 6 83.3 15 0 10 10 13 50.00 20 0 15 15 18 35.71 +2 + 10 MHz ns ns ns ns tS tH tCH tCL tCO Input setup time Input hold time Clock high time Clock low time Clock to output delay 22 –2 ns Doc ID 7833 Rev 7 101/128 AC/DC parameters Table 50. Symbol PSD8XXFX CPLD macrocell Synchronous clock mode timing (5 V devices) (continued) -70 Parameter Conditions Min Max 11 12 20 Min Max 16 30 Min Max 22 -90 -15 Fast Turbo Slew PT rate off (1) Aloc +2 Unit tARD tMIN CPLD array delay Minimum clock period(2) Any macrocell tCH+tCL ns ns 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. 2. CLKIN (PD1) tCLCL = tCH + tCL. Table 51. Symbol CPLD macrocell synchronous clock mode timing (3 V devices) -12 Parameter Maximum frequency External feedback Maximum frequency Internal feedback (fCNT) Maximum frequency Pipelined data Conditions Min Max Min Max Min Max -15 -20 PT Aloc Turbo Slew rate off (1) Unit 1/(tS+tCO) 22.2 18.8 15.8 MHz fMAX 1/(tS+tCO–10) 28.5 23.2 18.8 MHz 1/(tCH+tCL) 20 0 Clock input Clock input Clock input Any macrocell tCH+tCL 25 15 10 40.0 25 0 15 15 25 25 29 33.3 30 0 16 16 28 29 32 31.2 +4 + 20 MHz ns ns ns ns tS tH tCH tCL tCO tARD tMIN Input setup time Input hold time Clock high time Clock low time Clock to output delay CPLD array delay Minimum clock period(2) 33 33 +4 –6 ns ns ns 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. 2. CLKIN (PD1) tCLCL = tCH + tCL. 102/128 Doc ID 7833 Rev 7 PSD8XXFX Figure 41. Asynchronous Reset / Preset tARPW AC/DC parameters RESET/PRESET INPUT tARP REGISTER OUTPUT AI02864 Figure 42. Asynchronous Clock mode Timing (product term clock) tCHA tCLA CLOCK tSA tHA INPUT tCOA REGISTERED OUTPUT AI02859 Table 52. Symbol CPLD macrocell asynchronous clock mode timing (5 V devices) -70 Parameter Maximum frequency External feedback Maximum frequency Internal feedback (fCNTA) Maximum frequency Pipelined data Conditions Min Max Min Max Min Max -90 -15 PT Turbo Slew Aloc off rate Unit 1/(tSA+tCOA) 38.4 26.32 21.27 MHz fMAXA 1/(tSA+tCOA–10) 62.5 35.71 27.78 MHz 1/(tCHA+tCLA) 71.4 41.67 35.71 MHz tSA tHA tCHA tCLA Input setup time Input hold time Clock input high time Clock input low time 7 8 9 9 8 12 12 12 12 14 15 15 +2 + 10 ns ns + 10 + 10 ns ns Doc ID 7833 Rev 7 103/128 AC/DC parameters Table 52. Symbol PSD8XXFX CPLD macrocell asynchronous clock mode timing (5 V devices) (continued) -70 Parameter Clock to output delay CPLD array delay Minimum clock period Any macrocell 1/fCNTA 16 Conditions Min Max 21 11 28 Min Max 30 16 39 Min Max 37 22 +2 -90 -15 PT Turbo Slew Aloc off rate + 10 –2 Unit tCOA tARDA tMINA ns ns ns Table 53. Symbol CPLD macrocell Asynchronous clock mode timing (3 V devices) -12 Parameter Maximum frequency External feedback Maximum frequency Internal feedback (fCNTA) Maximum frequency Pipelined data Conditions Min Max Min Max Min Max -15 -20 PT Turbo Slew rate Aloc off Unit 1/(tSA+tCOA) 21.7 19.2 16.9 MHz fMAXA 1/(tSA+tCOA–10) 27.8 23.8 20.4 MHz 1/(tCHA+tCLA) 10 12 17 13 33.3 12 15 22 15 36 27 13 17 25 16 40 29 42 49 24.4 +4 + 20 MHz ns ns + 20 + 20 ns ns –6 ns ns ns tSA tHA tCHA tCLA tCOA tARD tMINA Input setup time Input hold time Clock high time Clock low time Clock to output delay CPLD array delay Minimum clock period Any macrocell 1/fCNTA 46 33 +4 + 20 25 36 104/128 Doc ID 7833 Rev 7 PSD8XXFX Figure 43. Input macrocell timing (product term clock) t INH PT CLOCK AC/DC parameters t INL t IS INPUT t IH OUTPUT t INO AI03101 Table 54. Symbol tIS tIH tINH tINL tINO Input macrocell timing (5 V devices) -70 Parameter Input setup time Input hold time NIB input high time NIB input low time NIB input to combinatorial delay Conditions Min Max Min Max Min Max (1) (1) (1) (1) (1) -90 -15 PT Aloc Turbo off Unit ns 0 15 9 9 34 0 20 12 12 46 0 26 18 18 59 +2 + 10 + 10 ns ns ns ns 1. Inputs from port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX. Table 55. Symbol tIS tIH tINH tINL tINO input macrocell timing (3 V devices) -12 Parameter Input setup time Input hold time NIB input high time NIB input low time NIB input to combinatorial delay Conditions Min Max Min Max Min Max (1) (1) (1) (1) (1) -15 -20 PT Aloc Turbo off Unit ns 0 25 12 12 46 0 25 13 13 62 0 30 15 15 70 +4 + 20 + 20 ns ns ns ns 1. Inputs from port A, B, and C relative to register/ latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX. Doc ID 7833 Rev 7 105/128 AC/DC parameters Figure 44. READ timing tAVLX ALE/AS tLVLX A /D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS tSLQV CSI tRLQV tRLRH RD (PSEN, DS) tRHQZ tRHQX ADDRESS VALID tAVQV ADDRESS VALID DATA VALID tLXAX PSD8XXFX 1 DATA VALID tEHEL E tTHEH tELTL R /W tAVPV ADDRESS OUT AI02895 1. tAVLX and tLXAX are not required for 80C251 in Page mode or 80C51XA in Burst mode. Table 56. Symbol tLVLX tAVLX tLXAX tAVQV tSLQV tRLQV tRHQX tRLRH tRHQZ tEHEL READ timing (5 V devices) -70 Parameter ALE or AS pulse width Address setup time Address hold time Address valid to data valid CS valid to data valid RD to data valid 8-bit bus RD or PSEN to data valid 8-bit bus, 8031, 80251 RD data hold time RD pulse width RD to data high-Z E pulse width (2) (3) (4) (4) (4) (1) (1) (1) -90 -15 Conditions Min Max Min Max Min Max 15 4 7 70 75 24 31 0 27 20 27 32 0 32 25 38 20 6 8 90 100 32 38 0 38 30 28 10 11 150 150 40 45 Turbo off Unit ns ns ns + 10 ns ns ns ns ns ns ns ns 106/128 Doc ID 7833 Rev 7 PSD8XXFX Table 56. Symbol tTHEH tELTL tAVPV AC/DC parameters READ timing (5 V devices) (continued) -70 Parameter Conditions Min Max Min Max Min Max 6 0 (5) -90 -15 Turbo off Unit ns ns R/W setup time to Enable R/W hold time After Enable Address input valid to Address output delay 10 0 20 25 18 0 30 ns 1. Any input used to select an internal PSD function. 2. RD timing has the same timing as DS, LDS, and UDS signals. 3. RD and PSEN have the same timing. 4. RD timing has the same timing as DS, LDS, UDS, and PSEN signals. 5. In multiplexed mode, latched addresses generated from ADIO delay to address output on any port. Table 57. Symbol tLVLX tAVLX tLXAX tAVQV tSLQV tRLQV tRHQX tRLRH tRHQZ tEHEL tTHEH tELTL tAVPV READ timing (3 V devices) -12 Parameter ALE or AS pulse width Address setup time Address hold time Address valid to data valid CS valid to data valid RD to data valid 8-bit bus RD or PSEN to data valid 8-bit bus, 8031, 80251 RD data hold time RD pulse width RD to data high-Z E pulse width R/W setup time to enable R/W hold time after enable Address input valid to address output delay (5) (4) (2) (3) (4) (1) (1) (1) -15 -20 Conditions Min Max Min Max Min Max 26 9 9 120 120 35 45 0 38 38 40 15 0 33 45 18 0 35 0 40 40 52 20 0 40 26 10 12 150 150 35 50 0 45 45 30 12 14 200 200 40 55 Turbo off Unit ns ns ns + 20 ns ns ns ns ns ns ns ns ns ns ns 1. Any input used to select an internal PSD function. 2. RD timing has the same timing as DS, LDS, and UDS signals. 3. RD and PSEN have the same timing for 8031. 4. RD timing has the same timing as DS, LDS, UDS, and PSEN signals. 5. In multiplexed mode latched address generated from ADIO delay to address output on any port. Doc ID 7833 Rev 7 107/128 AC/DC parameters Figure 45. WRITE timing tAVLX ALE/AS t LVLX A /D MULTIPLEXED BUS ADDRESS VALID tAVWL ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS tSLWL CSI tDVWH WR (DS) t WLWH t WHDX t WHAX ADDRESS VALID DATA VALID DATA VALID t LXAX PSD8XXFX t EHEL E t THEH R/ W t WLMV tAVPV ADDRESS OUT t WHPV STANDARD MCU I/O OUT t ELTL AI02896 Table 58. Symbol tLVLX tAVLX tLXAX tAVWL tSLWL tDVWH tWHDX tWLWH tWHAX1 tWHAX2 WRITE timing (5 V devices) -70 Parameter ALE or AS pulse width Address setup time Address hold time Address valid to leading edge of WR CS valid to leading edge of WR WR data setup time WR data hold time WR pulse widthpulse width Trailing edge of WR to address invalid Trailing edge of WR to DPLD address invalid (1) (1) (1)(2) (2) (2) (2) (2) (2) (2)(3) -90 -15 Unit Conditions Min Max Min Max Min Max 15 4 7 8 12 25 4 31 6 0 20 6 8 15 15 35 5 35 8 0 28 10 11 20 20 45 5 45 10 0 ns ns ns ns ns ns ns ns ns ns 108/128 Doc ID 7833 Rev 7 PSD8XXFX Table 58. Symbol AC/DC parameters WRITE timing (5 V devices) (continued) -70 Parameter Conditions Min Max Min Max Min Max -90 -15 Unit tWHPV Trailing edge of WR to port output valid using I/O port data register Data valid to port output valid using macrocell register Preset/Clear Address input valid to address output delay WR valid to port output valid using macrocell register Preset/Clear (2) 27 30 38 ns tDVMV (2)(4) 42 55 65 ns tAVPV tWLMV (5) 20 48 25 55 30 65 ns ns (2)(6) 1. Any input used to select an internal PSD function. 2. WR has the same timing as E, LDS, UDS, WRL, and WRH signals. 3. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory. 4. Assuming WRITE is active before data becomes valid. 5. In multiplexed mode, latched address generated from ADIO delay to address output on any port. 6. Assuming data is stable before active WRITE signal. Table 59. Symbol tLVLX tAVLX tLXAX tAVWL tSLWL tDVWH tWHDX tWLWH tWHAX1 tWHAX2 tWHPV tDVMV WRITE timing (3 V devices) -12 Parameter ALE or AS pulse width Address setup time Address hold time Address valid to Leading Edge of WR CS valid to Leading Edge of WR WR data setup time WR data hold time WR pulse width Trailing edge of WR to address invalid Trailing edge of WR to DPLD address invalid Trailing edge of WR to port output valid using I/O port data register Data valid to port output valid using macrocell register Preset/Clear (1) (1) (1)(2) (2) (2) (2) (2) (2) (2)(3) -15 -20 Unit Conditions Min Max Min Max Min Max 26 9 9 17 17 45 7 46 10 0 33 70 26 10 12 20 20 45 8 48 12 0 35 70 30 12 14 25 25 50 10 53 17 0 40 80 ns ns ns ns ns ns ns ns ns ns ns (2) (2)(4) Doc ID 7833 Rev 7 109/128 AC/DC parameters Table 59. Symbol tAVPV tWLMV PSD8XXFX WRITE timing (3 V devices) (continued) -12 Parameter Address input valid to address output delay WR valid to port output valid using macrocell register Preset/Clear Conditions Min Max Min Max Min Max (5) (2)(6) -15 -20 Unit 33 70 35 70 40 80 ns ns 1. Any input used to select an internal PSD function. 2. WR has the same timing as E, LDS, UDS, WRL, and WRH signals. 3. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory. 4. Assuming WRITE is active before data becomes valid. 5. In multiplexed mode, latched address generated from ADIO delay to address output on any port. 6. Assuming data is stable before active WRITE signal. Table 60. Symbol Program, WRITE and Erase times (5 V devices) Parameter Flash Program Flash Bulk Erase (pre-programmed)(1) Min. Typ. 8.5 3 5 1 2.2 14 100,000 100 polling)(2) 30 1200 30 30 Max. Unit s s s s s µs cycles µs ns Flash Bulk Erase (not pre-programmed) tWHQV3 tWHQV2 tWHQV1 Sector Erase (pre-programmed) Sector Erase (not pre-programmed) Byte Program Program/Erase cycles (per sector) tWHWLO tQ7VQV Sector Erase timeout DQ7 valid to output (DQ7-DQ0) valid (data 1. The whole memory is programmed to 00h before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. Table 61. Symbol Program, WRITE and Erase times (3 V devices) Parameter Flash Program Flash Bulk Erase (pre-programmed)(1) Flash Bulk Erase (not pre-programmed) Min. Typ. 8.5 3 5 1 2.2 14 100,000 100 30 1200 30 30 Max. Unit s s s s s µs cycles µs ns tWHQV3 tWHQV2 tWHQV1 Sector Erase (pre-programmed) Sector Erase (not pre-programmed) Byte Program Program / Erase Cycles (per sector) tWHWLO tQ7VQV Sector Erase timeout DQ7 valid to Output (DQ7-DQ0) valid (data polling)(2) 110/128 Doc ID 7833 Rev 7 PSD8XXFX AC/DC parameters 1. The whole memory is programmed to 00h before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. Figure 46. Peripheral I/O READ timing ALE/AS A /D BUS ADDRESS DATA VALID tAVQV (PA) tSLQV (PA) CSI tRLQV (PA) RD tRLRH (PA) tQXRH (PA) tRHQZ (PA) tDVQV (PA) DATA ON PORT A AI02897 Table 62. Symbol tAVQV–PA tSLQV–PA tRLQV–PA tDVQV–PA tQXRH–PA tRLRH–PA tRHQZ–PA Port A Peripheral Data mode READ timing (5 V devices) -70 Parameter Address valid to data valid CSI valid to data valid RD to data valid RD to data valid 8031 mode Data In to data out valid RD data hold time RD pulse width RD to data high-Z (2) (2) (2)(3) -90 -15 Conditions Min Max Min Max Min Max (1) Turbo off + 10 + 10 Unit ns ns ns ns ns ns ns 37 27 21 32 22 0 27 23 0 32 39 35 32 38 30 0 38 25 45 45 40 45 38 30 ns 1. Any input used to select port A Data Peripheral mode. 2. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode). 3. Data is already stable on port A. Doc ID 7833 Rev 7 111/128 AC/DC parameters Table 63. Symbol tAVQV–PA tSLQV–PA tRLQV–PA tDVQV–PA tQXRH–PA tRLRH–PA tRHQZ–PA PSD8XXFX Port A Peripheral Data mode READ timing (3V devices) -12 Parameter Address valid to data valid CSI valid to data valid RD to data valid RD to data valid 8031 mode Data In to data Out valid RD data hold time RD pulse width RD to data high-Z (2) (2) (2)(3) -15 -20 Conditions Min Max Min Max Min Max (1) Turbo off + 20 + 20 Unit ns ns ns ns ns ns ns 50 37 37 45 38 0 36 36 0 36 50 45 40 45 40 0 46 40 50 50 45 50 45 45 ns 1. Any input used to select port A Data Peripheral mode. 2. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode). 3. Data is already stable on port A. Figure 47. Peripheral I/O WRITE timing ALE/AS A / D BUS ADDRESS DATA OUT tWLQV WR (PA) tWHQZ (PA) tDVQV (PA) PORT A DATA OUT AI02898 Table 64. Symbol tWLQV–PA tDVQV–PA tWHQZ–PA Port A Peripheral Data mode WRITE timing (5 V devices) -70 Parameter WR to data propagation delay Data to port A data propagation delay WR invalid to port A tri-state Conditions Min Max Min Max Min Max (1) (2) (1) -90 -15 Unit 25 22 20 35 30 25 40 38 33 ns ns ns 1. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals. 2. Data stable on ADIO pins to data on port A. 112/128 Doc ID 7833 Rev 7 PSD8XXFX Table 65. Symbol tWLQV–PA tDVQV–PA tWHQZ–PA AC/DC parameters Port A Peripheral Data mode WRITE timing (3 V devices) -12 Parameter WR to data propagation delay Data to port A data propagation delay WR invalid to port A tri-state Conditions Min Max Min Max Min Max (1) (2) (1) -15 -20 Unit 42 38 33 45 40 33 55 45 35 ns ns ns 1. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals. 2. Data stable on ADIO pins to data on port A. Figure 48. Reset (RESET) timing VCC VCC(min) tNLNH tNLNH-A Warm Reset tNLNH-PO Power-On Reset tOPR tOPR RESET AI02866b Table 66. Symbol tNLNH tNLNH–PO tNLNH–A tOPR Reset (RESET) timing (5 V devices) Parameter RESET active low time(1) Power-on Reset active low time Warm Reset (on the PSD834Fx)(2) Conditions Min 150 1 25 120 Max Unit ns ms µs ns RESET high to operational device 1. Reset (RESET) does not reset Flash memory program or erase cycles. 2. Warm reset aborts Flash memory program or erase cycles, and puts the device in READ mode. Table 67. Symbol tNLNH tNLNH–PO tNLNH–A tOPR Reset (RESET) timing (3 V devices) Parameter RESET active low time(1) Power-on Reset active low time Warm Reset (on the PSD834Fx)(2) RESET high to operational device Conditions Min 300 1 25 300 Max Unit ns ms µs ns 1. Reset (RESET) does not reset Flash memory program or erase cycles. 2. Warm reset aborts Flash memory program or erase cycles, and puts the device in READ mode. Doc ID 7833 Rev 7 113/128 AC/DC parameters Figure 49. ISC timing t I SCCH TCK PSD8XXFX t ISCCL t ISCPSU t ISCPH TDI/TMS t ISCPZV t ISCPCO ISC OUTPUTS/TDO t ISCPVZ ISC OUTPUTS/TDO AI02865 Table 68. Symbol ISC timing (5 V devices) -70 Parameter Clock (TCK, PC1) frequency (except for PLD) Clock (TCK, PC1) high time (except for PLD) Clock (TCK, PC1) low time (except for PLD) Clock (TCK, PC1) frequency (PLD only) Clock (TCK, PC1) high time (PLD only) Clock (TCK, PC1) low time (PLD only) ISC port setup time ISC port hold up time ISC port clock to output ISC port high-impedance to valid output ISC port valid output to high-Impedance Conditions Min Max Min Max Min Max -90 -15 Unit tISCCF tISCCH tISCCL tISCCFP tISCCHP tISCCLP tISCPSU tISCPH tISCPCO tISCPZV tISCPVZ (1) 20 23 23 2 240 240 7 5 21 21 21 240 240 8 5 26 26 18 31 31 2 240 240 10 5 23 23 23 14 MHz ns ns (1) (1) (2) (2) (2) 2 MHz ns ns ns ns 25 25 25 ns ns ns 1. For non-PLD Programming, Erase or in ISC by-pass mode. 2. For program or erase PLD only. 114/128 Doc ID 7833 Rev 7 PSD8XXFX Table 69. Symbol AC/DC parameters ISC timing (3 V devices) -12 Parameter Conditions Min Max Min Max Min Max -15 -20 Unit tISCCF tISCCH tISCCL tISCCFP tISCCHP tISCCLP tISCPSU tISCPH tISCPCO tISCPZV tISCPVZ Clock (TCK, PC1) frequency (except for PLD) Clock (TCK, PC1) high time (except for PLD) Clock (TCK, PC1) low time (except for PLD) Clock (TCK, PC1) frequency (PLD only) Clock (TCK, PC1) high time (PLD only) Clock (TCK, PC1) low time (PLD only) ISC port setup time ISC port hold up time ISC port clock to output ISC port high-Impedance to valid Output ISC port valid Output to high-Impedance (1) 12 40 40 2 240 240 12 5 30 30 30 240 240 13 5 45 45 10 51 51 2 240 240 15 5 36 36 36 9 MHz ns ns (1) (1) (2) (2) (2) 2 MHz ns ns ns ns 40 40 40 ns ns ns 1. For non-PLD Programming, Erase or in ISC by-pass mode. 2. For program or erase PLD only. Table 70. Symbol tLVDV tCLWH Power-down timing (5 V devices) -70 Parameter ALE access time from Power-down Maximum delay from APD Enable to Internal PDN valid signal Using CLKIN (PD1) Conditions Min Max Min Max Min Max 80 90 15 * tCLCL(1) 150 ns µs -90 -15 Unit 1. tCLCL is the period of CLKIN (PD1). Table 71. Symbol tLVDV tCLWH Power-down timing (3 V devices) -12 Parameter ALE access time from Power-down Maximum Delay from APD Enable to Internal PDN valid Signal Using CLKIN (PD1) Conditions Min Max Min Max Min Max 145 150 15 * tCLCL(1) 200 ns µs -15 -20 Unit 1. tCLCL is the period of CLKIN (PD1). Doc ID 7833 Rev 7 115/128 Package mechanical PSD8XXFX 23 Package mechanical In order to meet environmental requirements, ST offers this device in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 116/128 Doc ID 7833 Rev 7 PSD8XXFX Package mechanical Figure 50. PQFP52 - 52-pin plastic quad flat package mechanical drawing D D1 D2 A2 e Ne E2 E1 E b N 1 Nd L1 A CP c QFP-A A1 α L 1. Drawing is not to scale. Table 72. Symbol PQFP52 - 52-pin plastic quad flat package mechanical dimensions mm Typ. Min. Max. 2.350 0.250 2.000 1.800 0.220 0.110 13.200 10.000 7.800 13.200 10.000 7.800 0.650 0.880 1.600 13.150 9.950 – 13.150 9.950 – – 0.730 – 0° 52 13 13 0.100 2.100 0.380 0.230 13.250 10.050 – 13.250 10.050 – – 1.030 – 7° 0.5200 0.3940 0.3070 0.5200 0.3940 0.3070 0.0260 0.0350 0.0630 0° 52 13 13 0.0040 7° 0.0290 0.0410 0.0790 0.0770 0.0090 0.0040 0.5180 0.3920 – 0.5180 0.3920 – Typ. inches Min. Max. 0.0930 0.0100 0.0830 0.0150 0.0090 0.5220 0.3960 – 0.5220 0.3960 – A A1 A2 b c D D1 D2 E E1 E2 e L L1 α N Nd Ne CP Doc ID 7833 Rev 7 117/128 Package mechanical PSD8XXFX Figure 51. PLCC52 - 52-lead plastic lead chip carrier package mechanical drawing D D1 M 1N A1 A2 M1 b1 E1 E D2/E2 D3/E3 b L1 L C A CP e PLCC-B 1. Drawing is not to scale. Table 73. Symbol PLCC52-52-lead plastic lead chip carrier mechanical dimensions mm Typ. Min. 4.190 2.540 – 0.330 0.660 0.2460 19.940 19.050 17.530 19.940 19.050 17.530 1.270 0.890 – – 52 13 13 Max. 4.570 2.790 0.910 0.530 0.810 0.2610 20.190 19.150 18.540 20.190 19.150 18.540 – – 0.050 0.035 Typ. inches Min. 0.1650 0.1000 – 0.0130 0.0260 0.0097 0.7850 0.7500 0.6900 0.7850 0.7500 0.6900 – – 52 13 13 Max. 0.1800 0.1100 0.0360 0.0210 0.0320 0.0103 0.7950 0.7540 0.7300 0.7950 0.7540 0.7300 – – A A1 A2 B B1 C D D1 D2 E E1 E2 e R N Nd Ne 118/128 Doc ID 7833 Rev 7 PSD8XXFX Package mechanical Figure 52. TQFP64 - 64-lead thin quad flatpack, package outline D D1 D2 A2 e Ne E2 E1 E b N 1 Nd L1 A CP c QFP-A A1 α L 1. Drawing is not to scale. Table 74. Symb. TQFP64 - 64-lead thin quad flatpack, package mechanical data mm Typ. Min. 1.420 0.100 1.400 3.5° 0.350 0.070 1.360 0.0° 0.330 Max. 1.540 0.140 1.440 7.0° 0.380 0.170 16.000 14.000 12.000 16.000 14.000 12.000 0.800 0.600 1.000 0.100 64 16 16 15.900 13.980 11.950 15.900 13.980 11.950 0.750 0.450 0.940 16.100 14.030 12.050 16.100 14.030 12.050 0.850 0.750 1.060 0.6300 0.5510 0.4720 0.6300 0.5510 0.4720 0.0310 0.0240 0.0390 0.0040 64 16 16 0.6260 0.5500 0.4700 0.6260 0.5500 0.4700 0.0300 0.0180 0.0370 0.0040 0.0550 3.5° 0.0140 Typ. inches Min. 0.0560 0.0030 0.0540 0.0° 0.0130 Max. 0.0610 0.0050 0.0570 7.0° 0.0150 0.006 0.6340 0.5520 0.4740 0.6340 0.5520 0.4740 0.0330 0.0300 0.0420 A A1 A2 a b c D D1 D2 E E1 E2 e L L1 CP N Nd Ne Doc ID 7833 Rev 7 119/128 Part numbering PSD8XXFX 24 Table 75. Example: Part numbering Ordering information scheme PSD8 1 3 F 2 V A – 15 J 1 T Device Type PSD8 = 8-bit PSD with register Logic SRAM Capacity 1 = 16 Kbit 3 = 64 Kbit 5 = 256 Kbit Flash Memory Capacity 3 = 1 Mbit (128K x 8) 4 = 2 Mbit (256K x 8) 2nd Flash Memory 2 = 256 Kbit Flash memory + SRAM 3 = SRAM but no Flash memory 4 = 256 Kbit Flash memory but no SRAM 5 = no Flash memory + no SRAM Operating voltage blank = VCC = 4.5 to 5.5V V = VCC = 3.0 to 3.6V Silicon Revision A = Revision A Speed 70 = 70ns 90 = 90ns 12 = 120ns 15 = 150ns 20 = 200ns Package J = ECOPACK-compliant PLCC52 M = ECOPACK-compliant PQFP52 U =ECOPACK-compliant TQFP64 Temperature Range blank = 0 to 70°C (commercial) I = –40 to 85°C (industrial) Option T = Tape & Reel Packing For a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 120/128 Doc ID 7833 Rev 7 PSD8XXFX PQFP52 pin assignments Appendix A Table 76. PQFP52 pin assignments PQFP52 connections (see Features) Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin assignments PD2 PD1 PD0 PC7 PC6 PC5 PC4 VCC GND PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 GND PA2 PA1 PA0 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 Doc ID 7833 Rev 7 121/128 PQFP52 pin assignments Table 76. PQFP52 connections (see Features) (continued) Pin number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Pin assignments AD9 AD10 AD11 AD12 AD13 AD14 AD15 CNTL0 RESET CNTL2 CNTL1 PB7 PB6 GND PB5 PB4 PB3 PB2 PB1 PB0 PSD8XXFX 122/128 Doc ID 7833 Rev 7 PSD8XXFX PLCC52 pin assignments Appendix B Table 77. PLCC52 pin assignments PLCC52 connections (see Features) Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin assignments GND PB5 PB4 PB3 PB2 PB1 PB0 PD2 PD1 PD0 PC7 PC6 PC5 PC4 VCC GND PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 GND PA2 PA1 PA0 AD0 AD1 AD2 Doc ID 7833 Rev 7 123/128 PLCC52 pin assignments Table 77. PLCC52 connections (see Features) (continued) Pin number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Pin assignments AD3 AD4 AD5 AD6 AD7 VCC AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 CNTL0 RESET CNTL2 CNTL1 PB7 PB6 PSD8XXFX 124/128 Doc ID 7833 Rev 7 PSD8XXFX TQFP64 pin assignments Appendix C Table 78. TQFP64 pin assignments TQFP64 connections (see Features) Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin assignments PD2 PD1 PD0 PC7 PC6 PC5 VCC VCC VCC GND GND PC3 PC2 PC1 PC0 NC NC NC PA7 PA6 PA5 PA4 PA3 GND GND PA2 PA1 PA0 AD0 AD1 N/D AD2 Doc ID 7833 Rev 7 125/128 TQFP64 pin assignments Table 78. TQFP64 connections (see Features) (continued) Pin number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin assignments AD3 AD4 AD5 AD6 AD7 VCC VCC AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 CNTL0 NC RESET CNTL2 CNTL1 PB7 PB6 GND GND PB5 PB4 PB3 PB2 PB1 PB0 NC NC PSD8XXFX 126/128 Doc ID 7833 Rev 7 PSD8XXFX Revision history Revision history Table 79. Date 15-Oct-99 27-Oct-00 30-Nov-00 23-Oct-01 07-Apr-03 12-Jun-03 02-Oct-03 17-Nov-03 04-Jun-04 05-Jan-06 Document revision history Revision 1.0 1.1 1.2 2.0 3.0 3.1 3.2 3.3 4.0 5.0 Changes Initial release as a WSI document Port A Peripheral Data mode Read Timing, changed to 50 PSD85xF2 added Document rewritten using the ST template v2.2 Template applied; voltage correction (Table 75) Fix errors in PQFQ52 Connections Correct Instructions (Table 10); update disclaimer, Title for EDOCS application Correct package references (Features) Reformatted (adjust RPN list); added Table 9; added ‘U’ package (64-pin) (Features, Figure 3, Figure 52; Table 74, Table 75, Table 78); 5V split from original Added Silicon Revision A into part numbering scheme. See Table 75 Document reformatted. Removed root part number PSD813F3. SRAM standby mode removed. Backup battery feature removed. All products are delivered in ECOPACK-compliant packages. Section 23: Package mechanical updated. Minor text modifications. Corrected pin 7 of TQFP64 package in Figure 3: TQFP64 connections. 13-Feb-2009 6 05-May-2009 7 Doc ID 7833 Rev 7 127/128 PSD8XXFX Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 128/128 Doc ID 7833 Rev 7