PSD835G2V-90U

PSD835G2V Flash PSD, 3 V supply, for 8-bit MCUs 4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM Features ■ Flash in-system programmable (ISP) peripheral for 8-bit MCUs Dual bank Flash memories – 4 Mbits of Primary Flash memory (8 uniform sectors, 64 Kbyte) – 256 Kbits of secondary Flash memory with 4 sectors – Concurrent operation: READ from one memory while erasing and writing the other 64 Kbit of battery-backed SRAM 52 reconfigurable I/O ports Enhanced JTAG serial port PLD with macrocells – Over 3000 gates of PLD: CPLD and DPLD – CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs) – DPLD - user defined internal chip select decoding 52 individually configurable I/O port pins They can be used for the following functions: – MCU I/Os – PLD I/Os – Latched MCU address output – Special function I/Os. – I/O ports may be configured as open-drain outputs. In-system programming (ISP) with JTAG – Built-in JTAG compliant serial port allows full-chip In-System Programmability – Efficient manufacturing allow easy product testing and programming – Use low cost FlashLINK cable with PC ■ ■ ■ TQFP80 (U) ■ ■ ■ ■ ■ Page register – Internal page register that can be used to expand the microcontroller address space by a factor of 256 Programmable power management High endurance: – 100 000 Erase/WRITE cycles of Flash memory – 1,000 Erase/WRITE cycles of PLD – 15 year data retention 3 V to 3.6 V single supply voltage Standby current as low as 25 µA Memory speed – 90 ns Flash memory and SRAM access time for VCC = 3.0 V to 3.6 V – 120 ns Flash memory and SRAM access time for VCC = 3.0 V to 3.6 V ECOPACK® packages ■ ■ ■ ■ ■ ■ April 2007 Rev 2 1/118 www.st.com 1 Contents PSD835G2V Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 In-system programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.1 1.1.2 1.1.3 First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . 11 Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.1 1.2.2 1.2.3 Simultaneous read and write to Flash memory . . . . . . . . . . . . . . . . . . . 12 Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Separate Program and Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3 PSDsoft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 In-application re-programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 4 5 6 Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PSD register description and address offset . . . . . . . . . . . . . . . . . . . . 23 Register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 6.2 6.3 6.4 Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Primary Flash memory and Secondary Flash memory description . . . . . 30 Memory Block Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Upper and Lower Block IN MAIN FLASH SECTOR . . . . . . . . . . . . . . . . . 30 2/118 PSD835G2V Contents 6.5 6.6 Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Read Primary Flash Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Read the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Data polling flag (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Toggle flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Error flag (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Erase time-out flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.1 8.2 Data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.2.1 Unlock bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.1 9.2 9.3 9.4 Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1 10.2 10.3 Flash memory sector protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Reset (RESET) signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11 12 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3/118 Contents PSD835G2V 12.2 12.3 Memory select configuration for MCUs with separate program and data spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Configuration modes for MCUs with separate program and data spaces 46 12.3.1 12.3.2 Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Combined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13 14 15 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Memory ID registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 The Turbo Bit in PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Product term allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15.5.1 Loading and reading the output macrocells (OMC) . . . . . . . . . . . . . . . . 56 The OMC mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 External chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 16 MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 16.1 16.2 16.3 16.4 16.5 16.6 16.7 PSD interface to a multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 63 MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 17 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 17.1 17.2 17.3 General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4/118 PSD835G2V Contents 17.4 17.5 17.6 17.7 17.8 17.9 PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Address out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Data Port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 17.10 Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 17.11 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 17.12 Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17.13 Drive Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17.14 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 17.15 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.16 Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.17 Output macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.18 OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.19 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.20 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 17.21 Ports A,B and C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . 80 17.22 Port D – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 17.23 Port E – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17.24 Port F – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17.25 Port G – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 18 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 18.1 18.2 18.3 18.4 18.5 18.6 Automatic Power-down (APD) unit and Power-down mode . . . . . . . . . . . 85 18.1.1 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 18.3.1 SRAM Standby mode (battery backup) . . . . . . . . . . . . . . . . . . . . . . . . . 87 PSD Chip Select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 19 Reset timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . . . 89 5/118 Contents PSD835G2V 19.1 19.2 19.3 19.4 Power-up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 I/O pin, Register and PLD status at reset . . . . . . . . . . . . . . . . . . . . . . . . . 89 Reset of Flash memory Erase and Program cycles . . . . . . . . . . . . . . . . . 89 20 Programming in-circuit using the JTAG/ISP interface . . . . . . . . . . . . . 91 20.1 20.2 20.3 Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 21 22 23 24 25 AC/DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 AC and DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Appendix A Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6/118 PSD835G2V List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Pin description (for the TQFP80 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 JTAG signals on Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Methods of programming different functional blocks of the PSD . . . . . . . . . . . . . . . . . . . . 21 Register address offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data-In Registers – Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Data-Out Registers – Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Direction Registers – Ports A, B, C, D, E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Control Registers – Ports E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Drive Registers – Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Drive Registers – Ports C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Enable-Out Registers – Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Input Macrocells – Ports A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mask Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Mask Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Flash Memory Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Flash Boot Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 JTAG Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PMMR0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PMMR2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Memory_ID0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Memory_ID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DPLD and CPLD Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Output macrocell port and data bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 MCUs and their control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 80C251 configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Interfacing the PSD with the 80C251, with one read input . . . . . . . . . . . . . . . . . . . . . . . . . 67 Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Port operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 I/O port latched address output assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Port pin direction control, Output Enable P.T. not defined . . . . . . . . . . . . . . . . . . . . . . . . . 78 Port pin direction control, Output Enable P.T. defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Port direction assignment example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Drive Register pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Power-down mode’s effect on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 PSD timing and Standby current during Power-down mode. . . . . . . . . . . . . . . . . . . . . . . . 86 APD counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Status during power-up reset, warm reset and power-down mode . . . . . . . . . . . . . . . . . . 90 JTAG port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7/118 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. PSD835G2V Example of PSD typical power calculation at VCC = 3.0 V (with Turbo mode on) . . . . . . . 94 Example of PSD typical power calculation at VCC = 3.0 V (with Turbo mode Off) . . . . . . . 95 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 AC signal letters for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 AC signal behavior symbols for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 CPLD combinatorial timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 CPLD Macrocell Synchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 CPLD Macrocell Asynchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Input macrocell timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Port F peripheral data mode read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Port F peripheral data mode write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Program, Write and Erase times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Reset (RESET) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 VSTBYON timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 TQFP80 - 80 lead Plastic Quad Flatpack, package mechanical data. . . . . . . . . . . . . . . . 114 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 PSD835G2V TQFP80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8/118 PSD835G2V List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. TQFP80 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PSD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PSDsoft development tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Example for Flash Sector Chip Select FS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Selecting the upper or lower block in a Primary Flash memory sector . . . . . . . . . . . . . . . . 31 Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Priority level of memory and I/O components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8031 memory modules – separate space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8031 memory modules – combined space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PLD diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DPLD logic array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Macrocell and I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 CPLD output macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Input macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Handshaking communication using input macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 An example of a typical 8-bit multiplexed bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 An example of a typical 8-bit non-multiplexed bus interface. . . . . . . . . . . . . . . . . . . . . . . . 64 Interfacing the PSD with an 80C31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Interfacing the PSD with the 80C251, with RD and PSEN Inputs . . . . . . . . . . . . . . . . . . . 68 Interfacing the PSD with the 80C51X, 8-bit data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Interfacing the PSD with a 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 General I/O port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Port A, B and C structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Port D structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Port E, F, G structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 APD unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Enable power-down flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Power-up and warm reset (RESET) timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 PLD ICC /frequency consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Switching waveforms – key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Input to Output Disable / Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Combinatorial Timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Synchronous Clock mode timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Asynchronous Reset / Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Asynchronous Clock mode timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Input macrocell timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Peripheral I/O Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Peripheral I/O Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9/118 List of figures Figure 49. PSD835G2V TQFP80 - 80 lead Plastic Quad Flatpack, package outline . . . . . . . . . . . . . . . . . . . . . . . 113 10/118 PSD835G2V Description 1 Description The PSD family of memory systems for microcontrollers (MCUs) brings In-SystemProgrammability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices. The PSD family offers two methods to program the PSD Flash memory while the PSD is soldered to the circuit board: In-System Programming (ISP) via JTAG, and In-Application Programming (IAP). 1.1 In-system programming (ISP) via JTAG An IEEE 1149.1 compliant JTAG In-System Programming (ISP) interface is included on the PSD enabling the entire device (Flash memories, PLD, configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU participation, which means the PSD can be programmed anytime, even when completely blank. The innovative JTAG interface to Flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: 1.1.1 First time programming How do I get firmware into the Flash memory the very first time? JTAG is the answer. Program the blank PSD with no MCU involvement. 1.1.2 Inventory build-up of pre-programmed devices How do I maintain an accurate count of pre-programmed Flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer. Build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to the customer. No more labels on chips, and no more wasted inventory. 1.1.3 Expensive sockets How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads. 1.2 In-application programming (IAP) Two independent Flash memory arrays are included so that the MCU can execute code from one while erasing and programming the other. Robust product firmware updates in the field are possible over any communications channel (CAN, Ethernet, UART, J1850, etc.) using this unique architecture. Designers are relieved of these problems: 11/118 Description PSD835G2V 1.2.1 Simultaneous read and write to Flash memory How can the MCU program the same memory from which it is executing code? It cannot. The PSD allows the MCU to operate the two Flash memory blocks concurrently, reading code from one while erasing and programming the other during IAP. 1.2.2 Complex memory mapping How can I map these two memories efficiently? A programmable Decode PLD (DPLD) is embedded in the PSD. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extremely high address resolution. As an option, the secondary Flash memory can be swapped out of the system memory map when IAP is complete. A built-in page register breaks the MCU address limit. 1.2.3 Separate Program and Data space How can I write to Flash memory while it resides in Program space during field firmware updates? My 80C51 will not allow it. The PSD provides means to reclassify Flash memory as Data space during IAP, then back to Program space when complete. 1.3 PSDsoft PSDsoft, a software development tool from ST, guides you through the design process stepby-step making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft takes you through the remainder of the design with point and click entry, covering PSD selection, pin definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI-C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft: FlashLINK (JTAG) and PSDpro. 12/118 PSD835G2V Figure 1. TQFP80 connections 70 GND 69 VCC 80 PD1 79 PD0 68 PB7 67 PB6 66 PB5 65 PB4 64 PB3 63 PB2 62 PB1 61 PB0 78 PE7 77 PE6 76 PE5 75 PE4 74 PE3 73 PE2 72 PE1 71 PE0 Description PD2 1 PD3 2 AD0 3 AD1 4 AD2 5 AD3 6 AD4 7 GND 8 VCC 9 AD5 10 AD6 11 AD7 12 AD8 13 AD9 14 AD10 15 AD11 16 AD12 17 AD13 18 AD14 19 AD15 20 60 CNTL1 59 CNTL0 58 PA7 57 PA6 56 PA5 55 PA4 54 PA3 53 PA2 52 PA1 51 PA0 50 GND 49 GND 48 PC7 47 PC6 46 PC5 45 PC4 44 PC3 43 PC2 42 PC1 41 PC0 PG0 21 PG1 22 PG2 23 PG3 24 PG4 25 PG5 26 PG6 27 PG7 28 VCC 29 GND 30 PF0 31 PF1 32 PF2 33 PF3 34 PF4 35 PF5 36 PF6 37 PF7 38 RESET 39 CNTL2 40 AI04943 13/118 Description Table 1. Pin name PSD835G2V Pin description (for the TQFP80 package) Pin Type Description This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this port. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect A8-A15 to this port. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port. If you are using an 80C251 in page mode, connect AD8-AD15 to this port. If you are using an 80C51XA in burst mode, connect A12-A19 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. The following control signals can be connected to this port, based on your MCU: WR – active Low Write Strobe input. R_W – active High read/active Low write input. This port is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. The following control signals can be connected to this port, based on your MCU: RD – active Low Read Strobe input. E – E clock input. DS – active Low Data Strobe input. PSEN – connect PSEN to this port when it is being used as an active Low read signal. For example, when the 80C251 outputs more than 16 address bits, PSEN is actually the read signal. This port is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. This port can be used to input the PSEN (Program Select Enable) signal from any MCU that uses this signal for code exclusively. If your MCU does not output a Program Select Enable signal, this port can be used as a generic input. This port is connected to the PLDs as input. Active Low input. Resets I/O Ports, PLD macrocells and some of the Configuration Registers and JTAG registers. Must be Low at Power-up. Reset also aborts the Flash programming/erase cycle that is in progress. ADIO0-7 3-7-10-12 I/O ADIO8-15 13-20 I/O CNTL0 59 I CNTL1 60 I CNTL2 40 I Reset 39 I 14/118 PSD835G2V Table 1. Pin name PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Description Pin description (for the TQFP80 package) (continued) Pin 58 57 56 55 54 53 52 51 68 67 66 65 64 63 62 61 48 47 46 45 44 43 42 41 Type Description These pins make up Port A. These port pins are configurable and can have the following functions: I/O CMOS MCU I/O – write to or read from a standard output or input port. or Open CPLD macrocell (McellA0-7) outputs. Drain Inputs to the PLDs. Latched, transparent or registered PLD input. I/O CMOS or Open Drain These pins make up Port B. These port pins are configurable and can have the following functions: MCU I/O – write to or read from a standard output or input port. CPLD macrocell (McellB0-7) output. Inputs to the PLDs. Latched, transparent or registered PLD input. These pins make up Port C. These port pins are configurable and can have the I/O following functions: CMOS MCU I/O – write to or read from a standard output or input port. or Open Drain External Chip Select (ECS0-7) output. Latched, transparent or registered PLD input. PD0 pin of Port D. This port pin can be configured to have the following functions: I/O ALE/AS input latches addresses on ADIO0-ADIO15 pins. CMOS AS input latches addresses on ADIO0-ADIO15 pins on the rising edge. or Open Drain Input to the PLDs. Transparent PLD input. PD1 pin of Port D. This port pin can be configured to have the following functions: I/O MCU I/O – write to or read from a standard output or input port. CMOS or Open Input to the PLDs. Drain CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and the CPLD AND Array. PD2 pin of Port D. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Input to the PLDs. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/O. When High, the PSD memory blocks are disabled to conserve power. The trailing edge of CSI can be used to get the PSD out of power-down mode. PD0 79 PD1 80 PD2 1 I/O CMOS or Open Drain PD3 2 I/O PD3 pin of Port D. This port pin can be configured to have the following functions: CMOS MCU I/O – write to or read from a standard output or input port. or Open Drain Input to the PLDs. 15/118 Description Table 1. Pin name PSD835G2V Pin description (for the TQFP80 package) (continued) Pin Type I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain I/O CMOS or Open Drain Description PE0 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address output. TMS input for JTAG/ISP interface. PE1 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address output. TCK input for JTAG/ISP interface (Schmidt Trigger). PE2 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address output. TDI input for JTAG/ISP interface. PE3 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address output. TDO input for JTAG/ISP interface. PE0 71 PE1 72 PE2 73 PE3 74 PE4 75 PE4 pin of Port E. This port pin can be configured to have the following functions: I/O MCU I/O – write to or read from a standard output or input port. CMOS Latched address output. or Open Drain TSTAT input for the ISP interface. Ready/Busy for in-circuit Parallel Programming. I/O CMOS or Open Drain I/O CMOS or Open Drain PE5 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address output. TERR active Low input for ISP interface. PE6 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address output. VSTBY SRAM standby voltage input for battery backup SRAM. PE5 76 PE6 77 PE7 78 PE7 pin of Port E. This port pin can be configured to have the following functions: I/O MCU I/O – write to or read from a standard output or input port. CMOS Latched address output. or Open Drain VBATON battery backup indicator output. Goes High when power is drawn from an external battery. PF0 through PF7 pins of Port F. This port pins can be configured to have the following functions: I/O MCU I/O – write to or read from a standard output or input port. CMOS Input to the PLDs. or Open Drain Latched address outputs. As address A0-A3 inputs in 80C51XA mode. As data bus port (D07) in non-multiplexed bus configuration. PF0-PF7 31-38 16/118 PSD835G2V Table 1. Pin name Description Pin description (for the TQFP80 package) (continued) Pin Type I/O CMOS or Open Drain Description PG0 through PG7 pins of Port G. This port pins can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address outputs. Supply Voltage Ground pins PG0-PG7 8, 30, 49, 50, 70 9, 29, 69 8, 30, 49, 50, 70 VCC GND 17/118 18/118 Description Figure 2. ADDRESS/DATA/CONTROL BUS PLD INPUT BUS PAGE REGISTER EMBEDDED ALGORITHM 8 SECTORS 4 MBIT PRIMARY FLASH MEMORY CNTL0, CNTL1, CNTL2 SECTOR SELECTS FLASH DECODE PLD (DPLD) 82 SECTOR SELECTS SRAM SELECT PERIP I/O MODE SELECTS ADIO PORT CSIOP RUNTIME CONTROL AND I/O REGISTERS 8 EXT CS TO PORT C OR F 16 OUTPUT MACROCELLS PROG. PORT PORT F CLKIN PORT A & B 24 INPUT MACROCELLS PORT A ,B & C 64 KBIT BATTERY BACKUP SRAM PROG. MCU BUS INTRF. 256 KBIT SECONDARY FLASH MEMORY (BOOT OR DATA) 4 SECTORS PSD block diagram POWER MANGMT UNIT VSTDBY (PE6 ) PROG. PORT PA0 – PA7 AD0 – AD15 PORT A PROG. PORT PORT B PB0 – PB7 82 FLASH ISP CPLD (CPLD) PF0 –PF7 PROG. PORT PORT C PC0 – PC7 MACROCELL FEEDBACK OR PORT INPUT CLKIN PORT F PROG. PORT PORT D PD0 – PD2 PG0 – PG7 PORT G PROG. PORT PROG. PORT GLOBAL CONFIG. & SECURITY PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PORT E PE0 – PE7 CLKIN (PD1) PSD835G2V AI05793b PSD835G2V PSD architectural overview 2 PSD architectural overview PSD devices contain several major functional blocks. Figure 2. on page 18 shows the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. 2.1 Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in Memory blocks on page 29. The 4Mbit (512K x 8) Flash memory is the primary memory of the PSD. It is divided into 8 equally-sized sectors that are individually selectable. The 256Kbit (32K x8) secondary Flash memory is divided into 4 equally-sized sectors. Each sector is individually selectable. The 64 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. If an external battery is connected to Voltage Standby (VSTBY, PC2), data is retained in the event of power failure. Each sector of memory can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time. 2.2 Page Register The 8-bit Page Register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page Register can also be used to change the address mapping of sectors of the Flash memories into different memory spaces for IAP. 2.3 PLDs The device contains two PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 2, each optimized for a different function. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The DPLD is used to decode addresses and to generate Sector Select signals for the PSD internal memory and registers. The CPLD can implement user-defined logic functions. The DPLD has combinatorial outputs. The CPLD has 16 Output Macrocells (OMC) and 8 combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of product terms, and macrocells. The PLDs consume minimal power by using Power-Management design techniques. The speed and power consumption of the PLD is controlled by the Turbo bit in PMMR0 and other bits in the PMMR2. These registers are set by the MCU at run-time. There is a slight penalty to PLD propagation time when invoking the power management features. 19/118 PSD architectural overview PSD835G2V 2.4 I/O Ports The PSD has 52 I/O pins distributed over the seven ports (Port A, B, C, D, E, F and G). Each I/O pin can be individually configured for different functions. Ports can be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using multiplexed address/data buses. The JTAG pins can be enabled on Port E for In-System Programming (ISP). Ports F and G can also be configured as data ports for a non-multiplexed bus. Ports A and B can also be configured as a data port for a non-multiplexed bus. 2.5 MCU Bus Interface PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU’s control signals, which are also used as inputs to the PLDs. For examples, please see MCU bus interface examples on page 63. Table 2. PLD I/O Name Decode PLD (DPLD) Complex PLD (CPLD) Inputs 82 82 Outputs 17 24 Product Terms 43 150 Table 3. JTAG signals on Port E Port E Pins JTAG Signal TMS TCK TDI TDO TSTAT TERR PE0 PE1 PE2 PE3 PE4 PE5 2.6 JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port E. This serial interface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port E. Table 3. on page 20 indicates the JTAG pin assignments. 2.7 In-system programming (ISP) Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can be programmed or erased without the use of the MCU. 20/118 PSD835G2V PSD architectural overview 2.8 In-application re-programming (IAP) The primary Flash memory can also be programmed in-system by the MCU executing the programming algorithms out of the secondary memory, or SRAM. Since this is a sizable separate block, the application can also continue to operate. The secondary memory can be programmed the same way by executing out of the primary Flash memory. The PLD or other PSD Configuration blocks can be programmed through the JTAG port or a device programmer. Table 4 indicates which programming methods can program different functional blocks of the PSD. 2.9 Power management unit (PMU) The Power Management Unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit has a Power-down mode that helps reduce power consumption. The PSD also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo bit in PMMR0 can be reset to 0 and the CPLD latches its outputs and goes to sleep until the next transition on its inputs. Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD to reduce power consumption. Please see Power management on page 84 for more details. Table 4. Methods of programming different functional blocks of the PSD Functional Block Primary Flash Memory Secondary Flash Memory PLD Array (DPLD and CPLD) PSD Configuration JTAG/ISP Yes Yes Yes Yes Device Programmer Yes Yes Yes Yes IAP Yes Yes No No 21/118 Development system PSD835G2V 3 Development system The PSD family is supported by PSDsoft, a Windows-based (95, 98, NT) software development tool. A PSD design is quickly and easily produced in a point-and-click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 3. PSDsoft is available from our web site (the address is given on the back page of this data sheet) or other distribution channels. PSDsoft directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/representative, or directly from our web site using a credit card. The PSD is also supported by third party device programmers. See our web site for the current list. Figure 3. PSDsoft development tool Choose MCU and PSD Automatically Configures MCU bus interface and other PSD attributes. Define PSD Pin and Node Functions Point-and-click definition of PSD pin functions, internal nodes and MCU system memory map Define General Purpose Logic in CPLD Point-and-click definition of combinatorial and registered logic in CPLD. Access to HDL is available if needed. C Code Generation GENERATE C CODE SPECIFIC TO PSD FUNCTIONS Merge MCU Firmware with PSD Configuration A composite object file is created containing MCU firmware and PSD configuration MCU FIRMWARE HEX OR S-RECORD FORMAT USER'S CHOICE OF MICROCONTROLLER COMPILER/LINKER *.OBJ FILE ST PSD Programmer PSDPro, or FlashLINK (JTAG) *.OBJ FILE AVAILABLE FOR 3rd PARTY PROGRAMMERS (CONVENTIONAL or JTAG/ISP) AI04918b 22/118 PSD835G2V PSD register description and address offset 4 PSD register description and address offset Table 5 shows the offset addresses to the PSD registers relative to the CSIOP base address. The CSIOP space is the 256 Bytes of address that is allocated by the user to the internal PSD registers. Table 5 provides brief descriptions of the registers in CSIOP space. The following section gives a more detailed description. Table 5. Register address offset Description Reads Port pin as input, MCU I/O input mode Selects mode between MCU I/O or Address Out Stores data for output to Port pins, MCU I/O output mode Configures Port pin as input or output Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins. Reads Input Macrocells 4C Reads the status of the output enable to the I/O Port driver Read – reads output of macrocells A Write – loads macrocell flipflops Read – reads output of macrocells B Write – loads macrocell flipflops Blocks writing to the Output Macrocells A 23 C0 Blocks writing to the Output Macrocells B Read only – Primary Flash Sector Protection Read only – PSD Security and Secondary Flash memory Sector Protection Enables JTAG Port Power Management Register 0 Power Management Register 2 Register name Port A Port B Port C Port D Port E Port F Port G Other(1) Data In Control Data Out Direction 04 06 05 07 14 14 15 15 00 01 10 11 30 32 34 36 40 42 44 46 41 43 45 47 Drive Select 08 09 18 19 38 48 49 Input Macrocell Enable Out 0A 0C 0B 0D 1C 1A 1B Output Macrocells A 20 Output Macrocells B Mask Macrocells A Mask Macrocells B Primary Flash Protection Secondary Flash memory Protection JTAG Enable PMMR0 PMMR2 21 22 C2 C7 B0 B4 23/118 PSD register description and address offset Table 5. Register address offset (continued) PSD835G2V Register name Port A Port B Port C Port D Port E Port F Port G Other(1) Page VM E0 E2 Description Page Register Places PSD memory areas in Program and/or Data space on an individual basis. Read only – Primary Flash memory and SRAM size Read only – Secondary Flash memory type and size Memory_ID0 Memory_ID1 1. Other registers that are not part of the I/O ports. F0 F1 24/118 PSD835G2V Register bit definition 5 Register bit definition All the registers of the PSD are included here, for reference. Detailed descriptions of these registers can be found in the following sections. Table 6. Bit 7 Port pin 7 Data-In Registers – Ports A, B, C, D, E, F, G(1) Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 1. Bit Definitions (Read-only registers): Read Port pin status when Port is in MCU I/O input mode. Table 7. Bit 7 Port pin 7 Data-Out Registers – Ports A, B, C, D, E, F, G(1) Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 1. Bit Definitions: Latched data for output to Port pin when pin is configured in MCU I/O output mode. Table 8. Bit 7 Port pin 7 Direction Registers – Ports A, B, C, D, E, F, G(1) Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 1. Bit Definitions: Port pin 0 = Port pin is configured in Input mode (default). Port pin 1 = Port pin is configured in Output mode. Table 9. Bit 7 Port pin 7 Control Registers – Ports E, F, G(1) Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 1. Bit Definitions: Port pin 0 = Port pin is configured in MCU I/O mode (default). Port pin 1 = Port pin is configured in Latched Address Out mode. Table 10. Bit 7 Port pin 7 Drive Registers – Ports A, B, D, E, G(1) Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 1. Bit Definitions: Port pin 0 = Port pin is configured for CMOS Output driver (default). Port pin 1 = Port pin is configured for Open Drain output driver. Table 11. Bit 7 Port pin 7 Drive Registers – Ports C, F(1) Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 1. Bit Definitions: Port pin 0 = Port pin is configured for CMOS Output driver (default). Port pin 1 = Port pin is configured in Slew Rate mode. 25/118 Register bit definition Table 12. Bit 7 Port pin 7 PSD835G2V Enable-Out Registers – Ports A, B, C, F(1) Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 1. Bit Definitions (Read-only registers): Port pin 0 = Port pin is in tri-state driver (default). Port pin 1 = Port pin is enabled. Table 13. Bit 7 IMcell 7 Input Macrocells – Ports A, B, C(1) Bit 6 IMcell 6 Bit 5 IMcell 5 Bit 4 IMcell 4 Bit 3 IMcell 3 Bit 2 IMcell 2 Bit 1 IMcell 1 Bit 0 IMcell 0 1. Bit Definitions (Read-only registers): Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C. Table 14. Bit 7 Mcella 7 Output Macrocells A Register(1) Bit 6 Mcella 6 Bit 5 Mcella 5 Bit 4 Mcella 4 Bit 3 Mcella 3 Bit 2 Mcella 2 Bit 1 Mcella 1 Bit 0 Mcella 0 1. Bit Definitions: Write Register: Load MCellA7-MCellA0 with 0 or 1. Read Register: Read MCellA7-MCellA0 output status. Table 15. Bit 7 Mcellb 7 Output Macrocells B Register(1) Bit 6 Mcellb 6 Bit 5 Mcellb 5 Bit 4 Mcellb 4 Bit 3 Mcellb 3 Bit 2 Mcellb 2 Bit 1 Mcellb 1 Bit 0 Mcellb 0 1. Bit Definitions: Write Register: Load MCellB7-MCellB0 with 0 or 1. Read Register: Read MCellB7-MCellB0 output status. Table 16. Bit 7 Mcella 7 Mask Macrocells A Register(1) Bit 6 Mcella 6 Bit 5 Mcella 5 Bit 4 Mcella 4 Bit 3 Mcella 3 Bit 2 Mcella 2 Bit 1 Mcella 1 Bit 0 Mcella 0 1. Bit Definitions: McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default). McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU. Table 17. Bit 7 Mcellb 7 Mask Macrocells B Register(1) Bit 6 Mcellb 6 Bit 5 Mcellb 5 Bit 4 Mcellb 4 Bit 3 Mcellb 3 Bit 2 Mcellb 2 Bit 1 Mcellb 1 Bit 0 Mcellb 0 1. Bit Definitions: McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default). McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by MCU. Table 18. Bit 7 Flash Memory Protection Register(1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot 1. Bit Definitions (Read-only register): Sec_Prot 1 = Primary Flash memory Sector is write protected. Sec_Prot 0 = Primary Flash memory Sector is not write protected. 26/118 PSD835G2V Table 19. Bit 7 Register bit definition Flash Boot Protection Register(1) Bit 6 Bit 5 not used Bit 4 not used Bit 3 Bit 2 Bit 1 Bit 0 Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot Security_Bit not used 1. Bit Definitions: Sec_Prot 1 = Secondary Flash memory Sector is write protected. Sec_Prot 0 = Secondary Flash memory Sector is not write protected. Security_Bit 0 = Security Bit in device has not been set. Security_Bit 1 = Security Bit in device has been set. Table 20. Bit 7 not used JTAG Enable Register(1) Bit 6 not used Bit 5 not used Bit 4 not used Bit 3 not used Bit 2 not used Bit 1 not used Bit 0 JTAGEnable 1. Bit Definitions: JTAG_Enable 1 = JTAG Port is enabled. JTAG_Enable 0 = JTAG Port is disabled. Table 21. Bit 7 PGR 7 Page Register(1) Bit 6 PGR 6 Bit 5 PGR 5 Bit 4 PGR 4 Bit 3 PGR 3 Bit 2 PGR 2 Bit 1 PGR 1 Bit 0 PGR 0 1. Bit Definitions: Configure Page input to PLD. Default is PGR7-PGR0=00. Table 22. Bit 7 not used (set to 0) PMMR0 Register(1) (2) Bit 6 not used (set to 0) Bit 5 Bit 4 Bit 3 Bit 2 not used (set to 0) Bit 1 APD Enable Bit 0 not used (set to 0) PLD PLD PLD MCells CLK Array CLK Turbo 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers. 2. Bit Definitions: APD Enable0 = Automatic Power-down (APD) is disabled. 1 = Automatic Power-down (APD) is enabled. PLD Turbo0 = PLD Turbo is on. 1 = PLD Turbo is off, saving power. PLD Array CLK0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off. 1 = CLKIN to the PLD AND array is disconnected, saving power. PLD MCells CLK0 = CLKIN to the PLD Macrocells is connected. 1 = CLKIN to the PLD Macrocells is disconnected, saving power. Table 23. Bit 7 not used (set to 0) PMMR2 Register(1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLD Array Addr PLD Array PLD Array WRH ALE PLD Array PLD Array PLD Array not used CNTL2 CNTL1 CNTL0 (set to 0) 1. Bit Definitions: PLD Array Addr0 = Address A7-A0 are connected to the PLD array. 1 = Address A7-A0 are blocked from the PLD array, saving power. (Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4) PLD Array CNTL20 = CNTL2 input to the PLD AND array is connected. 1 = CNTL2 input to the PLD AND array is disconnected, saving power. PLD Array CNTL10 = CNTL1 input to the PLD AND array is connected. 1 = CNTL1 input to the PLD AND array is disconnected, saving power. PLD Array CNTL00 = CNTL0 input to the PLD AND array is connected. 1 = CNTL0 input to the PLD AND array is disconnected, saving power. PLD Array ALE0 = ALE input to the PLD AND array is connected. 1 = ALE input to the PLD AND array is disconnected, saving power. PLD Array WRH0 = WRH/DBE input to the PLD AND array is connected. 1 = WRH/DBE input to the PLD AND array is disconnected, saving power. 27/118 Register bit definition Table 24. Bit 7 Peripheral mode PSD835G2V VM Register(1) (2) Bit 6 not used (set to 0) Bit 5 not used (set to 0) Bit 4 FL_data Bit 3 Boot_data Bit 2 FL_code Bit 1 Boot_code Bit 0 SR_code 1. On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft. Bit0 and Bit7 are always cleared on reset. Bit0-Bit4 are active only when the device is configured for the 8031 and compatible MCU families. 2. Bit Definitions: SR_code0 = PSEN cannot access SRAM. 1 = PSEN can access SRAM. Boot_code0 = PSEN cannot access Secondary NVM. 1 = PSEN can access Secondary NVM. FL_code0 = PSEN cannot access Primary Flash memory. 1 = PSEN can access Primary Flash memory. Boot_data0 = RD cannot access Secondary NVM. 1 = RD can access Secondary NVM. FL_data0 = RD cannot access Primary Flash memory. 1 = RD can access Primary Flash memory. Peripheral mode0 = Peripheral mode of Port F is disabled. 1 = Peripheral mode of Port F is enabled. Table 25. Bit 7 S_size 3 Memory_ID0 Register(1) Bit 6 S_size 2 Bit 5 S_size 1 Bit 4 S_size 0 Bit 3 F_size 3 Bit 2 F_size 2 Bit 1 F_size 1 Bit 0 F_size 0 1. Bit Definitions: F_size[3:0]4h = Primary Flash memory size is 4 Mbit 5h = Primary Flash memory size is 8Mbit S_size[3:0]0h = There is no SRAM 1h = SRAM size is 16 Kbit 3h = SRAM size is 64 Kbit Table 26. Bit 7 not used (set to 0) Memory_ID1 Register(1) Bit 6 not used (set to 0) Bit 5 B_type 1 Bit 4 B_type 0 Bit 3 B_size 3 Bit 2 B_size 2 Bit 1 B_size 1 Bit 0 B_size 0 1. Bit Definitions: B_size[3:0]0h = There is no Secondary NVM 2h = Secondary NVM size is 256 Kbit B_type[1:0]0h = Secondary NVM is Flash memory 1h = Secondary NVM is EEPROM 28/118 PSD835G2V Detailed operation 6 Detailed operation As shown in Figure 2. on page 18, the PSD consists of six major types of functional blocks: ● ● ● ● ● ● Memory Blocks PLD Blocks MCU Bus Interface I/O Ports Power Management Unit (PMU) JTAG/ISP Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. 6.1 Memory blocks The PSD has the following memory blocks: – – – Primary Flash memory Secondary Flash memory SRAM The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are user-defined in PSDsoft. Table 27. Memory block size and organization Primary Flash memory Sector number 0 1 2 3 4 5 6 7 Total Secondary Flash memory SRAM Sector size Sector Select Sector size Sector Select SRAM size SRAM Select (bytes) signal (bytes) signal (bytes) signal 64K 64K 64K 64K 64K 64K 64K 64K 512K FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 8 Sectors 32K 4 Sectors 16K 8K 8K 8K 8K CSBOOT0 CSBOOT1 CSBOOT2 CSBOOT3 16K RS0 29/118 Detailed operation PSD835G2V 6.2 Primary Flash memory and Secondary Flash memory description The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors of eight KBytes each. Each sector of either memory block can be separately protected from Program and Erase cycles. Flash memory may be erased on a sector-by-sector basis and programmed Word-by-Word. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading. During a Program or Erase cycle in Flash memory, the status can be output on Ready/Busy (PE4). This pin is set up using PSDsoft. 6.3 Memory Block Select signals The DPLD generates the Select signals for all the internal memory blocks (see PLDs on page 49). Each of the eight sectors of the primary Flash memory has a Select signal (FS0FS7) which can contain up to three product terms. Each of the four sectors of the secondary Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in different areas of system memory. When using an MCU with separate Program and Data space, these flexible Select signals allow dynamic re-mapping of sectors from one memory space to the other before and after IAP. 6.4 Upper and Lower Block IN MAIN FLASH SECTOR The PSD835G2’s main Flash memory has eight 64-KByte sectors. The 64-KByte sector size may cause some difficulty in code mapping for an 8-bit MCU with only 64-KByte address space. To resolve this mapping issue, the PSD835G2 provides additional logic (see Figure 5. on page 31) for the user to split the 8 sectors such that each sector has a lower and upper 32-KByte block, and the two blocks can reside in different pages but in the same address range. If your design works with 64KB sectors, you don’t need to configure this logic. If the design requires 32KB blocks in each sector, you need to define a “FA15” PLD equation in PSDsoft as the A15 address input to the main Flash module. FA15 consists of 3 product terms and will control whether the MCU is accessing the lower or upper 32KB in the selected sector. Figure 4 shows an example for Flash sector chip select FS0. A typical equation is FA15 = pgr4 of the Page Register. When pgr4 is 0 (page 00), the lower 32KB is selected. When pgr4 is switched to 1 by the user, the upper 32KB is selected. PSDsoft will automatically generate the PLD equations shown, based on your point and click selections. If no FA15 equation is defined in PSDsoft, the A15 that comes from the MCU address bus will be routed as input to the primary Flash memory instead of FA15. The FA15 equation has no impact on the Sector Erase operation. Note: FA15 affects all eight sectors of the primary Flash memory simultaneously. You cannot direct FA15 to a particular Flash sector only. 30/118 PSD835G2V Figure 4. Example for Flash Sector Chip Select FS0 Detailed operation page = [pgr7... pgr0]; “Page Register output “Sector Chip Select Equation FS0 = ((0000h