PSD835G2_04

PSD835G2 Flash PSD, 5V Supply, for 8-bit MCUs 4 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERAL FOR 8-BIT MCUS DUAL BANK FLASH MEMORIES – 4 Mbits of Primary Flash Memory (8 uniform sectors, 64Kbyte) – 256 Kbits of Secondary Flash Memory with 4 sectors – Concurrent operation: READ from one memory while erasing and writing the other 64 KBIT OF BATTERY-BACKED SRAM 52 RECONFIGURABLE I/O PORTS ENHANCED JTAG SERIAL PORT PLD WITH MACROCELLS – Over 3000 Gates of PLD: CPLD and DPLD – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs) – DPLD - user defined internal chip select decoding 52 INDIVIDUALLY CONFIGURABLE I/O PORT PINS They can be used for the following functions: – MCU I/Os – PLD I/Os – Latched MCU address output – Special function I/Os. – I/O ports may be configured as open-drain outputs. IN-SYSTEM PROGRAMMING (ISP) WITH JTAG – Built-in JTAG compliant serial port allows full-chip In-System Programmability – Efficient manufacturing allow easy product testing and programming – Use low cost FlashLINK cable with PC PAGE REGISTER – Internal page register that can be used to expand the microcontroller address space by a factor of 256 PROGRAMMABLE POWER MANAGEMENT Figure 1. Package TQFP80 (U) ■ ■ ■ ■ HIGH ENDURANCE: – 100,000 Erase/WRITE Cycles of Flash Memory – 1,000 Erase/WRITE Cycles of PLD – 15 Year Data Retention 5V±10% SINGLE SUPPLY VOLTAGE STANDBY CURRENT AS LOW AS 50µA MEMORY SPEED – 70ns Flash memory and SRAM access time for VCC = 4.5V to 5.5V – 90ns Flash memory and SRAM access time for VCC = 4.5V to 5.5V March 2004 1/102 PSD835G2 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 First time programming.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Inventory build-up of pre-programmed devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Expensive sockets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Simultaneous READ and WRITE to Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Complex memory mapping.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Separate Program and Data space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PSDsoft. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2. TQFP80 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 1. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3. PSD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2. PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3. JTAG SIgnals on Port E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 In-Application re-Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Methods of Programming Different Functional Blocks of the PSD . . . . . . . . . . . . . . . . . 17 DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4. PSDsoft Development Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PSD REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. Register Address Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 REGISTER BIT DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 6. Data-In Registers – Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Data-Out Registers – Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Direction Registers – Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 9. Control Registers – Ports E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 10. Drive Registers – Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/102 PSD835G2 Table 11. Drive Registers – Ports C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 12. Enable-Out Registers – Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 13. Input Macrocells – Ports A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 14. Output Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 15. Output Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 16. Mask Macrocells A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 17. Mask Macrocells B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 18. Flash Memory Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 19. Flash Boot Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 20. JTAG Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 21. Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 22. PMMR0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 23. PMMR2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 24. VM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 25. Memory_ID0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 26. Memory_ID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 27. Memory Block Size and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . . 25 Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Upper and Lower Block IN MAIN FLASH SECTOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 5. Example for Flash Sector Chip Select FS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 6. Selecting the Upper or Lower Block in a Primary Flash Memory Sector . . . . . . . . . . . . . 26 Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Memory Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 28. Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Read Primary Flash Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Read the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 29. Status Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Data Polling Flag (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Toggle Flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Error Flag (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Erase Time-out Flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3/102 PSD835G2 Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 8. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash Bulk Erase . . . . . . . . . . . . . Flash Sector Erase . . . . . . . . . . . Suspend Sector Erase . . . . . . . . Resume Sector Erase . . . . . . . . . ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 33 . . . . 33 . . . . 33 . . . . 33 SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reset (RESET) Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SECTOR SELECT AND SRAM SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . . 35 Figure 9. Priority Level of Memory and I/O Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Configuration Modes for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . . 36 Separate Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Combined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 10.8031 Memory Modules – Separate Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 11.8031 Memory Modules – Combined Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 12.Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MEMORY ID REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 30. DPLD and CPLD Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 13.PLD Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 14.DPLD Logic Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 15.Macrocell and I/O Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 31. Output Macrocell Port and Data Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 16.CPLD Output Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4/102 PSD835G2 Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 17.Input Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 18.Handshaking Communication Using Input Macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . 48 External Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 19.External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 32. MCUs and their Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 20.An Example of a Typical 8-bit Multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . 51 PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 MCU Bus Interface Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 21.An Example of a Typical 8-bit Non-Multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . 52 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 22.Interfacing the PSD with an 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 33. 80C251 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 34. Interfacing the PSD with the 80C251, with One READ Input . . . . . . . . . . . . . . . . . . . . . 55 Figure 23.Interfacing the PSD with the 80C251, with RD and PSEN Inputs . . . . . . . . . . . . . . . . . . 56 80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 24.Interfacing the PSD with the 80C51X, 8-bit Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 25.Interfacing the PSD with a 68HC11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 26.General I/O Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 35. Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 36. Port Operating Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 37. I/O Port Latched Address Output Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 27.Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 38. Port Configuration Registers (PCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 39. Port Pin Direction Control, Output Enable P.T. Not Defined . . . . . . . . . . . . . . . . . . . . . . 64 Table 40. Port Pin Direction Control, Output Enable P.T. Defined . . . . . . . . . . . . . . . . . . . . . . . . . 64 5/102 PSD835G2 Table 41. Port Direction Assignment Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 42. Drive Register Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 OMC Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 43. Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Ports A,B and C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 28.Port A, B and C Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 29.Port D Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Port E – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Port F – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Port G – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 30.Port E, F, G Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 44. Power-down Mode’s Effect on Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 31.APD Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 45. PSD Timing and Stand-by Current during Power-down Mode . . . . . . . . . . . . . . . . . . . . 71 Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SRAM Standby Mode (Battery Backup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 32.Enable Power-down Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 46. APD Counter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Reset of Flash Memory Erase and Program Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 33.Power-Up and Warm Reset (RESET) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 47. Status During Power-Up Reset, Warm Reset and Power-down Mode . . . . . . . . . . . . . . 75 PROGRAMMING IN-CIRCUIT USING THE JTAG/ISP INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6/102 PSD835G2 Table 48. JTAG Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 34.PLD ICC /Frequency Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 49. Example of PSD Typical Power Calculation at VCC = 5.0V (with Turbo Mode On) . . . . . 79 Table 50. Example of PSD Typical Power Calculation at VCC = 5.0V (with Turbo Mode Off) . . . . . 80 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 51. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 52. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 53. AC Signal Letters for PLD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 54. AC Signal Behavior Symbols for PLD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 55. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 56. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 35.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 36.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 37.Switching Waveforms – Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 57. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 38.Input to Output Disable / Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 39.Combinatorial Timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 58. CPLD Combinatorial Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 59. CPLD Macrocell Synchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 60. CPLD Macrocell Asynchronous Clock Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 40.Synchronous Clock Mode Timing – PLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 41.Asynchronous Reset / Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 42.Asynchronous Clock Mode Timing (Product Term Clock). . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 43.Input Macrocell Timing (Product Term Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 61. Input Macrocell Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 44.READ Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 62. READ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 45.WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 63. WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 46.Peripheral I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 64. Port F Peripheral Data Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 47.Peripheral I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 65. Port F Peripheral Data Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 66. Program, Write and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 67. Power-down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 48.Reset (RESET) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 68. Reset (Reset) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 69. VSTBYON Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 49.ISC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 70. ISC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7/102 PSD835G2 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 50.TQFP80 - 80 lead Thin, Quad, Flat Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 71. TQFP80 - 80 lead Thin, Quad, Flat Package Mechanical Data. . . . . . . . . . . . . . . . . . . . 98 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 72. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 APPENDIX A.PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 73. PSD835G2 TQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 74. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8/102 PSD835G2 SUMMARY DESCRIPTION The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices. The PSD family offers two methods to program the PSD Flash memory while the PSD is soldered to the circuit board: In-System Programming (ISP) via JTAG, and In-Application Programming (IAP). In-System Programming (ISP) via JTAG An IEEE 1149.1 compliant JTAG In-System Programming (ISP) interface is included on the PSD enabling the entire device (Flash memories, PLD, configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU participation, which means the PSD can be programmed anytime, even when completely blank. The innovative JTAG interface to Flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: First time programming. How do I get firmware into the Flash memory the very first time? JTAG is the answer. Program the blank PSD with no MCU involvement. Inventory build-up of pre-programmed devices. How do I maintain an accurate count of preprogrammed Flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer. Build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to the customer. No more labels on chips, and no more wasted inventory. Expensive sockets. How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads. In-Application Programming (IAP) Two independent Flash memory arrays are included so that the MCU can execute code from one while erasing and programming the other. Robust product firmware updates in the field are possible over any communications channel (CAN, Ethernet, UART, J1850, etc.) using this unique architecture. Designers are relieved of these problems: Simultaneous READ and WRITE to Flash memory. How can the MCU program the same memory from which it is executing code? It cannot. The PSD allows the MCU to operate the two Flash memory blocks concurrently, reading code from one while erasing and programming the other during IAP. Complex memory mapping. How can I map these two memories efficiently? A programmable Decode PLD (DPLD) is embedded in the PSD. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extremely high address resolution. As an option, the secondary Flash memory can be swapped out of the system memory map when IAP is complete. A built-in page register breaks the MCU address limit. Separate Program and Data space. How can I write to Flash memory while it resides in Program space during field firmware updates? My 80C51 will not allow it. The PSD provides means to reclassify Flash memory as Data space during IAP, then back to Program space when complete. PSDsoft PSDsoft, a software development tool from ST, guides you through the design process step-bystep making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft takes you through the remainder of the design with point and click entry, covering PSD selection, pin definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI-C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft: FlashLINK (JTAG) and PSDpro. 9/102 PSD835G2 Figure 2. TQFP80 Connections 70 GND 69 VCC 68 PB7 80 PD1 79 PD0 67 PB6 66 PB5 65 PB4 64 PB3 63 PB2 62 PB1 PD2 1 PD3 2 AD0 3 AD1 4 AD2 5 AD3 6 AD4 7 GND 8 VCC 9 AD5 10 AD6 11 AD7 12 AD8 13 AD9 14 AD10 15 AD11 16 AD12 17 AD13 18 AD14 19 AD15 20 61 PB0 78 PE7 77 PE6 76 PE5 75 PE4 74 PE3 73 PE2 72 PE1 71 PE0 60 CNTL1 59 CNTL0 58 PA7 57 PA6 56 PA5 55 PA4 54 PA3 53 PA2 52 PA1 51 PA0 50 GND 49 GND 48 PC7 47 PC6 46 PC5 45 PC4 44 PC3 43 PC2 42 PC1 41 PC0 PG0 21 PG1 22 PG2 23 PG3 24 PG4 25 PG5 26 PG6 27 PG7 28 VCC 29 GND 30 PF0 31 PF1 32 PF2 33 PF3 34 PF4 35 PF5 36 PF6 37 PF7 38 RESET 39 CNTL2 40 AI04943 10/102 PSD835G2 Table 1. Pin Description Pin Name Pin Type Description This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this port. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect A8-A15 to this port. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port. 13-20 I/O If you are using an 80C251 in page mode, connect AD8-AD15 to this port. If you are using an 80C51XA in burst mode, connect A12-A19 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. The following control signals can be connected to this port, based on your MCU: WR – active Low Write Strobe input. CNTL0 59 I R_W – active High READ/active Low WRITE input. This port is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. The following control signals can be connected to this port, based on your MCU: RD – active Low Read Strobe input. E – E clock input. DS – active Low Data Strobe input. CNTL1 60 I PSEN – connect PSEN to this port when it is being used as an active Low READ signal. For example, when the 80C251 outputs more than 16 address bits, PSEN is actually the READ signal. This port is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. This port can be used to input the PSEN (Program Select Enable) signal from any MCU that uses this signal for code exclusively. If your MCU does not output a Program Select Enable signal, this port can be used as a generic input. This port is connected to the PLDs as input. ADIO0-7 3-710-12 I/O ADIO815 CNTL2 40 I 11/102 PSD835G2 Pin Name Reset Pin Type Description Active Low input. Resets I/O Ports, PLD macrocells and some of the Configuration Registers and JTAG registers. Must be Low at Power-up. Reset also aborts the Flash programming/erase cycle that is in progress. These pins make up Port A. These port pins are configurable and can have the following functions: MCU I/O – write to or read from a standard output or input port. 39 I PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 58 57 56 55 54 53 52 51 68 67 66 65 64 63 62 61 48 47 46 45 44 43 42 41 I/O CMOS or Open Drain CPLD macrocell (McellA0-7) outputs. Inputs to the PLDs. Latched, transparent or registered PLD input. These pins make up Port B. These port pins are configurable and can have the following functions: MCU I/O – write to or read from a standard output or input port. I/O CMOS or Open Drain CPLD macrocell (McellB0-7) output. Inputs to the PLDs. Latched, transparent or registered PLD input. These pins make up Port C. These port pins are configurable and can have the following functions: MCU I/O – write to or read from a standard output or input port. External Chip Select (ECS0-7) output. Latched, transparent or registered PLD input. PD0 pin of Port D. This port pin can be configured to have the following functions: ALE/AS input latches addresses on ADIO0-ADIO15 pins. I/O CMOS or Open Drain PD0 79 I/O CMOS or Open Drain AS input latches addresses on ADIO0-ADIO15 pins on the rising edge. Input to the PLDs. Transparent PLD input. PD1 pin of Port D. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. PD1 80 I/O CMOS or Open Drain Input to the PLDs. CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter, and the CPLD AND Array. PD2 pin of Port D. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. PD2 1 I/O CMOS or Open Drain Input to the PLDs. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/O. When High, the PSD memory blocks are disabled to conserve power. The trailing edge of CSI can be used to get the PSD out of power-down mode. 12/102 PSD835G2 Pin Name Pin Type I/O CMOS or Open Drain Description PD3 pin of Port D. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Input to the PLDs. PE0 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address output. TMS input for JTAG/ISP interface. PE1 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address output. TCK input for JTAG/ISP interface (Schmidt Trigger). PE2 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address output. TDI input for JTAG/ISP interface. PE3 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address output. TDO input for JTAG/ISP interface. PE4 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. PD3 2 PE0 71 I/O CMOS or Open Drain PE1 72 I/O CMOS or Open Drain PE2 73 I/O CMOS or Open Drain PE3 74 I/O CMOS or Open Drain PE4 75 I/O CMOS or Open Drain Latched address output. TSTAT input for the ISP interface. Ready/Busy for in-circuit Parallel Programming. PE5 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address output. TERR active Low input for ISP interface. PE6 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address output. VSTBY SRAM standby voltage input for battery backup SRAM. PE5 76 I/O CMOS or Open Drain PE6 77 I/O CMOS or Open Drain 13/102 PSD835G2 Pin Name Pin Type Description PE7 pin of Port E. This port pin can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. PE7 78 I/O CMOS or Open Drain Latched address output. VBATON battery backup indicator output. Goes High when power is drawn from an external battery. PF0 through PF7 pins of Port F. This port pins can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. PF0-PF7 31-38 I/O CMOS or Open Drain Input to the PLDs. Latched address outputs. As address A0-A3 inputs in 80C51XA mode. As data bus port (D07) in non-multiplexed bus configuration. PG0PG7 8, 30, 49, 50, 70 9, 29, 69 8, 30, 49, 50, 70 I/O CMOS or Open Drain PG0 through PG7 pins of Port G. This port pins can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Latched address outputs. VCC Supply Voltage GND Ground pins 14/102 ADDRESS/DATA/CONTROL BUS PLD INPUT BUS PAGE REGISTER EMBEDDED ALGORITHM 8 SECTORS POWER MANGMT UNIT 4 MBIT PRIMARY FLASH MEMORY Figure 3. PSD Block Diagram VSTDBY (PE6 ) CNTL0, CNTL1, CNTL2 SECTOR SELECTS FLASH DECODE PLD (DPLD) 82 SECTOR SELECTS SRAM SELECT PERIP I/O MODE SELECTS ADIO PORT CSIOP RUNTIME CONTROL AND I/O REGISTERS 8 EXT CS TO PORT C OR F 16 OUTPUT MACROCELLS PROG. PORT PORT F CLKIN PORT A & B 24 INPUT MACROCELLS PORT A ,B & C 64 KBIT BATTERY BACKUP SRAM PROG. MCU BUS INTRF. 256 KBIT SECONDARY FLASH MEMORY (BOOT OR DATA) 4 SECTORS PROG. PORT PA0 – PA7 AD0 – AD15 PORT A PROG. PORT PORT B PB0 – PB7 82 FLASH ISP CPLD (CPLD) PF0 –PF7 PROG. PORT PORT C PC0 – PC7 MACROCELL FEEDBACK OR PORT INPUT CLKIN PORT F PROG. PORT PORT D PD0 – PD2 PG0 – PG7 PORT G PROG. PORT PROG. PORT PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PORT E PE0 – PE7 CLKIN (PD1) GLOBAL CONFIG. & SECURITY PSD835G2 AI05793b 15/102 PSD835G2 PSD ARCHITECTURAL OVERVIEW PSD devices contain several major functional blocks. Figure 3., page 15 shows the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in the section entitled Memory Blocks, page 24. The 4 Mbit (512K x 8) Flash memory is the primary memory of the PSD. It is divided into 8 equally-sized sectors that are individually selectable. The 256 Kbit (32K x 8) secondary Flash memory is divided into 4 equally-sized sectors. Each sector is individually selectable. The 64 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. If an external battery is connected to Voltage Standby (VSTBY, PC2), data is retained in the event of power failure. Each sector of memory can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time. Page Register The 8-bit Page Register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page Register can also be used to change the address mapping of sectors of the Flash memories into different memory spaces for IAP. PLDs The device contains two PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 2, each optimized for a different function. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The DPLD is used to decode addresses and to generate Sector Select signals for the PSD internal memory and registers. The CPLD can implement user-defined logic functions. The DPLD has combinatorial outputs. The CPLD has 16 Output Macrocells (OMC) and 8 combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of product terms, and macrocells. The PLDs consume minimal power by using Power-Management design techniques. The speed and power consumption of the PLD is controlled by the Turbo Bit in PMMR0 and other bits in the PMMR2. These registers are set by the MCU at run-time. There is a slight penalty to PLD propagation time when invoking the power management features. I/O Ports The PSD has 52 I/O pins distributed over the seven ports (Port A, B, C, D, E, F and G). Each I/O pin can be individually configured for different functions. Ports can be configured as standard MCU I/ O ports, PLD I/O, or latched address outputs for MCUs using multiplexed address/data buses. The JTAG pins can be enabled on Port E for InSystem Programming (ISP). Ports F and G can also be configured as data ports for a non-multiplexed bus. Ports A and B can also be configured as a data port for a non-multiplexed bus. MCU Bus Interface PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU’s control signals, which are also used as inputs to the PLDs. For examples, please see MCU Bus Interface Examples, page 52. Table 2. PLD I/O Name Decode PLD (DPLD) Complex PLD (CPLD) Inputs 82 82 Outputs 17 24 Product Terms 43 150 Table 3. JTAG SIgnals on Port E Port E Pins PE0 PE1 PE2 PE3 PE4 PE5 TMS TCK TDI TDO TSTAT TERR JTAG Signal 16/102 PSD835G2 JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port E. This serial interface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port E. Table 3., page 16 indicates the JTAG pin assignments. In-System Programming (ISP) Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can be programmed or erased without the use of the MCU. In-Application re-Programming (IAP) The primary Flash memory can also be programmed in-system by the MCU executing the programming algorithms out of the secondary memory, or SRAM. Since this is a sizable separate block, the application can also continue to operate. The secondary memory can be programmed the same way by executing out of the primary Flash memory. The PLD or other PSD Configuration blocks can be programmed through the JTAG port or a device programmer. Table 4 indicates which programming methods can program different functional blocks of the PSD. Power Management Unit (PMU) The Power Management Unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit has a Power-down mode that helps reduce power consumption. The PSD also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to ’0’ and the CPLD latches its outputs and goes to sleep until the next transition on its inputs. Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD to reduce power consumption. Please see POWER MANAGEMENT, page 70 for more details. Table 4. Methods of Programming Different Functional Blocks of the PSD Functional Block Primary Flash Memory Secondary Flash Memory PLD Array (DPLD and CPLD) PSD Configuration Yes Yes Yes Yes JTAG/ISP Device Programmer Yes Yes Yes Yes Yes Yes No No IAP 17/102 PSD835G2 DEVELOPMENT SYSTEM The PSD family is supported by PSDsoft, a Windows-based (95, 98, NT) software development tool. A PSD design is quickly and easily produced in a point-and-click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 4. PSDsoft is available from our web site (the address is given on the back page of this data sheet) or other distribution channels. Figure 4. PSDsoft Development Tool PSDsoft directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/representative, or directly from our web site using a credit card. The PSD is also supported by third party device programmers. See our web site for the current list. Choose MCU and PSD Automatically Configures MCU bus interface and other PSD attributes. Define PSD Pin and Node Functions Point-and-click definition of PSD pin functions, internal nodes and MCU system memory map Define General Purpose Logic in CPLD Point-and-click definition of combinatorial and registered logic in CPLD. Access to HDL is available if needed. C Code Generation GENERATE C CODE SPECIFIC TO PSD FUNCTIONS Merge MCU Firmware with PSD Configuration A composite object file is created containing MCU firmware and PSD configuration MCU FIRMWARE HEX OR S-RECORD FORMAT USER'S CHOICE OF MICROCONTROLLER COMPILER/LINKER *.OBJ FILE ST PSD Programmer PSDPro, or FlashLINK (JTAG) *.OBJ FILE AVAILABLE FOR 3rd PARTY PROGRAMMERS (CONVENTIONAL or JTAG/ISP) AI04918b 18/102 PSD835G2 PSD REGISTER DESCRIPTION AND ADDRESS OFFSET Table 5 shows the offset addresses to the PSD registers relative to the CSIOP base address. The CSIOP space is the 256 Bytes of address that is allocated by the user to the internal PSD registers. Table 5. Register Address Offset Register Name Data In Control Data Out Direction 04 06 05 07 14 14 15 15 Port A 00 Port B 01 Port C 10 Port D 11 Port E 30 32 34 36 Port F 40 42 44 46 Port G 41 43 45 47 Other 1 Table 5 provides brief descriptions of the registers in CSIOP space. The following section gives a more detailed description. Description Reads Port pin as input, MCU I/ O input mode Selects mode between MCU I/O or Address Out Stores data for output to Port pins, MCU I/O output mode Configures Port pin as input or output Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins. Reads Input Macrocells Reads the status of the output enable to the I/O Port driver READ – reads output of macrocells A WRITE – loads macrocell flipflops Drive Select Input Macrocell Enable Out Output Macrocells A 08 0A 0C 09 0B 0D 18 19 1A 38 48 49 1C 1B 4C 20 Output Macrocells B Mask Macrocells A Mask Macrocells B Primary Flash Protection Secondary Flash memory Protection JTAG Enable PMMR0 PMMR2 Page VM Memory_ID0 Memory_ID1 22 21 READ – reads output of macrocells B WRITE – loads macrocell flipflops Blocks writing to the Output Macrocells A 23 C0 C2 C7 B0 B4 E0 E2 F0 F1 Blocks writing to the Output Macrocells B Read only – Primary Flash Sector Protection Read only – PSD Security and Secondary Flash memory Sector Protection Enables JTAG Port Power Management Register 0 Power Management Register 2 Page Register Places PSD memory areas in Program and/or Data space on an individual basis. Read only – Primary Flash memory and SRAM size Read only – Secondary Flash memory type and size Note: 1. Other registers that are not part of the I/O ports. 19/102 PSD835G2 REGISTER BIT DEFINITION All the registers of the PSD are included here, for reference. Detailed descriptions of these registers can be found in the following sections. Table 6. Data-In Registers – Ports A, B, C, D, E, F, G Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 Note: Bit Definitions (Read only registers): Read Port pin status when Port is in MCU I/O input mode. Table 7. Data-Out Registers – Ports A, B, C, D, E, F, G Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 Note: Bit Definitions: Latched data for output to Port pin when pin is configured in MCU I/O output mode. Table 8. Direction Registers – Ports A, B, C, D, E, F, G Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 Note: Bit Definitions: Port pin 0 = Port pin is configured in Input mode (default). Port pin 1 = Port pin is configured in Output mode. Table 9. Control Registers – Ports E, F, G Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 Note: Bit Definitions: Port pin 0 = Port pin is configured in MCU I/O mode (default). Port pin 1 = Port pin is configured in Latched Address Out mode. Table 10. Drive Registers – Ports A, B, D, E, G Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 Note: Bit Definitions: Port pin 0 = Port pin is configured for CMOS Output driver (default). Port pin 1 = Port pin is configured for Open Drain output driver. Table 11. Drive Registers – Ports C, F Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 Note: Bit Definitions: Port pin 0 = Port pin is configured for CMOS Output driver (default). Port pin 1 = Port pin is configured in Slew Rate mode. 20/102 PSD835G2 Table 12. Enable-Out Registers – Ports A, B, C, F Bit 7 Port pin 7 Bit 6 Port pin 6 Bit 5 Port pin 5 Bit 4 Port pin 4 Bit 3 Port pin 3 Bit 2 Port pin 2 Bit 1 Port pin 1 Bit 0 Port pin 0 Note: Bit Definitions (Read only registers): Port pin 0 = Port pin is in tri-state driver (default). Port pin 1 = Port pin is enabled. Table 13. Input Macrocells – Ports A, B, C Bit 7 IMcell 7 Bit 6 IMcell 6 Bit 5 IMcell 5 Bit 4 IMcell 4 Bit 3 IMcell 3 Bit 2 IMcell 2 Bit 1 IMcell 1 Bit 0 IMcell 0 Note: Bit Definitions (Read only registers): Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C. Table 14. Output Macrocells A Register Bit 7 Mcella 7 Bit 6 Mcella 6 Bit 5 Mcella 5 Bit 4 Mcella 4 Bit 3 Mcella 3 Bit 2 Mcella 2 Bit 1 Mcella 1 Bit 0 Mcella 0 Note: Bit Definitions: Write Register: Load MCellA7-MCellA0 with '0' or '1.' Read Register: Read MCellA7-MCellA0 output status. Table 15. Output Macrocells B Register Bit 7 Mcellb 7 Bit 6 Mcellb 6 Bit 5 Mcellb 5 Bit 4 Mcellb 4 Bit 3 Mcellb 3 Bit 2 Mcellb 2 Bit 1 Mcellb 1 Bit 0 Mcellb 0 Note: Bit Definitions: Write Register: Load MCellB7-MCellB0 with '0' or '1.' Read Register: Read MCellB7-MCellB0 output status. Table 16. Mask Macrocells A Register Bit 7 Mcella 7 Bit 6 Mcella 6 Bit 5 Mcella 5 Bit 4 Mcella 4 Bit 3 Mcella 3 Bit 2 Mcella 2 Bit 1 Mcella 1 Bit 0 Mcella 0 Note: Bit Definitions: McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default). McellA_Prot 1 = Prevent MCellA flip-flop from being loaded by MCU. Table 17. Mask Macrocells B Register Bit 7 Mcellb 7 Bit 6 Mcellb 6 Bit 5 Mcellb 5 Bit 4 Mcellb 4 Bit 3 Mcellb 3 Bit 2 Mcellb 2 Bit 1 Mcellb 1 Bit 0 Mcellb 0 Note: Bit Definitions: McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default). McellB_Prot 1 = Prevent MCellB flip-flop from being loaded by MCU. Table 18. Flash Memory Protection Register Bit 7 Sec7_Prot Bit 6 Sec6_Prot Bit 5 Sec5_Prot Bit 4 Sec4_Prot Bit 3 Sec3_Prot Bit 2 Sec2_Prot Bit 1 Sec1_Prot Bit 0 Sec0_Prot Note: Bit Definitions (Read only register): Sec_Prot 1 = Primary Flash memory Sector is write protected. Sec_Prot 0 = Primary Flash memory Sector is not write protected. 21/102 PSD835G2 Table 19. Flash Boot Protection Register Bit 7 Security_Bit Bit 6 not used Bit 5 not used Bit 4 not used Bit 3 Sec3_Prot Bit 2 Sec2_Prot Bit 1 Sec1_Prot Bit 0 Sec0_Prot Note: Bit Definitions: Sec_Prot 1 = Secondary Flash memory Sector is write protected. Sec_Prot 0 = Secondary Flash memory Sector is not write protected. Security_Bit 0 = Security Bit in device has not been set. Security_Bit 1 = Security Bit in device has been set. Table 20. JTAG Enable Register Bit 7 not used Bit 6 not used Bit 5 not used Bit 4 not used Bit 3 not used Bit 2 not used Bit 1 not used Bit 0 JTAGEnable Note: Bit Definitions: JTAG_Enable 1 = JTAG Port is enabled. JTAG_Enable 0 = JTAG Port is disabled. Table 21. Page Register Bit 7 PGR 7 Bit 6 PGR 6 Bit 5 PGR 5 Bit 4 PGR 4 Bit 3 PGR 3 Bit 2 PGR 2 Bit 1 PGR 1 Bit 0 PGR 0 Note: Bit Definitions: Configure Page input to PLD. Default is PGR7-PGR0=00. Table 22. PMMR0 Register Bit 7 not used (set to ’0’) Bit 6 not used (set to ’0’) Bit 5 PLD MCells CLK Bit 4 PLD Array CLK Bit 3 PLD Turbo Bit 2 not used (set to ’0’) Bit 1 APD Enable Bit 0 not used (set to ’0’) Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers. 2. Bit Definitions: APD Enable0 = Automatic Power-down (APD) is disabled. 1 = Automatic Power-down (APD) is enabled. PLD Turbo0 = PLD Turbo is on. 1 = PLD Turbo is off, saving power. PLD Array CLK0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo Bit is off. 1 = CLKIN to the PLD AND array is disconnected, saving power. PLD MCells CLK0 = CLKIN to the PLD Macrocells is connected. 1 = CLKIN to the PLD Macrocells is disconnected, saving power. Table 23. PMMR2 Register Bit 7 not used (set to ’0’) Bit 6 PLD Array WRH Bit 5 PLD Array ALE Bit 4 PLD Array CNTL2 Bit 3 PLD Array CNTL1 Bit 2 PLD Array CNTL0 Bit 1 not used (set to ’0’) Bit 0 PLD Array Addr Note: Bit Definitions: PLD Array Addr 0 = Address A7-A0 are connected to the PLD array. 1 = Address A7-A0 are blocked from the PLD array, saving power. (Note: in XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4) PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected. 1 = CNTL2 input to the PLD AND array is disconnected, saving power. PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected. 1 = CNTL1 input to the PLD AND array is disconnected, saving power. PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected. 1 = CNTL0 input to the PLD AND array is disconnected, saving power. PLD Array ALE 0 = ALE input to the PLD AND array is connected. 1 = ALE input to the PLD AND array is disconnected, saving power. PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected. 1 = WRH/DBE input to the PLD AND array is disconnected, saving power. 22/102 PSD835G2 Table 24. VM Register Bit 7 Peripheral mode Bit 6 not used (set to ’0’) Bit 5 not used (set to ’0’) Bit 4 FL_data Bit 3 Boot_data Bit 2 FL_code Bit 1 Boot_code Bit 0 SR_code Note: 1. On reset, Bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft. Bit0 and Bit7 are always cleared on reset. Bit0-Bit4 are active only when the device is configured in Philips 80C51XA mode. 2. Bit Definitions: SR_code0 = PSEN cannot access SRAM in 80C51XA modes. 1 = PSEN can access SRAM in 80C51XA modes. Boot_code0 = PSEN cannot access Secondary NVM in 80C51XA modes. 1 = PSEN can access Secondary NVM in 80C51XA modes. FL_code0 = PSEN cannot access Primary Flash memory in 80C51XA modes. 1 = PSEN can access Primary Flash memory in 80C51XA modes. Boot_data0 = RD cannot access Secondary NVM in 80C51XA modes. 1 = RD can access Secondary NVM in 80C51XA modes. FL_data0 = RD cannot access Primary Flash memory in 80C51XA modes. 1 = RD can access Primary Flash memory in 80C51XA modes. Peripheral mode0 = Peripheral mode of Port F is disabled. 1 = Peripheral mode of Port F is enabled. Table 25. Memory_ID0 Register Bit 7 S_size 3 Bit 6 S_size 2 Bit 5 S_size 1 Bit 4 S_size 0 Bit 3 F_size 3 Bit 2 F_size 2 Bit 1 F_size 1 Bit 0 F_size 0 Note: Bit Definitions: F_size[3:0] S_size[3:0] 4h = Primary Flash memory size is 4 Mbit 5h = Primary Flash memory size is 8Mbit 0h = There is no SRAM 1h = SRAM size is 16 Kbit 3h = SRAM size is 64 Kbit Table 26. Memory_ID1 Register Bit 7 not used (set to ’0’) Bit 6 not used (set to ’0’) Bit 5 B_type 1 Bit 4 B_type 0 Bit 3 B_size 3 Bit 2 B_size 2 Bit 1 B_size 1 Bit 0 B_size 0 Note: Bit Definitions: B_size[3:0] B_type[1:0] 0h = There is no Secondary NVM 2h = Secondary NVM size is 256 Kbit 0h = Secondary NVM is Flash memory 1h = Secondary NVM is EEPROM 23/102 PSD835G2 DETAILED OPERATION As shown in Figure 3., page 15, the PSD consists of six major types of functional blocks: ■ Memory Blocks ■ PLD Blocks ■ MCU Bus Interface ■ I/O Ports ■ Power Management Unit (PMU) ■ JTAG/ISP Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. Table 27. Memory Block Size and Organization Primary Flash Memory Sector Number 0 1 2 3 4 5 6 7 Total Sector Size (Bytes) 64K 64K 64K 64K 64K 64K 64K 64K 512K Sector Select Signal FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 8 Sectors 32K 4 Sectors 16K Secondary Flash Memory Sector Size (Bytes) 8K 8K 8K 8K Sector Select Signal CSBOOT0 CSBOOT1 CSBOOT2 CSBOOT3 SRAM SRAM Size (Bytes) 16K SRAM Select Signal RS0 Memory Blocks The PSD has the following memory blocks: – Primary Flash memory – Secondary Flash memory – SRAM The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are userdefined in PSDsoft. 24/102 PSD835G2 Primary Flash Memory and Secondary Flash memory Description The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash memory is divided into four equal sectors of eight KBytes each. Each sector of either memory block can be separately protected from Program and Erase cycles. Flash memory may be erased on a sector-by-sector basis and programmed Word-by-Word. Flash sector erasure may be suspended while data is read from other sectors of the block and then resumed after reading. During a Program or Erase cycle in Flash memory, the status can be output on Ready/Busy (PE4). This pin is set up using PSDsoft. Memory Block Select Signals The DPLD generates the Select signals for all the internal memory blocks (see PLDs, page 38). Each of the eight sectors of the primary Flash memory has a Select signal (FS0-FS7) which can contain up to three product terms. Each of the four sectors of the secondary Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped in different areas of system memory. When using an MCU with separate Program and Data space, these flexible Select signals allow dynamic re-mapping of sectors from one memory space to the other before and after IAP. Upper and Lower Block IN MAIN FLASH SECTOR The PSD835G2’s main Flash memory has eight 64-KByte sectors. The 64-KByte sector size may cause some difficulty in code mapping for an 8-bit MCU with only 64-KByte address space. To resolve this mapping issue, the PSD835G2 provides additional logic (see Figure 6., page 26) for the user to split the 8 sectors such that each sector has a lower and upper 32-KByte block, and the two blocks can reside in different pages but in the same address range. If your design works with 64KB sectors, you don’t need to configure this logic. If the design requires 32KB blocks in each sector, you need to define a “FA15” PLD equation in PSDsoft as the A15 address input to the main Flash module. FA15 consists of 3 product terms and will control whether the MCU is accessing the lower or upper 32KB in the selected sector. Figure 4 shows an example for Flash sector chip select FS0. A typical equation is FA15 = pgr4 of the Page Register. When pgr4 is 0 (page 00), the lower 32KB is selected. When pgr4 is switched to ’1’ by the user, the upper 32KB is selected. PSDsoft will automatically generate the PLD equations shown, based on your point and click selections. If no FA15 equation is defined in PSDsoft, the A15 that comes from the MCU address bus will be routed as input to the primary Flash memory instead of FA15. The FA15 equation has no impact on the Sector Erase operation. Note: FA15 affects all eight sectors of the primary Flash memory simultaneously. You cannot direct FA15 to a particular Flash sector only. Figure 5. Example for Flash Sector Chip Select FS0 page = [pgr7... pgr0]; “Page Register output “Sector Chip Select Equation FS0 = ((0000h