RF3L05250CB4

RF3L05250CB4 Datasheet 250 W, 28/32 V, HF to 1 GHz RF power LDMOS transistor Features 1 2 Order code Frequency VDD POUT Gain Efficiency RF3L05250CB4 650 MHz 28 V 250 W 18 dB 62% 5 4 3 LBB • • • • High efficiency and linear gain operations Integrated ESD protection Large positive and negative gate-source voltage range for improved class C operation In compliance with the European directive 2002/95/EC Pin connection Pin Connection 1 Drain A 2 Drain B 3 Source (bottom side) 4 Gate B 5 Gate A Applications • • • • • • 2-30 MHz HF or short wave communication 30-88 MHz ground communication 118-140 MHz Avionics 136-174 MHz commercial ground communication 30-512 MHz Jammer, ground/air communication HF to 1000 MHz ISM - instrumentation Description The RF3L05250CB4 is a 250 W, 28/32 V, LDMOS FET designed for wideband communication and ISM applications in the frequency range from HF to 1 GHz. It can be used in class AB, B or C for all typical modulation formats. Product status link RF3L05250CB4 Product summary Order code RF3L05250CB4 Marking 3L05250 Package LBB Packing Tape and reel 13" Base/bulk quantity 100/100 DS13360 - Rev 2 - September 2021 For further information contact your local STMicroelectronics sales office. www.st.com RF3L05250CB4 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings (TC = 25 °C) Symbol Parameter Value Unit VDS Drain-source voltage 90 V VGS Gate-source voltage -8 to 10 V VDD Maximum operating voltage 36 V TSTG Storage temperature range -65 to 150 °C 200 °C Value Unit 0.32 °C/W TJ Maximum junction temperature Table 2. Thermal data Symbol RthJC(1) Parameter Thermal resistance, junction-to-case 1. TC = 85 °C , TJ = 200 °C, DC test. Table 3. ESD protection Symbol DS13360 - Rev 2 Test methodology HBM Human body model (according to ANSI/ESDA/JEDEC JS001-2017) CDM Charge device model (according to ANSI/ESDA/JEDEC JS002-2014) Class 2 C3 page 2/12 RF3L05250CB4 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified. Table 4. Static Symbol Parameter Test conditions Min. Max. Unit V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage drain leakage current IGSS Gate-source leakage current VGS = -8/10 V, VDS = 0 V VGS(th) Gate threshold voltage VDS = 42 V, ID = 600 µA VGS(Q) Gate quiescent voltage VDS = 28 V, ID = 700 mA VDS(on) Static drain-source on-voltage VGS = 10 V, ID = 3 A 550 mV IDS(on) Static drain-source on-current VGS = 10 V, VDS = 100 mV 2.5 A RDS(on) Drain-source on-state resistance VGS = 10 V, VDS = 100 mV 1 Ω CISS Common source input capacitance CRSS Common source feedback capacitance COSS Common source output capacitance VGS = 0 V, ID = 100 µA Typ. 90 V VGS = 0 V, VDS = 28 V 1 VGS = 0 V, VDS = 75 V 1 1.75 μA ±100 nA 2.50 V 3.0 V 128 pF 2.4 pF 43 pF VGS = 0 V, VDD = 28 V, f = 1 MHz Table 5. Dynamic Symbol f Note: DS13360 - Rev 2 Parameter Test conditions Min. Typ. Frequency POUT Output power GPS Power gain ηD Drain efficiency VSWR Load mismatch f = 650 MHz, 2.5 dB compression POUT = 250 W, all phases Max. Unit 1000 MHz 250 W 18 dB 62 % 10:1 VDD = 28 V, IDQ = 100 mA, CW test signal. page 3/12 RF3L05250CB4 Typical performances 3 Typical performances Table 6. Output power, power gain and drain efficiency vs input power (f = 650 MHz) PIN (dBm) POUT (dBm) POUT (W) IDS (A) GPS (dB) ηD(%) 23.65 43.18 21 3.65 19.53 20 24.67 44.45 28 4.25 19.78 23 25.68 45.65 37 4.91 19.97 27 26.69 46.84 48 5.66 20.15 30 27.7 47.97 63 6.49 20.27 34 28.72 49.05 80 7.41 20.33 39 29.71 50 100 8.38 20.29 43 30.73 50.94 124 9.38 20.21 47 31.73 51.69 148 10.35 19.96 51 32.74 52.34 171 11.31 19.6 54 33.74 52.94 197 12.25 19.2 57 34.76 53.43 220 13.15 18.67 60 35.76 53.88 244 14.02 18.12 62 36.74 54.23 265 14.71 17.49 64 22 GADG290920210929GT 80 21 70 20 60 19 50 18 40 17 30 16 20 15 Drain efficiency, ηD (%) Power gain, GPS (dB) Figure 1. Power gain and drain efficiency versus output power (f = 650 MHz) 10 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 POUT (dbm) GPS Note: DS13360 - Rev 2 ηD VDD = 28 V, IDQ =100 mA, CW test signal. page 4/12 RF3L05250CB4 Test circuits 4 Test circuits Figure 2. Test circuit layout (f = 650 MHz) 3L05250 Figure 3. Test circuit photo 3L05250 DS13360 - Rev 2 page 5/12 RF3L05250CB4 Test circuits Table 7. Components list Component Value Reference C1, C18, C20, C21, C24, C25 47 pF ATC800B C2, C3 120 pF ATC800B C4, C5 2 pF DLC70B C6, C12 10 pF ATC800B C7 20 pF DLC70B C8, C10 15 pF DLC70B C9, C13 6.8 pF DLC70B C11 4.7 pF DLC70B C14 1.8 pF DLC70B C15 3.9 pF DLC70B C16, C17 240 pF DLC70B C29, C30 1000 pF ATC800B C19, C22, C23, C26 10 uF 50 V ceramic multilayer capacitor C27, C28 470 uF 63 V electrolytic capacitor R1, R2 200 Ω Metal film resistor R3, R4 13 Ω 0805 chip resistor L1, L2 Φ 0.8 mm Copper wire T1, T2, T3, T4 25 Ω, line length = 50 mm SF-086-25 PCB DS13360 - Rev 2 0.762 mm [0.030’’] thick, εr = 3.48, Rogers RO4350B, 1 oz. copper page 6/12 RF3L05250CB4 Package information 5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 5.1 LBB package information Figure 4. LBB package outline A B C Ex4 N M G S L I H F CH2 x 45° R1 x 2 D R2 x 4 CH1 x 45° T S R P Q DM00666717_2 DS13360 - Rev 2 page 7/12 RF3L05250CB4 LBB package information Table 8. LBB mechanical data Symbol Millimeters Min. Typ. Max. A 28.82 28.95 29.08 B 22.73 22.86 22.99 C 16.87 17.00 17.13 E 5.32 5.45 5.58 F 1.01 1.14 1.27 H 5.72 5.85 5.98 I 5.72 5.85 5.98 L 17.65 17.78 17.91 M 1.02 1.15 1.28 N DS13360 - Rev 2 0.10 P 4.72 4.85 4.98 Q 16.38 16.51 16.64 R 1.37 1.50 1.63 S 1.97 2.10 2.23 T 6.60 CH1 2.72 CH2 1.02 R1 1.65 R2 0.50 page 8/12 RF3L05250CB4 Marking information 5.2 Marking information Figure 5. Marking composition PACKAGE FACE : TOP LEGEND Unmarkable Surface Marking Composition Field A - STANDARD ST LOGO B - ECO level (e4) A C - MARKING AREA D - ADDITIONAL INFORMATION B (MAX CHAR ALLOWED = 7) E - COUNTRY OF ORIGIN C (MAX CHAR ALLOWED = 3) F - Assy Plant D E F G H (PP) G - Assy Year (Y) H - Assy Week (WW) GADG040220211644GT DS13360 - Rev 2 page 9/12 RF3L05250CB4 Revision history Table 9. Document revision history Date Revision 16-Jun-2020 1 Changes First release Updated title and Device summary in cover page. Updated Section 1 Electrical ratings. Updated Section 2 Electrical characteristics. 29-Sep-2021 2 Updated Figure 1. Power gain and drain efficiency versus output power (f = 650 MHz). Updated Section 4 Test circuits. Added Section 5.2 Marking information. Minor text changes. DS13360 - Rev 2 page 10/12 RF3L05250CB4 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Typical performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 4 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 5 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1 LBB package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.2 Marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 DS13360 - Rev 2 page 11/12 RF3L05250CB4 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS13360 - Rev 2 page 12/12