RIVA128

® ™ RIVA 128™ 128-BIT 3D MULTIMEDIA ACCELERATOR DESCRIPTION The RIVA 128™ is the first 128-bit 3D Multimedia Accelerator to offer unparalleled 2D and 3D performance, meeting all the requirements of the mainstream PC graphics market and Microsoft’s PC’97. The RIVA 128 introduces the most advanced Direct3D™ acceleration solution and also delivers leadership VGA, 2D and Video performance, enabling a range of applications from 3D games through to DVD, Intercast™ and video conferencing. KEY FEATURES • Fast 32-bit VGA/SVGA • High performance 128-bit 2D/GUI/DirectDraw Acceleration • Interactive, Photorealistic Direct3D Acceleration with advanced effects • Massive 1.6Gbytes/s, 100MHz 128-bit wide frame buffer interface • Video Acceleration for DirectDraw/DirectVideo, MPEG-1/2 and Indeo® - Planar 4:2:0 and packed 4:2:2 Color Space Conversion - X and Y smooth up and down scaling • 230MHz Palette-DAC supporting up to 1600x1200@75Hz • NTSC and PAL output with flicker-filter • Multi-function Video Port and serial interface • Bus mastering DMA 66MHz Accelerated Graphics Port (AGP) 1.0 Interface • Bus mastering DMA PCI 2.1 interface • 0.35 micron 5LM CMOS • 300 PBGA BLOCK DIAGRAM 1.6 GByte/s Internal Bus Bandwidth DMA Bus DMA Engine Video Port CCIR656 Video PCI/AGP Host Interface FIFO/ DMA Pusher Graphics Engine 128 bit 2D Direct3D DMA Engine VGA Internal Bus Palette DAC YUV - RGB, X & Y scaler Monitor/ TV SGRAM Interface 128 bit interface October 1997 The information in this datasheet is subject to change 42 1687 01 (SGS-THOMSON) 1/77 RIVA 128 128-BIT 3D MULTIMEDIA ACCELERATOR TABLE OF CONTENTS 1 1 2 REVISION HISTORY ...................................................................................................................... RIVA 128 300PBGA DEVICE PINOUT .......................................................................................... PIN DESCRIPTIONS ...................................................................................................................... 2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE ..................................................... 2.2 PCI 2.1 LOCAL BUS INTERFACE ........................................................................................ 2.3 SGRAM FRAMEBUFFER INTERFACE ................................................................................ 2.4 VIDEO PORT......................................................................................................................... 2.5 DEVICE ENABLE SIGNALS.................................................................................................. 2.6 DISPLAY INTERFACE .......................................................................................................... 2.7 VIDEO DAC AND PLL ANALOG SIGNALS .......................................................................... 2.8 POWER SUPPLY .................................................................................................................. 2.9 TEST...................................................................................................................................... OVERVIEW OF THE RIVA 128 ...................................................................................................... 3.1 BALANCED PC SYSTEM...................................................................................................... 3.2 HOST INTERFACE ............................................................................................................... 3.3 2D ACCELERATION ............................................................................................................. 3.4 3D ENGINE ........................................................................................................................... 3.5 VIDEO PROCESSOR............................................................................................................ 3.6 VIDEO PORT......................................................................................................................... 3.7 DIRECT RGB OUTPUT TO LOW COST PAL/NTSC ENCODER ......................................... 3.8 SUPPORT FOR STANDARDS.............................................................................................. 3.9 RESOLUTIONS SUPPORTED.............................................................................................. 3.10 CUSTOMER EVALUATION KIT............................................................................................ 3.11 TURNKEY MANUFACTURING PACKAGE........................................................................... ACCELERATED GRAPHICS PORT (AGP) INTERFACE ............................................................. 4.1 RIVA 128 AGP INTERFACE ................................................................................................. 4.2 AGP BUS TRANSACTIONS.................................................................................................. PCI 2.1 LOCAL BUS INTERFACE................................................................................................. 5.1 RIVA 128 PCI INTERFACE ................................................................................................... 5.2 PCI TIMING SPECIFICATION............................................................................................... SGRAM FRAMEBUFFER INTERFACE......................................................................................... 6.1 SGRAM INITIALIZATION ...................................................................................................... 6.2 SGRAM MODE REGISTER .................................................................................................. 6.3 LAYOUT OF FRAMEBUFFER CLOCK SIGNALS ................................................................ 6.4 SGRAM INTERFACE TIMING SPECIFICATION .................................................................. VIDEO PLAYBACK ARCHITECTURE........................................................................................... 7.1 VIDEO SCALER PIPELINE ................................................................................................... VIDEO PORT .................................................................................................................................. 8.1 VIDEO INTERFACE PORT FEATURES ............................................................................... 8.2 BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC .............................. 8.3 TIMING DIAGRAMS .............................................................................................................. 8.4 656 MASTER MODE ............................................................................................................. 8.5 VBI HANDLING IN THE VIDEO PORT ................................................................................. 8.6 SCALING IN THE VIDEO PORT ........................................................................................... BOOT ROM INTERFACE............................................................................................................... 4 5 6 6 6 8 8 9 9 9 9 10 11 11 11 12 12 12 13 13 13 13 14 14 15 16 16 22 22 23 29 31 31 32 32 37 38 40 40 41 42 46 47 47 48 3 4 5 6 7 8 9 2/77 128-BIT 3D MULTIMEDIA ACCELERATOR 10 11 RIVA 128 50 52 52 52 53 54 55 56 58 58 58 59 59 59 59 60 60 61 62 62 63 63 64 64 64 POWER-ON RESET CONFIGURATION........................................................................................ DISPLAY INTERFACE ................................................................................................................... 11.1 PALETTE-DAC ...................................................................................................................... 11.2 PIXEL MODES SUPPORTED ............................................................................................... 11.3 HARDWARE CURSOR ......................................................................................................... 11.4 I2C INTERFACE.................................................................................................................... 11.5 ANALOG INTERFACE .......................................................................................................... 11.6 TV OUTPUT SUPPORT ........................................................................................................ IN-CIRCUIT BOARD TESTING ...................................................................................................... 12.1 TEST MODES ....................................................................................................................... 12.2 CHECKSUM TEST ................................................................................................................ ELECTRICAL SPECIFICATIONS .................................................................................................. 13.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................ 13.2 OPERATING CONDITIONS .................................................................................................. 13.3 DC SPECIFICATIONS........................................................................................................... 13.4 ELECTRICAL SPECIFICATIONS.......................................................................................... 13.5 DAC CHARACTERISTICS .................................................................................................... 13.6 FREQUENCY SYNTHESIS CHARACTERISTICS................................................................ PACKAGE DIMENSION SPECIFICATION .................................................................................... 14.1 300 PIN BALL GRID ARRAY PACKAGE .............................................................................. REFERENCES................................................................................................................................ ORDERING INFORMATION .......................................................................................................... APPENDIX...................................................................................................................................... PCI CONFIGURATION REGISTERS ............................................................................................. A.1 REGISTER DESCRIPTIONS FOR PCI CONFIGURATION SPACE .................................... 12 13 14 15 16 A 3/77 RIVA 128 1 REVISION HISTORY Date 15 Jul 97 28 Aug 97 29 Aug 97 4 Sep 97 15 Sep 97 15 Sep 97 17 Sep 97 17 Sep 97 17 Sep 97 18 Sep 97 18 Sep 97 25 Sep 97 25 Sep 97 Section, page 6, page 28 13.5, page 59 6.3, page 31 10, page 49 13, page 58 13, page 58 1, page 5 2, page 6 8, page 39 11.6, page 55 13.3, page 58 4.2, page 16 11.4, page 53 128-BIT 3D MULTIMEDIA ACCELERATOR Description of change Update of SGRAM framebuffer interface configuration diagrams. Change of DAC specification from 206MHz to 230MHz max. operating frequency. Update to recommendation for connection of FBCLK2 and FBCLKB pins. Update to RAM Type Power-On Reset configuration bits. Temperature specification TC now based on case, not ambient temperature. Change to Power Supply voltage VDD specification. Change to Video Port pin names. Change to Video Port pin descriptions. Updates to Video Port section. Change to capacitor value in TV output implementation schematic. Change to power dissipation specification. Removal of AGP flow control description. Updates to Serial Port description. 4/77 1 NOTES 1 FBD[17] FBD[19] FBD[21] FBD[23] FBDQM[2] FBA[0] FBA[2] FBA[4] FBA[6] FBA[8] FBDQM[5] FBD[41] FBD[43] FBD[45] FBD[47] FBD[56] FBD[57] 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 RIVA 128 300PBGA DEVICE PINOUT 128-BIT 3D MULTIMEDIA ACCELERATOR 1 2 ∗ FBD[18] FBD[20] FBD[22] FBDQM[0] FBA[9] FBA[1] FBA[3] FBA[5] FBA[7] FBCLK1 FBDQM[7] FBD[40] FBD[42] FBD[44] FBD[46] FBD[58] FBD[59] FBD[27] FBDQM[4] FBD[55] FBD[54] FBD[53] FBD[26] FBD[25] FBD[15] FBD[13] FBD[11] FBD[9] FBDQM[1] FBWE# FBRAS# A FBD[4] FBD[6] FBD[7] B FBA[10]∗ FBD[60] FBD[3] FBD[5] FBD[16] C FBD[30] VDD FBD[24] FBD[14] FBD[12] FBD[10] FBD[8] FBDQM[3] FBCAS# FBCS0 FBCS1 FBDQM[6] VDD FBD[52] FBD[51] FBD[1] FBD[2] FBD[28] FBD[61] D VDD NIC VDD VDD VDD FBCLK0 FBD[0] FBD[29] FBD[62] FBD[63] E FBCKE∗ VDD VDD VDD VDD FBCLKFB VDD VDD FBD[48] SCL FBCLK2 FBD[31] FBD[50] FBD[39] FBD[38] F MP_AD[4] MPCLAMP VDD MP_AD[6] NIC SDA FBD[49] FBD[37] FBD[36] G MP_AD[3] VDD MPFRAME# MP_AD[7] MP_AD[5] FBD[35] FBD[34] FBD[33] FBD[32] H MP_AD[0] GND GND GND GND MP_AD[2] MPSTOP# MPCLK NIC FBDQM[12] FBDQM[14] FBDQM[15] FBDQM[13] J GND GND GND GND FBDQM[8] MPDTACK# MP_AD[1] FBD[118] FBD[119] FBD[105] FBD[104] K FBD[73] GND GND GND GND FBDQM[9] FBD[87] FBDQM[10] FBDQM[11] FBD[116] FBD[117] FBD[107] FBD[106] L FBD[75] GND GND GND GND FBD[86] FBD[85] FBD[72] FBD[114] FBD[115] FBD[109] FBD[108] M FBD[77] NIC FBD[84] FBD[83] FBD[74] FBD[112] FBD[113] FBD[111] FBD[110] N FBD[79] VDD FBD[82] FBD[81] FBD[76] NIC FBD[102] FBD[103] FBD[121] FBD[120] P FBD[89] NIC FBD[80] FBD[71] FBD[78] VDD FBD[100] FBD[101] FBD[123] FBD[122] R VDD NIC HOSTVDD HOSTVDD HOSTCLAMP FBD[70] FBD[69] FBD[88] NIC FBD[98] FBD[99] FBD[125] FBD[124] T FBD[91] HOSTCLAMP XTALOUT PCIRST# AGPST[1] PCIAD[30] FBD[68] FBD[67] FBD[90] HOSTVDD HOSTCLAMP HOSTVDD HOSTCLAMP VDD FBD[97] FBD[127] FBD[126] U DACVDD VREF PCIINTA# PCIGNT# FBD[66] FBD[65] FBD[92] PCIAD[26] PCICBE#[3] PCIAD[20] PCIAD[16] PCITRDY# PCIPAR HOSTVDD PCICBE#[0] FBD[96] VIDVSYNC VIDHSYNC V COMP PLLVDD PCIREQ# AGPST[2] FBD[64] FBD[95] RED AGPPIPE# PCIAD[28] PCIAD[24] PCIAD[22] PCIAD[18] PCIFRAME# PCISTOP# PCIAD[15] PCIAD[11] PCIAD[6] PCIAD[2] TESTMODE ROMCS# W XTALIN PCICLK AGPST[0] FBD[93] FBD[94] BLUE PCIAD[31] PCIAD[27] AGPADSTB1∗ PCIAD[21] PCIAD[17] PCIIRDY# PCICBE#[1] PCIAD[13] PCIAD[9] PCIAD[4] PCIAD[0] PCIAD[7] PCIAD[5] NIC = No Internal Connection. Do not connect to these pins. VDD=3.3V Signals denoted with an asterisk are defined for future expansion. See Pin Descriptions, Section 2, page 6 for details. PCIIDSEL/ AGPRBF# PCIAD[29] PCIAD[25] PCIAD[23] PCIAD[19] PCICBE#[2] PCIDEVSEL# PCIAD[14] PCIAD[12] PCIAD[10] PCIAD[8] RIVA 128 Y GREEN GND RSET AGPADSTB0∗ PCIAD[3] PCIAD[1] 5/77 RIVA 128 2 2.1 PIN DESCRIPTIONS 128-BIT 3D MULTIMEDIA ACCELERATOR ACCELERATED GRAPHICS PORT (AGP) INTERFACE I/O I Description AGP status bus providing information from the arbiter to the RIVA 128 on what it may do. AGPST[2:0] only have meaning to the RIVA 128 when PCIGNT# is asserted. When PCIGNT# is de-asserted these signals have no meaning and must be ignored. 000 001 010 011 100 101 110 111 Indicates that previously requested low priority read or flush data is being returned to the RIVA 128. Indicates that previously requested high priority read data is being returned to the RIVA 128. Indicates that the RIVA 128 is to provide low priority write data for a previous enqueued write command. Indicates that the RIVA 128 is to provide high priority write data for a previous enqueued write command. Reserved Reserved Reserved Indicates that the RIVA 128 has been given permission to start a bus transaction. The RIVA 128 may enqueue AGP requests by asserting AGPPIPE# or start a PCI transaction by asserting PCIFRAME#. AGPST[2:0] are always an output from the Core Logic (AGP chipset) and an input to the RIVA 128. Signal AGPST[2:0] AGPRBF# O Read Buffer Full indicates when the RIVA 128 is ready to accept previously requested low priority read data or not. When AGPRBF# is asserted the arbiter is not allowed to return (low priority) read data to the RIVA 128. This signal should be pulled up via a 4.7KΩ resistor (although it is supposed to be pulled up by the motherboard chipset). Pipelined Read is asserted by RIVA 128 (when the current master) to indicate a full width read address is to be enqueued by the target. The RIVA 128 enqueues one request each rising clock edge while AGPPIPE# is asserted. When AGPPIPE# is de-asserted no new requests are enqueued across PCIAD[31:0]. AGPPIPE# is a sustained tri-state signal from the RIVA 128 and is an input to the target (the core logic). These signals are currently a “no-connect” in this revision of the RIVA 128 but may be activated to support AGP double-edge clocking in future pin compatible devices. It is recommended that these pins are connected directly to the AD_STB0 and AD_STB1 pins defined in the AGP specification. AGPPIPE# O AGPADSTB0∗, AGPADSTB1∗ I/O 2.2 PCI 2.1 LOCAL BUS INTERFACE I/O I Description PCI clock. This signal provides timing for all transactions on the PCI bus, except for PCIRST# and PCIINTA#. All PCI signals are sampled on the rising edge of PCICLK and all timing parameters are defined with respect to this edge. PCI reset. This signal is used to bring registers, sequencers and signals to a consistent state. When PCIRST# is asserted all output signals are tristated. 32-bit multiplexed address and data bus. A bus transaction consists of an address phase followed by one or more data phases. Signal PCICLK PCIRST# PCIAD[31:0] I I/O 6/77 128-BIT 3D MULTIMEDIA ACCELERATOR RIVA 128 Signal PCICBE[3:0]# I/O I/O Description Multiplexed bus command and byte enable signals. During the address phase of a transaction PCICBE[3:0]# define the bus command, during the data phase PCICBE[3:0]# are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain valid data. PCICBE[0]# applies to byte 0 (LSB) and PCICBE[3]# applies to byte 3 (MSB). When connected to AGP these signals carry different commands than PCI when requests are being enqueued using AGPPIPE#. Valid byte information is provided during AGP write transactions. PCICBE[3:0]# are not used during the return of AGP read data. Parity. This signal is the even parity bit generated across PCIAD[31:0] and PCICBE[3:0]#. PCIPAR is stable and valid one clock after the address phase. For data phases PCIPAR is stable and valid one clock after either PCIIRDY# is asserted on a write transaction or PCITRDY# is asserted on a read transaction. Once PCIPAR is valid, it remains valid until one clock after completion of the current data phase. The master drives PCIPAR for address and write data phases; the target drives PCIPAR for read data phases. Cycle frame. This signal is driven by the current master to indicate the beginning of an access and its duration. PCIFRAME# is asserted to indicate that a bus transaction is beginning. Data transfers continue while PCIFRAME# is asserted. When PCIFRAME# is deasserted, the transaction is in the final data phase. Initiator ready. This signal indicates the initiator’s (bus master’s) ability to complete the current data phase of the transaction. See extended description for PCITRDY#. When connected to AGP this signal indicates the initiator (AGP compliant master) is ready to provide all write data for the current transaction. Once PCIIRDY# is asserted for a write operation, the master is not allowed to insert wait states. The assertion of PCIIRDY# for reads, indicates that the master is ready to transfer a subsequent block of read data. The master is never allowed to insert a wait state during the initial block of a read transaction. However, it may insert wait states after each block transfers. PCIPAR I/O PCIFRAME# I/O PCIIRDY# I/O PCITRDY# I/O Target ready. This signal indicates the target’s (selected device’s) ability to complete the current data phase of the transaction. PCITRDY# is used in conjunction with PCIIRDY#. A data phase is completed on any clock when both PCITRDY# and PCIIRDY# are sampled as being asserted. During a read, PCITRDY# indicates that valid data is present on PCIAD[31:0]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both PCIIRDY# and PCITRDY# are asserted together. When connected to AGP this signal indicates the AGP compliant target is ready to provide read data for the entire transaction (when transaction can complete within four clocks) or is ready to transfer a (initial or subsequent) block of data, when the transfer requires more than four clocks to complete. The target is allowed to insert wait states after each block transfers on both read and write transactions. PCISTOP# PCIIDSEL I/O I PCISTOP# indicates that the current target is requesting the master to terminate the current transaction. Initialization device select. This signal is used as a chip select during configuration read and write transactions. For AGP applications note that IDSEL is not a pin on the AGP connector. The RIVA 128 performs the device select decode internally within its host interface. It is not required to connect the AD16 signal to the IDSEL pin as suggested in the AGP specification. PCIDEVSEL# I/O Device select. When acting as an output PCIDEVSEL# indicates that the RIVA 128 has decoded the PCI address and is claiming the current access as the target. As an input PCIDEVSEL# indicates whether any other device on the bus has been selected. Request. This signal is asserted by the RIVA 128 to indicate to the arbiter that it desires to become master of the bus. PCIREQ# O 7/77 RIVA 128 128-BIT 3D MULTIMEDIA ACCELERATOR Signal PCIGNT# I/O I Description Grant. This signal indicates to the RIVA 128 that access to the bus has been granted and it can now become bus master. When connected to AGP additional information is provided on AGPST[2:0] indicating that the master is the recipient of previously requested read data (high or low priority), it is to provide write data (high or low priority), for a previously enqueued write command or has been given permission to start a bus transaction (AGP or PCI). Interrupt request line. This open drain output is asserted and deasserted asynchronously to PCICLK. PCIINTA# O 2.3 SGRAM FRAMEBUFFER INTERFACE I/O I/O Description The 128-bit SGRAM memory data bus. FBD[31:0] are also used to access up to 64KBytes of 8-bit ROM or Flash ROM, using FBD[15:0] as address ROMA[15:0], FBD[31:24] as ROMD[7:0], FBD[17] as ROMWE# and FBD[16] as ROMOE#. Memory Address bus. Configuration strapping options are also decoded on these signals during PCIRST# as described in Section 10, page 49. [FBA[10] is reserved for future expansion and should be pulled to GND via a 4.7KΩ resistor. Memory Row Address Strobe for all memory devices. Memory Column Address Strobe for all memory devices. Memory Chip Select strobes for each SGRAM bank. Memory Write Enable strobe for all memory devices. Memory Data/Output Enable strobes for each of the 16 bytes. Memory Clock signals. Separate clock signals FBCLK0 and FBCLK1 are provided for each bank of SGRAM for reduced clock skew and loading. FBCLK2 is fed back to FBCLKFB. Details of recommended memory clock layout are given in Section 6.3, page 31. Framebuffer clock feedback. FBCLK2 is fed back to FBCLKFB. This signal is currently a “no-connect” in this revision of the RIVA 128 but may be activated to support the framebuffer memory clock enable for power management in future pin compatible devices. It is recommended that this pin is tied to VDD through a 4.7KΩ pull-up resistor. Signal FBD[127:0] FBA[10:0] O FBRAS# FBCAS# FBCS[1:0]# FBWE# FBDQM[15:0] FBCLK0, FBCLK1, FBCLK2 FBCLKFB FBCKE∗ O O O O O O I O 2.4 VIDEO PORT I/O I/O I I O I Description Media Port 8-bit multiplexed address and data bus or ITU-R-656 video data bus when in 656 mode. 40MHz Media Port system clock or pixel clock when in 656 mode. Media Port data transfer acknowledgment signal. Initiates Media Port transfers when active, terminates transfers when inactive. Media Port control signal used by the slave to terminate transfers. Signal MP_AD[7:0] MPCLK MPDTACK# MPFRAME# MPSTOP# 8/77 128-BIT 3D MULTIMEDIA ACCELERATOR 2.5 DEVICE ENABLE SIGNALS I/O O Description RIVA 128 Signal ROMCS# Enables reads from an external 64Kx 8 or 32Kx8 ROM or Flash ROM. This signal is used in conjunction with framebuffer data lines as described above in Section 2.3. 2.6 DISPLAY INTERFACE I/O I/O I/O O O Description Used for DDC2B+ monitor communication and interface to video decoder devices. Used for DDC2B+ monitor communication and interface to video decoder devices. Vertical sync supplied to the display monitor. No buffering is required. In TV mode this signal supplies composite sync to an external PAL/NTSC encoder. Horizontal sync supplied to the display monitor. No buffering is required. Signal SDA SCL VIDVSYNC VIDHSYNC 2.7 VIDEO DAC AND PLL ANALOG SIGNALS I/O O Description RGB display monitor outputs. These are software configurable to drive either a doubly terminated or singly terminated 75Ω load. External compensation capacitor for the video DACs. This pin should be connected to DACVDD via the compensation capacitor, see Figure 58, page 54. A precision resistor placed between this pin and GND sets the full-scale video DAC current, see Figure 58, page 54. A capacitor should be placed between this pin and GND as shown in Figure 58, page 54. A series resonant crystal is connected between these two points to provide the reference clock for the internal MCLK and VCLK clock synthesizers, see Figure 58 and Table 16, page 54. Alternately, an external LVTTL clock oscillator output may be driven into XTALOUT, connecting XTALIN to GND. For designs supporting TV-out, XTALOUT should be driven by a reference clock as described in Section 11.6, page 55. Signal RED, GREEN, BLUE COMP RSET VREF XTALIN XTALOUT I O 2.8 POWER SUPPLY I/O P P P P P P Description Analog power supply for the video DACs. Analog power supply for all clock synthesizers. Digital power supply. Ground. MPCLAMP is connected to +5V to protect the 3.3V RIVA 128 from external devices which will potentially drive 5V signal levels onto the Video Port input pins. HOSTVDD is connected to the Vddq 3.3 pins on the AGP connector. This is the supply voltage for the I/O buffers and is isolated from the core VDD. On AGP designs these pins are also connected to the HOSTCLAMP pins. On PCI designs they are connected to the 3.3V supply. HOSTCLAMP is the supply signalling rail protection for the host interface. In AGP designs these signals are connected to Vddq 3.3. For PCI designs they are connected to the I/O power pins (V(I/O)). Signal DACVDD PLLVDD VDD GND MPCLAMP HOSTVDD HOSTCLAMP P 9/77 RIVA 128 2.9 TEST I/O I Description 128-BIT 3D MULTIMEDIA ACCELERATOR Signal TESTMODE For designs which will be tested in-circuit, this pin should be connected to GND through a 10KΩ pull-down resistor, otherwise this pin should be connected directly to GND. When TESTMODE is asserted, MP_AD[3:0] are reassigned as TESTCTL[3:0] respectively. Information on in-circuit test is given in Section 12, page 57. 10/77 128-BIT 3D MULTIMEDIA ACCELERATOR 3 OVERVIEW OF THE RIVA 128 RIVA 128 cesses offer other performance enhancements since they are from non-cacheable memory (no snoop) and can be low priority to prevent processor stalls, or high priority to prevent graphics engine stalls. Building a balanced system RIVA 128 is architected to provide the level of 3D graphics performance and quality available in top arcade platforms. To provide comparable scene complexity in the 1997 time-frame, processors will have to achieve new levels of floating point performance. Profiles have shown that 1997 mainstream CPUs will be able to transform over 1 million lit, meshed triangles/s at 50% utilization using Direct3D. This represents an order of magnitude performance increase over anything attainable in 1996 PC games. To build a balanced system the graphics pipeline must match the CPU’s performance. It must be capable of rendering at least 1 million polygons/s in order to avoid CPU stalls. Factors affecting this system balance include: • Direct3D compatibility. Minimizing the differences between the hardware interface and the Direct3D data structures. • Triangle setup. Minimizing the number of format conversions and delta calculations done by the CPU. • Display-list processing. Avoiding CPU stalls by allowing the graphics pipeline to execute independently of the CPU. • Vertex caching. Avoids saturating the host interface with repeated vertices, lowering the traffic on the bus and reducing system memory collisions. • Host interface performance. 3.2 HOST INTERFACE The RIVA 128 is the first 128-bit 3D Multimedia Accelerator to offer unparalleled 2D and 3D performance, meeting all the requirements of the mainstream PC graphics market and Microsoft’s PC’97. The RIVA 128 introduces the most advanced Direct3D™ acceleration solution and also delivers leadership VGA, 2D and Video performance, enabling a range of applications from 3D games through to DVD, Intercast™ and video conferencing. 3.1 BALANCED PC SYSTEM The RIVA 128 is designed to leverage existing PC system resources such as system memory, high bandwidth internal buses and bus master capabilities. The synergy between the RIVA 128 graphics pipeline architecture and that of the current generation PCI and next generation AGP platforms, defines ground breaking performance levels at the cost point currently required for mainstream PC graphics solutions. Execute versus DMA models The RIVA 128 is architected to optimize PC system resources in a manner consistent with the AGP “Execute” model. In this model texture map data for 3D applications is stored in system memory and individual texels are accessed as needed by the graphics pipeline. This is a significant enhancement over the DMA model where entire texture maps are transferred into off-screen framebuffer memory. The advantages of the Execute versus the DMA model are: • Improved system performance since only the required texels and not the entire texture map, cross the bus. • Substantial cost savings since all the framebuff- er is usable for the displayed screen and Z buffer and no part of it is required to be dedicated to texture storage or texture caching. • There is no software overhead in the Direct3D driver to manage texture caching between application memory and the framebuffer. To extend the advantages of the Execute model, the RIVA 128’s proprietary texture cache and virtual DMA bus master design overcomes the bandwidth limitation of PCI, by sustaining a high texel throughput with minimum bus utilization. The host interface supports burst transactions up to 66MHz and provides over 200MBytes/s on AGP. AGP ac- The host interface boosts communication between the host CPU and the RIVA 128. The optimized interface performs burst DMA bus mastering for efficient and fast data transfer. • 32-bit PCI version 2.1 or AGP version 1.0 • Burst DMA Master and target • 33MHz PCI clock rate or 66MHz AGP clock rate • Supports over 100MBytes/s with 33MHz PCI and over 200MBytes/s on 66MHz AGP • Implements read buffer posting on AGP • Fully supports the “Execute” model on both PCI and AGP 11/77 RIVA 128 3.3 2D ACCELERATION 128-BIT 3D MULTIMEDIA ACCELERATOR • Rendering pipeline optimized for Microsoft’s • • • • • • The RIVA 128's 2D rendering engine delivers industry-leading Windows acceleration performance: • 100MHz 128-bit graphics engine optimized for single cycle operation into the 128-bit SGRAM interface supporting up to 1.6GBytes/s • Acceleration functions optimized for minimal software overhead on key GDI calls support for DirectDraw in • Extensive Windows95 including optimized Direct Framebuffer (DFB) access with Write-combining • Accelerated primitives including BLT, transpar- ent BLT, stretchBLT, points, lins, lines, polylines, polygons, fills, patterns, arbitrary rectangular clipping and improved text rendering • Pipeline optimized for multiple color depths in- • • • • • • • • cluding 8, 15, 24, and 30 bits per pixel • DMA Pusher allows the 2D graphics pipeline to load rendering methods optimizing RIVA 128/ host multi-tasking • Execution of all 256 Raster Operations (as de- fined by Microsoft Windows) at 8, 15, 24 and 30-bit color depths • 15-bit hardware color cursor • Hardware color dithering • Multi buffering (Double, Triple, Quad buffering) for smooth animation 3.4 3D ENGINE Direct3D API Perspective correct true-color Gouraud lighting and texture mapping Full 32-bit RGBA texture filter and Gouraud lighting pixel data path Alpha blending for translucency and transparency Sub-pixel accurate texture mapping Internal pixel path: up to 24bits, alpha: up to 8 bits Texture magnification filtering with high quality bilinear filtering without performance degradation Texture minification filtering with MIP mapping without performance degradation LOD MIP-mapping: filter shape is dynamically adjusted based on surface orientation Texture sizes from 4 to 2048 texels in either U or V Textures can be looped and paged in real time for texture animation Perspective correct per-pixel fog for atmospheric effects Perspective correct specular highlights Multi buffering (Double, Triple, Quad buffering) for smooth 3D animation Multipass rendering for environmental mapping and advanced texturing VIDEO PROCESSOR 3.5 Triangle setup engine • Setup hardware optimized for Microsoft’s Direct3D API • 5Gflop floating point geometry processor • Slope and setup calculations • Accepts IEEE Single Precision format used in Direct3D • Efficient vertex caching Rendering engine The RIVA 128 Multimedia Accelerator integrates an orthodox 3D rendering pipeline and triangle setup function which not only fully utilizes the capabilities of the Accelerated Graphics Port, but also supports advanced texture mapped 3D over the PCI bus. The RIVA 128 3D pipeline offers to Direct3D or similar APIs advanced triangle rendering capabilities: 12/77 The RIVA 128 Palette-DAC pipeline accelerates full-motion video playback, sustaining 30 frames per second while retaining the highest quality color resolution, implementing true bilinear filtering for scaled video, and compensating for filtering losses using edge enhancement algorithms. • Advanced support for DirectDraw (DirectVideo) in Windows 95 • Back-end hardware video scaling for video conferencing and playback • Hardware color space conversion (YUV 4:2:2 and 4:2:0) • Multi-tap X and Y filtering for superior image quality • Optional edge enhancement to retain video sharpness • Support for scaled field interframing for reduced motion artifacts and reduced storage 128-BIT 3D MULTIMEDIA ACCELERATOR • Per-pixel color keying • Multiple video windows with hardware color RIVA 128 3.7 DIRECT RGB OUTPUT TO LOW COST PAL/NTSC ENCODER space conversion and filtering • Planar YUV12 (4:2:0) to/from packed (4:2:2) conversion for software MPEG acceleration and H.261 video conferencing applications • Accelerated playback of industry standard co- The RIVA 128 has also been designed to interface to a standard PAL or NTSC television via a low cost TV encoder chip. In PAL or NTSC display modes the interlaced output is internally flicker-filtered and CCIR/EIA compliant timing reference signals are generated. 3.8 SUPPORT FOR STANDARDS decs including MPEG-1/2, Indeo, Cinepak 3.6 VIDEO PORT • Multimedia support for MS-DOS, Windows The RIVA 128 Multimedia Accelerator provides connectivity for video input devices such as Philips SAA7111A, ITT 3225 and Samsung KS0127 through an ITU-R-656 video input bus to DVD and MPEG2 decoders through bidirectional media port functionality. • Supported 3.11, Windows 95, and Windows NT • Acceleration for Windows 95 Direct APIs in- cluding Direct3D, DirectDraw and DirectVideo • VGA and SVGA: The RIVA 128 has an industry through VPE extensions to DirectDraw • Supports filtered down-scaling and decimation • Supports real time video capture via Bus Mas- standard 32-bit VGA core and BIOS support. In PCI configuration space the VGA can be enabled and disabled independently of the GUI. • Glue-less Accelerated Graphics Port (AGP 1.0) or PCI 2.1 bus interface • ITU/CCIR-656 compatible video port • VESA DDC2B+, DPMS, VBE 2.0 supported tering DMA • Serial interface for decoder control 3.9 RESOLUTIONS SUPPORTED Resolution BPP 4 8 16 32 4 8 16 32 4 8 16 32 4 8 16 32 4 8 16 32 4 8 16 32 2MByte 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 100Hz 100Hz 75Hz 75Hz 4MByte (128-bit) 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 100Hz 100Hz 100Hz 100Hz 75Hz 75Hz 75Hz - 640x480 800x600 1024x768 1152x864 1280x1024 1600x1200 13/77 RIVA 128 3.10 CUSTOMER EVALUATION KIT A Customer Evaluation Kit (CEK) is available for evaluating the RIVA 128. The CEK includes a PCI or AGP adapter card designed to support the RIVA 128 feature set, an evaluation CD-ROM containing a fast-installation application, extensive device drivers and programs demonstrating the RIVA 128 features and performance. This CEK includes: • RIVA 128 evaluation board and CD-ROM • QuickStart install/user guide • OS drivers and files - Windows 3.11 - Windows 95 Direct X/3D - Windows NT 3.5 - Windows NT 4.0 • Demonstration files and Game demos • Benchmark programs and files 3.11 TURNKEY MANUFACTURING PACKAGE A Turnkey Manufacturing Package (TMP) is available to support OEM designs and development through to production. It delivers a complete manufacturable hardware and software solution that 128-BIT 3D MULTIMEDIA ACCELERATOR allows an OEM to rapidly design and bring to volume an RIVA 128-based product. This TMP includes: • CD-ROM - RIVA 128 Datasheet and Application Notes - OrCAD™ schematic capture and PADS™ layout design information - Quick Start install/user guide/release notes - BIOS Modification program, BIOS binaries and utilities - Bring-up and OEM Production Diagnostics - Software and Utilities • OS drivers and files - Windows 3.11 Windows 95 Direct X/3D Windows NT 3.5 Windows NT 4.0 • FCC/CE Certification Package • Content developer and WWW information • Partner solutions • Access to our password-protected web site for upgrade files and release notes. 14/77 128-BIT 3D MULTIMEDIA ACCELERATOR 4 ACCELERATED GRAPHICS PORT (AGP) INTERFACE RIVA 128 The Accelerated Graphics Port (AGP) is a high performance, component level interconnect targeted at 3D graphical display applications and based on performance enhancements to the PCI local bus. Figure 1. System block diagram showing relationship between AGP and PCI buses CPU RIVA 128 AGP AGP chipset System memory PCI I/O I/O I/O Background to AGP Although 3D graphics acceleration is becoming a standard feature of multimedia PC platforms, 3D rendering generally has a voracious appetite for memory bandwidth. Consequently there is upward pressure on the PC’s memory requirement leading to higher bill of material costs. These trends will increase, requiring high speed access to larger amounts of memory. The primary motivation for AGP therefore was to contain these costs whilst enabling performance improvements. By providing significant bandwidth improvement between the graphics accelerator and system memory, some of the 3D rendering data structures can be shifted into main memory, thus relieving the pressure to increase the cost of the local graphics memory. Texture data are the first structures targeted for shifting to system memory for four reasons: 1 Textures are generally read only, and therefore do not have special access ordering or coherency problems. 2 Shifting textures balances the bandwidth load between system memory and local graphics memory, since a well cached host processor has much lower memory bandwidth requirements than a 3D rendering engine. Texture access comprises perhaps the largest single component of rendering memory bandwidth (compared with rendering, display and Z buffers), so avoiding loading or caching textures in graphics local memory saves not only this component of local memory bandwidth, but also the bandwidth necessary to load the texture store in the first place. Furthermore, this data must pass through main memory anyway as it is loaded from a mass store device. 3 Texture size is dependent upon application quality rather than on display resolution, and therefore subject to the greatest pressure for growth. 4 Texture data is not persistent; it resides in memory only for the duration of the application, so any system memory spent on texture storage can be returned to the free memory heap when the application finishes (unlike display buffers which remain in use). Other data structures can be moved to main memory but the biggest gain results from moving texture data. Relationship of AGP to PCI AGP is a superset of the 66MHz PCI Specification (Revision 2.1) with performance enhancements optimized for high performance 3D graphics applications. The PCI Specification is unmodified by AGP and ‘reserved’ PCI fields, encodings and pins, etc. are not used. AGP does not replace the need for the PCI bus in the system and the two are physically, logically, and electrically independent. As shown in Figure 1 15/77 RIVA 128 the AGP bridge chip and RIVA 128 are the only devices on the AGP bus - all other I/O devices remain on the PCI bus. The add-in slot defined for AGP uses a new connector body (for electrical signaling reasons) which is not compatible with the PCI connector; PCI and AGP boards are not mechanically interchangeable. AGP accesses differ from PCI in that they are pipelined. This compares with serialized PCI 4.1 RIVA 128 AGP INTERFACE 128-BIT 3D MULTIMEDIA ACCELERATOR transactions, where the address, wait and data phases need to complete before the next transaction starts. AGP transactions can only access system memory - not other PCI devices or CPU. Bus mastering accesses can be either PCI or AGPstyle. Full details of AGP are given in the Accelerated Graphics Port Interface Specification [3] published by Intel Corporation. The RIVA 128 glueless interface to AGP 1.0 is shown in Figure 2. Figure 2. AGP interface pin connections PCIAD[31:0] 32 PCICBE[3:0]# 4 AGPST[2:0]# 3 AGPRBF# AGPPIPE# PCIDEVSEL# AGP bus PCIIRDY# PCITRDY# PCISTOP# PCIIDSEL PCIPAR PCIREQ# PCIGNT# PCICLK PCIRST# PCIINTA# RIVA 128 4.2 AGP BUS TRANSACTIONS PCI transactions on the AGP bus PCI transactions can be interleaved with AGP transactions including between pipelined AGP data transfers. A basic PCI transaction on the AGP interface is shown in Figure 3. If the PCI target is a non AGP compliant master, it will not see AGPST[2:0] and the transaction appears to be on a PCI bus. For AGP aware bus masters, AGPST[2:0] indicate that permission to use the interface has been granted to initiate a request and not to move AGP data. AGP bus commands supported The following AGP bus commands are supported by the RIVA 128: - Read - Read (hi-priority) 16/77 128-BIT 3D MULTIMEDIA ACCELERATOR Figure 3. Basic PCI transaction on AGP 1 PCICLK PCIFRAME# PCIAD[31:0] PCICBE[3:0]# PCIIRDY# PCITRDY# PCIDEVSEL# PCIREQ# PCIGNT# AGPST[2:0] RIVA 128 2 3 4 5 6 address bus cmd data_pci BE[3:0]# xxx 111 111 xxx xxx xxx An example of a PCI transaction occurring between an AGP command cycle and return of data is shown in Figure 4. This shows the smallest number of cycles during which an AGP request can be enqueued, a PCI transaction performed and AGP read data returned. Figure 4. PCI transaction occurring between AGP request and data 1 PCICLK AGPPIPE# PCIFRAME# PCIAD[31:0] PCICBE# PCIIRDY# PCITRDY# PCIDEVSEL# PCIAGPRBF# PCIREQ# PCIGNT# AGPST[2:0] 111 111 xxx 111 111 xxx xxx 00x xxx xxx A9 C9 address pci_cmd data BE D7 0000 +1 000 2 3 4 5 6 7 8 9 10 17/77 RIVA 128 Figure 5. Basic AGP pipeline concept 128-BIT 3D MULTIMEDIA ACCELERATOR Bus Idle Pipelined data transfer Data-1 Data-2 Data-3 Intervene cycles A1 A2 A3 A Data Pipelined AGP requests PCI transaction Pipeline operation Memory access pipelining provides the main performance enhancement of AGP over PCI. AGP pipelined bus transactions share most of the PCI signal set, and are interleaved with PCI transactions on the bus. The RIVA 128 supports AGP pipelined reads with a 4-deep queue of outstanding read requests. Pipelined reads are primarily used by the RIVA 128 for cache filling, the cache size being optimized for AGP bursts. Depending on the AGP bridge, a bandwidth of up to 248MByte/s is achievable for 128-byte pipelined reads. This compares with around 100MByte/s for 128-byte 33MHz PCI reads. Another feature of AGP is that for smaller sized reads the bandwidth is not significantly reduced. Whereas 16-byte reads on PCI transfer at around 33MByte/s, on AGP around 175MByte/s is achievable. The RIVA 128 actually requests reads greater than 64 bytes in multiples of 32-byte transactions. The pipe depth can be maintained by the AGP bus master (RIVA 128) intervening in a pipelined transfer to insert new requests between data replies. This bus sequencing is illustrated in Figure 5. When the bus is in an idle condition, the pipe can be started by inserting one or more AGP access requests consecutively. Once the data reply to those accesses starts, that stream can be broken (or intervened) by the bus master (RIVA 128) inserting one or more additional AGP access requests or inserting a PCI transaction. This intervention is accomplished with the bus ownership signals, PCIREQ# and PCIGNT#. 18/77 The RIVA 128 implements both high and low priority reads depending of the status of the rendering engine. If the pipeline is likely to stall due to system memory read latency, a high priority read request is posted. Address Transactions The RIVA 128 requests permission from the bridge to use PCIAD[31:0] to initiate either an AGP request or a PCI transaction by asserting PCIREQ#. The arbiter grants permission by asserting PCIGNT# with AGPST[2:0] equal to ‘111’ (referred to as START). When the RIVA 128 receives START it must start the bus operation within two clocks of the bus becoming available. For example, when the bus is in an idle condition when START is received, the RIVA 128 must initiate the bus transaction on the next clock and the one following. Figure 6 shows a single address being enqueued by the RIVA 128. Sometime before clock 1, the RIVA 128 asserts PCIREQ# to gain permission to use PCIAD[31:0]. The arbiter grants permission by indicating START on clock 2. A new request (address, command and length) are enqueued on each clock in which AGPPIPE# is asserted. The address of the request to be enqueued is presented on PCIAD[31:3], the length on PCIAD[2:0] and the command on PCICBE[3:0]#. In Figure 6 only a single address is enqueued since AGPPIPE# is just asserted for a single clock. The RIVA 128 indicates that the current address is the last it intends to enqueue when AGPPIPE# is asserted and PCIREQ# is deasserted (occurring on clock 3). Once the arbiter detects the assertion of AGPPIPE# or PCIFRAME# it deasserts PCIGNT# on clock 4. 128-BIT 3D MULTIMEDIA ACCELERATOR Figure 6. Single address - no delay by master 1 PCICLK AGPPIPE# PCIAD[31:0] PCICBE[3:0]# PCIREQ# PCIGNT# AGPST[2:0] xxx 111 111 xxx xxx xxx xxx A1 C1 RIVA 128 2 3 4 5 6 7 8 xxx Figure 7 shows the RIVA 128 enqueuing 4 requests, where the first request is delayed by the maximum 2 cycles allowed. START is indicated on clock 2, but the RIVA 128 does not assert AGPPIPE# until clock 4. Note that PCIREQ# remains asserted on clock 6 to indicate that the current request is not the last one. When PCIREQ# is deasserted on clock 7 with AGPPIPE# still asserted this indicates that the current address is the last one to be enqueued during this transaction. AGPPIPE# must be deasserted on the next clock when PCIREQ# is sampled as deasserted. If the RIVA 128 wants to enqueue more requests during this bus operation, it continues asserting AGPPIPE# until all of its requests are enqueued or until it has filled all the available request slots provided by the target. Figure 7. Multiple addresses enqueued, maximum delay by RIVA 128 1 PCICLK AGPPIPE# PCIAD[31:0] PCICBE# PCIREQ# PCIGNT# AGPST[2:0] xxx 111 111 111 xxx xxx xxx xxx A1 C1 A2 C2 A3 C3 A4 C4 2 3 4 5 6 7 19/77 RIVA 128 AGP timing specification Figure 8. AGP clock specification 128-BIT 3D MULTIMEDIA ACCELERATOR 0.6VDD 0.5VDD tCYC tHIGH tLOW 2V p-to-p (minimum) PCICLK 0.4VDD 0.3VDD 0.2VDD Table 1. Symbol tCYC tHIGH tLOW AGP clock timing parameters Parameter PCICLK period PCICLK high time PCICLK low time PCICLK slew rate Min. 15 6 6 1.5 4 Max. 30 Unit ns ns ns V/ns 1 Notes NOTES 1 This rise and fall time is measured across the minimum peak-to-peak range as shown in Figure 8. Figure 9. AGP timing diagram tVAL AGPCLK Output delay tOFF tON Tri-state output data1 tVAL data2 Input tH tSU data1 data2 Table 2. AGP timing parameters Symbol tVAL tON tOFF tSU tH Parameter AGPCLK to signal valid delay (data and control signals) Float to active delay Active to float delay Input set up time to AGPCLK (data and control signals) Input hold time from AGPCLK 7 0 Min. 2 2 28 Max. 11 Unit ns ns ns ns ns Notes 20/77 128-BIT 3D MULTIMEDIA ACCELERATOR 5 5.1 PCI 2.1 LOCAL BUS INTERFACE RIVA 128 PCI INTERFACE RIVA 128 The RIVA 128 supports a glueless interface to PCI 2.1 with both master and slave capabilities. The host interface is fully compliant with the 32-bit PCI 2.1 specification. The Multimedia Accelerator supports PCI bus operation up to 33MHz with zero-wait state capability and full bus mastering capability handling burst reads and burst writes. Figure 10. PCI interface pin connections PCIAD[31:0] 32 PCICBE[3:0]# 4 PCIFRAME# PCIDEVSEL# PCIIRDY# PCI bus PCITRDY# PCISTOP# PCIIDSEL PCIPAR PCIREQ# PCIGNT# PCICLK PCIRST# PCIINTA# RIVA 128 Table 3. PCI bus commands supported by the RIVA 128 Bus master Memory read and write Memory read line Memory read multiple Bus slave Memory read and write I/O read and write Configuration read and write Memory read line Memory read multiple Memory write invalidate 21/77 RIVA 128 5.2 PCI TIMING SPECIFICATION 128-BIT 3D MULTIMEDIA ACCELERATOR The timing specification of the PCI interface takes the form of generic setup, hold and delay times of transitions to and from the rising edge of PCICLK as shown in Figure 11. Figure 11. PCI timing parameters PCICLK tVAL Output timing parameters Output delay tON tOFF Tri-state output PCICLK Input timing parameters tSU Input tH Table 4. Symbol tVAL tVAL(PTP) tON tOFF tSU tSU (PTP) tSU (PTP) tH NOTE 1 PCI timing parameters Parameter PCICLK to signal valid delay (bussed signals) PCICLK to signal valid delay (point to point) Float to active delay Active to float delay Input set up time to PCICLK (bussed signals) Input set up time to PCICLK (PCIGNT#) Input set up time to PCICLK (PCIREQ#) Input hold time from PCICLK 7 10 12 0 Min. 2 2 2 28 Max. 11 12 Unit ns ns ns ns ns ns ns ns 1 1 Notes 1 1 PCIREQ# a nd PCIGNT# are point to point signals and have different valid delay and input setup times than bussed signals. All other signals are bussed. 22/77 128-BIT 3D MULTIMEDIA ACCELERATOR Figure 12. PCI Target write - Slave Write (single 32-bit with 1-cycle DEVSEL# response) RIVA 128 PCICLK PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# (med) address bus cmd data BE[3:0]# Figure 13. PCI Target write - Slave Write (multiple 32-bit with zero wait state DEVSEL# response) PCICLK PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd data0 BE[3:0]# data1 BE[3:0]# data2 BE[3:0]# 23/77 RIVA 128 Figure 14. 128-BIT 3D MULTIMEDIA ACCELERATOR PCI Target read - Slave Read (1-cycle single word read) PCICLK PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd BE[3:0]# data0 Figure 15. PCI Target read - Slave Read (slow single word read) PCICLK PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd BE[3:0]# data0 24/77 128-BIT 3D MULTIMEDIA ACCELERATOR Figure 16. PCI Master write - multiple word RIVA 128 PCICLK PCIREQ# PCIGNT# PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd data0 BE[3:0]# data1 BE[3:0]# data2 BE[3:0]# data3 BE[3:0]# Figure 17. PCI Master read - multiple word PCICLK PCIREQ# PCIGNT# PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd BE[3:0]# data0 BE[3:0]# data1 Note: The RIVA 128 does not generate fast back to back cycles as a bus master 25/77 RIVA 128 Figure 18. 128-BIT 3D MULTIMEDIA ACCELERATOR PCI Target configuration cycle - Slave Configuration Write PCICLK AD[31:0] PCICBE[3:0]# PCIFRAME# PCIIDSEL PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd data0 BE[3:0]# (med) Figure 19. PCI Target configuration cycle - Slave Configuration Read PCICLK PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIDSEL PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd BE[3:0]# config_data (med) 26/77 128-BIT 3D MULTIMEDIA ACCELERATOR Figure 20. PCI basic arbitration cycle RIVA 128 PCICLK PCIREQ#_a PCIREQ#_b PCIGNT#_a PCIGNT#_b PCIFRAME# PCIAD[31:0] address access A data address data access B Figure 21. Target initiated termination PCICLK 1 2 3 4 1 2 3 4 PCIFRAME# PCIIRDY# PCITRDY# PCISTOP# PCIDEVSEL# Disconnect - A Disconnect - B PCICLK PCIFRAME# PCIIRDY# PCITRDY# PCIPCISTOP# PCIDEVSEL# 1 2 3 4 5 1 2 3 4 Disconnect - C / Retry Target - Abort 27/77 RIVA 128 6 SGRAM FRAMEBUFFER INTERFACE 128-BIT 3D MULTIMEDIA ACCELERATOR The RIVA 128 SGRAM interface can be configured with a 2MByte 64-bit or 4MByte 128-bit data bus. With a 128-bit bus, 4MBytes of SGRAM is supported as shown in Figure 22. All of the SGRAM signalling environment is 3.3V. Figure 22. 64-bit 2MByte and 128-bit 4MByte SGRAM configurations FBD[31:0] 256K x32 FBD[63:32] 256K x32 RIVA 128 FBD[95:64] 256K x32 Expansion to 4MBytes FBD[127:96] 256K x32 Read and write accesses to SGRAM are burst oriented. SGRAM commands supported by the RIVA 128 are shown in Table 5. Initialization of the memory devices is performed in the standard SGRAM manner as described in Section 6.1. Access sequences begin with an Active command followed by a Read or Write command. The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. The RIVA 128 always uses a burst length of one and can launch a new read or write on every cycle. SGRAM has a fully synchronous interface with all signals registered on the positive edge of FBCLKx. Multiple clock outputs allow reductions in signal loading and more accuracy in data sampling at high frequency. The clock signals can be interspersed as shown in Figure 23, page 29 for optimal loading with either 2 or 4MBytes. The I/O timings relative to FBCLKx are shown in Figure 25, page 31. 28/77 128-BIT 3D MULTIMEDIA ACCELERATOR Figure 23. 2 and 4MByte SGRAM configurations RIVA 128 FBA[10] 1 FBA[9:0] FBRAS# FBCAS# FBWE# FBCKE# FBDQM[0]# FBDQM[1]# FBDQM[2]# FBDQM[3]# FBCS[0]# FBCLK0 FBA[10] 1 FBA[9:0] FBRAS# FBCAS# FBWE# FBCKE# FBDQM[4]# FBDQM[5]# FBDQM[6]# FBDQM[7]# FBCS[0]# FBCLK1 FBD[63:32] 256K×32 SGRAM FBD[31:0] 256K×32 SGRAM FBD[127:0] Expansion to 4MBytes FBDQM[8]# FBDQM[9]# FBDQM[10]# FBDQM[11]# FBCS[1]# FBCLK0 FBD[95:64] 256K×32 SGRAM FBDQM[12]# FBDQM[13]# FBDQM[14]# FBDQM[15]# FBCS[1]# FBCLK1 FBD[127:96] 256K×32 SGRAM NOTE 1 RIVA 128 has a pin reserved for an eleventh address signal, F BA[10], which may be used in the future with pin compatible 16MBit 256K x 2 x 32 SDRAMs. This signal is a “no-connect” in the initial RIVA 128 but may be activated in a future pincompatible upgrade. If there is sufficient routing space it may be prudent to route this signal to pin 30 of the 100 pin PQFP SGRAM. [FBA10] should be pulled to GND with a 47KΩ resistor. 29/77 RIVA 128 Table 5. 128-BIT 3D MULTIMEDIA ACCELERATOR Truth table of supported SGRAM commands FBCSx H L L L FBRAS# FBCAS# FBWE# x H L H x H H L x H H H FBDQM x x x x FBA[9:0] x x FBA[9]=bank FBA[8:0]=row FBA[9]=bank FBA[8]=0 FBA[7:0]=row FBD[63:0] Notes x x x x Command1 Command inhibit (NOP) No operation (NOP) Active (select bank and activate row) Read (select bank and column and start read burst) Write (select bank and column and start write burst) Precharge (deactivate row in both banks) Load mode register Write enable/output enable Write inhibit/output High-Z NOTES 1 2 L H L L x FBA[9]=bank valid data FBA[8]=0 FBA[7:0]=row FBA[8]=1 FBA[8:0] = opcode active high-Z 2 2 x L L - L L - H L - L L - x x L H FBCKE is high and DSF is low for all supported commands. Activates or deactivates FBD[127:0] during writes (zero clock delay) and reads (two-clock delay). 6.1 SGRAM INITIALIZATION SGRAMs must be powered-up and initialized in a predefined manner. The first SGRAM command is registered on the first clock edge following PCIRST# inactive. All internal SGRAM banks are precharged to bring the device(s) into the “all bank idle” state. The SGRAM mode registers are then programmed and loaded to bring them into a defined state before performing any operational command. 6.2 SGRAM MODE REGISTER The Mode register defines the mode of operation of the SGRAM. This includes burst length, burst type, read latency and SGRAM operating mode. The Mode register is programmed via the Load Mode register and retains its state until reprogrammed or power-down. Mode register bits M[2:0] specify the burst length; for the RIVA 128 SGRAM interface these bits are set to zero, selecting a burst length of one. In this case FBA[7:0] select the unique column to be accessed and Mode register bit M[3] is ignored. Mode register bits M[6:4] specify the read latency; for the RIVA 128 SGRAM interface these bits are set to either 2 or 3, selecting a burst length of 2 or 3 respectively. 30/77 128-BIT 3D MULTIMEDIA ACCELERATOR 6.3 LAYOUT OF FRAMEBUFFER CLOCK SIGNALS RIVA 128 Separate clock signals FBCLK0 and FBCLK1 are provided for each bank of SGRAM to give reduced clock skew and loading. Additionally there is a clock feedback loop between FBCLK2 and FBCLKFB. It is recommended that long traces are used without tunable components. If the layout includes provision for expansion to 4MBytes, the clock path to the 2MByte parts should be at the end of the trace, and the clock path to the 4MByte expansion located between the RIVA 128 and the 2MByte parts as shown in Figure 24. FBCLK2 and FBCLKFB should be shorted together as close to the package as possible and connected via a 150Ω resistor to VCC (3.3V), again as close to the package as possible. Figure 24. Recommended memory clock layout VDD (3.3V) 150Ω Expansion to 4MBytes FBCLK2 FBCLKFB RIVA 128 FBCLK0 Bank 1 256K x32 Bank 0 256K x32 t t FBCLK1 256K x32 256K x32 6.4 SGRAM INTERFACE TIMING SPECIFICATION SGRAM I/O timing diagram Figure 25. tCK FBCLKx tCH tAS, tDS tAH , tDH tAC FBD[63:0] tLZ tOH tCL FBA[9:0], FBD[63:0] Table 6. SGRAM I/O timing parameters Symbol Parameter -10 Min. -12 12 4.5 -10 Max. -12 ns ns Unit Notes tCK tCH CLK period CLK high time 10 3.5 31/77 RIVA 128 Symbol Parameter -10 Min. 128-BIT 3D MULTIMEDIA ACCELERATOR Max. -12 4.5 4 1 4 1 3 9 0 -10 -12 ns ns ns ns ns ns ns ns Unit Notes tCL tAS tAH tDS tDH tOH tAC tLZ Figure 26. CLK low time Address setup time Address hold time Write data setup time Write data hold time Read data hold time Read data access time Data out low impedance time 3.5 3 1 3 1 3 9 0 SGRAM random read accesses within a page, read latency of two1 FBCLKx Command FBA[9:0] FBD[63:0] read read read read nop nop bank, col n bank, col a bank, col x bank, col m data n data a data x data m NOTE 1 Covers either successive reads to the active row in a given bank, or to the active rows in different banks. DQMs are all active (LOW). Figure 27. SGRAM random read accesses within a page, read latency of three1 FBCLKx Command FBA[9:0] FBD[63:0] read read read read nop nop nop bank, col n bank, col a bank, col x bank, col m data n data a data x data m NOTE 1 Covers either successive reads to the active row in a given bank, or to the active rows in different banks. FBDQM is all active (LOW). 32/77 128-BIT 3D MULTIMEDIA ACCELERATOR Figure 28. SGRAM read to write, read latency of three FBCLKx TDDQM Command FBA[9:0] read bank, col n nop nop nop write RIVA 128 bank, col b FBD[63:0] tHZ read data n tDS write data b Table 7. SGRAM I/O timing parameters Symbol Parameter Data out high impedance time Write data setup time Min. 4 4 Max. 10 Unit ns ns Notes tHZ tDS Figure 29. SGRAM random write cycles within a page FBCLKx Command FBA[9:0] FBD[63:0] write bank, col n data n write bank, col a data a write bank, col x data x write bank, col m data m NOTE 1 Covers either successive writes to the active row in a given bank or to the active rows in different banks. FBDQM is active (low). Figure 30. SGRAM write to read cycle FBCLKx Command FBA[9:0] FBD[63:0] write bank, col n write data n nop read bank, col b nop nop nop write data n read data b NOTE 1 A read latency of 2 is shown for illustration 33/77 RIVA 128 Figure 31. 128-BIT 3D MULTIMEDIA ACCELERATOR SGRAM read to precharge, read latency of two tRP FBCLKx Command FBA[9:0] FBD[63:0] read precharge nop nop active bank,row bank, col n bank(s) data n NOTE 1 FBDQM is active (low) Figure 32. SGRAM read to precharge, read latency of three FBCLKx Command FBA[9:0] FBD[63:0] read bank, col n tRP precharge nop bank(s) data n nop active bank, row NOTE 1 FBDQM is active (low) Figure 33. SGRAM Write to Precharge tRP FBCLKx FBDQM# Command FBA[9:0] FBD[63:0] write bank, col n tWR write data n write data n+1 nop nop precharge bank(s) nop nop active row 34/77 128-BIT 3D MULTIMEDIA ACCELERATOR Figure 34. SGRAM Active to Read or Write RIVA 128 FBCLKx Command active nop tRCD nop read or write Table 8. SGRAM timing parameters Symbol Parameter FBCSx, FBRAS#, FBCAS#, FBWE#, FBDQM setup time FBCSx, FBRAS#, FBCAS#, FBWE#, FBDQM hold time Load Mode register command to command Active to Precharge command period Active to Active command period Active to Read or Write delay Refresh period (1024 cycles) Precharge command period Active bank A to Active bank B command period Transition time Write recovery time 2 4 3 1 Min. 3 1 2 7 10 3 16 Max. Unit ns ns tCK tCK tCK tCK ms tCK tCK ns tCK Notes tCS tCH tMTC tRAS tRC tRCD tREF tRP tRRD tT tWR 35/77 RIVA 128 7 VIDEO PLAYBACK ARCHITECTURE 128-BIT 3D MULTIMEDIA ACCELERATOR ‘temporal averaging’ being applied based on intraframing. • Linestore: - To support high quality video playback the RIVA 128 memory controller and video overlay engine supports horizontal and vertical interpolation using a 3x2 multitap interpolating filter with image sharpening. • YUV to RGB conversion: - YUV 4:2:2 format to 24-bit RGB true-color - Chrominance optimization/user control • Color key video composition The RIVA 128 video playback architecture is designed to allow playback of CCIR PAL or NTSC video formats with the highest quality while requiring the smallest video surface. The implementation is optimized around the Windows 95 Direct Video and ActiveX APIs, and supports the following features: • Accepts interlaced video fields: - This allows the off-screen video surface to consume less memory since only one field (half of each frame) is stored. Double buffering between fields is done in hardware with Figure 35. Video scaler pipeline Linestore YUV Vertical Interpolation Filter (Smooth/Sharpen) Color Space Conversion to 24-bit RGB Horizontal Interpolation 24-bit RGB Video output Video windowing, merge with graphics pixel pipeline 36/77 128-BIT 3D MULTIMEDIA ACCELERATOR 7.1 VIDEO SCALER PIPELINE Horizontal stretching RIVA 128 The RIVA 128 video scaler pipeline performs stretching of video images in any arbitrary factor in both horizontal and vertical directions. The video scaler pipeline consists of the following stages: 1 Vertical stretching 2 Filtering 3 Color space conversion 4 Horizontal stretching Vertical stretching Vertical stretching is performed on pixels prior to color conversion. The video scaler linearly interpolates the pixels in the vertical direction using an internal buffer which stores the previous line of pixel information. Filtering After vertical interpolation, the pixels are horizontally filtered using an edge-enhancement or a smoothing filter. The edge-enhancement filter enhances picture transition information to prevent loss of image clarity following the smoothing filtering stage. The smoothing filter is a low-pass filter that reduces the noise in the source image. Color space conversion The video overlay pipeline logic converts images from YUV 4:2:2 format to 24-bit RGB true-color. The default color conversion coefficients convert from YCrCb to gamma corrected RGB. Saturation controls make sure that the conversion does not exceed the output range. Four control flags in the color converter provides 16 sets of color conversion coefficients to allow adjustment of the hue and saturation. The brightness of each R G B component can also be individually adjusted, similar to the brightness controls of the monitor. Horizontal stretching is done in 24-bit RGB space after color conversion. Each component is linearly interpolated using a triangle 2-tap filter. Windowing and panning Video images are clipped to a rectangular window by a pair of registers specifying the position and width. By programming the video start address and the video pitch, the video overlay logic also supports a panning window that can zoom into a portion of the source image. Video composition With the color keying feature enabled, a programmable key in the graphics pixel stream allows selection of either the video or the graphics output on a pixel by pixel basis. Color keying allows any arbitrary portions of the video to overlay the graphics. With color keying disabled and video overlay turned on, the video output overlays the graphics in the video window. Interlaced video The video overlay can display both non-interlaced and interlaced video. Traditional video overlay hardware typically drops every other field of an interlaced video stream, resulting in a low frame rate. Some solutions have attempted to overcome the this problem by deinterlacing the fields into a single frame. This however introduces motion artifacts. Fast moving objects appearing in different positions in different fields, when deinterlaced, introduces visible artifacts which look like hair-like lines projecting out of the object. 37/77 RIVA 128 Figure 36. Displaying 2 fields with 1:1 ratio Frame 1 (Top field) 128-BIT 3D MULTIMEDIA ACCELERATOR Frame 2 (Bottom field) Line 10 Line 11 Interpolated line (Line 11 & 13) Line 12 Line 13 Interpolated line (Line 10 & 12) The RIVA 128 video overlay handles interlaced video by displaying every field, at the original frame rate of the video (50Hz for PAL and 60Hz for NTSC). The video scaling logic upscales, in the vertical direction, the luma components in each field and linearly interpolates successive lines to produce the missing lines of each field. This interpolated scale is applied such that the full frame size of each field is stretched to the desired height. The video scaler offsets the bottom field image by half a source image line to ensure that both frames when played back align vertically. The vertical filtering results in a smooth high quality video playback. Also by displaying both fields one after another, any motion artifacts often found in deinterlaced video output are removed, because the pixels in each field are displayed in the order in which the original source was captured. 38/77 128-BIT 3D MULTIMEDIA ACCELERATOR 8 VIDEO PORT RIVA 128 - Local interrupt and pixel stream handling - Hardware buffer management of compressed data, decompressed video pixel data and decompressed audio streams • Supports popular video decoders including the Philips SAA7111A, SAA7112, ITT 3225, and Samsung KS0127. The Video Port initiates transfers of video packets over the internal NV bus to either on or off screen surfaces as defined in the DirectDraw and DirectVideo APIs. • Supports filtered down-scaling or decimation • Allows additional devices to be added The RIVA 128 Multimedia Accelerator introduces a multi-function Video Port that has been designed to exploit the bus mastering functionality of the RIVA 128. The Video Port is compliant with a simplified ITU-R-656 video format with control of attached video devices performed through the RIVA 128 serial interface. Video Port support includes: • Windows 95 DirectMPEG API acceleration by providing: - Bus mastered compressed data transfer to attached DVD and MPEG-2 decoders Figure 37. Connections to multiple video modules SDA SCL RIVA 128 MPCLK MPAD[7:0] MPFRAME# MPDTACK# MPSTOP# TV tuner Video decoder S Video PCI/AGP VMI 1.4 Media Port Controller (MPC) ITU-R-656 DVD Controller 8.1 VIDEO INTERFACE PORT FEATURES • • • • • • Single 8-bit bus multiplexing among four transfer types: video, VBI, host and compressed data Synchronous 40MHz address/data multiplexed bus Hardware-based round-robin scheduler with predictable performance for all transfer types Supports multiple video modules and one ribbon cable board on the same bus ITU-R-656 Master Mode Video Port - Simplified ITU-R-656 Video Format -- supports HSYNC, VSYNC, ODD FIELD and EVEN FIELD - VBI data output from video decoder is captured as raw or sliced data 39/77 RIVA 128 8.2 BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC 128-BIT 3D MULTIMEDIA ACCELERATOR the initiation of the read cycle. The Media Port transfers the address of the register to be read during this cycle. After completion of the Read Issue cycle the media port goes back to polling for the next transaction. When it receives a Read Data ready command, it will start the next cycle in the read. CPU Register Read Receive Initiated by the MPC ASIC when it has read data ready to be transferred to the media port. The MPC ASIC waits for the next polling cycle and returns a Read Data Ready status. The media port will transfer the read data on the next Read Receive Cycle. The PCI bus will be held off and retry until the register read is complete. Video Compressed Data DMA Write Initiated by the MPC ASIC with the appropriate Polling Command. The media port manages the Video Compressed data buffer in system memory. Each request for data will return 32 bytes in a single burst. Display Data DMA Read Initiated by the MPC ASIC with the polling command. The MPC ASIC initiates this transfer when it wishes to transfer video data in ITU-R-656 format. The Media Port transfers data using a Polling Protocol. The Media Port is enabled on the RIVA 128 by the host system software. The first cycle after being enabled is a Poll Cycle. The MPC ASIC must respond to every poll cycle with valid data during DTACK active. If no transactions are needed, it responds with 00h. The Media Port will continue to Poll until a transaction is requested, or until there is a Host CPU access to an external register. Polling Cycle Media Port initiates a Polling Cycle whenever there is no pending transaction. This gives the MPC ASIC a mechanism to initiate a transaction. The valid Polling commands are listed in the Polling Command table. The priority for the polling requests should be to give the Display Data FIFO highest priority. CPU Register Write Initiated by the Host system software. CPU Register Read Issue Initiated by the Host system software. The read differs from the write in the fact that it must be done in two separate transfers. The Read Issue is just Table 9. Media Port Transactions Transaction Poll_Cycle CPUWrite CPURead_Issue CPURead_Receive VCD_DMA_Write Display_Data_Read A0 Cycle 11xx0000 00xx---01xx1111 11xx1111 01xx0001 11xx1000 Description Polling Cycle CPU Register Write CPU Register Read Issue CPU Register Read Receive Video Compressed Data DMA Write Display Data DMA Read Table 10. BIT 0 1 3 4 Polling Cycle Commands Data 000xxxx1 000xxx1x 000x1xxx 0001xxxx 00000000 NV_PME_VMI_POLL_UNCD NV_PME_VMI_POLL_VIDCD NV_PME_VMI_POLL_INT NV_PME_VMI_POLL_CPURDREC NULL Description Request DMA Read of Display Data Request DMA Write of Video Compressed Data Request for Interrupt Respond to Read Issue - Read Data Ready No Transactions requested 40/77 128-BIT 3D MULTIMEDIA ACCELERATOR 8.3 TIMING DIAGRAMS Poll cycle RIVA 128 Figure 38. MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 D0 Figure 39. Poll cycle throttled by slave MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 D0 Figure 40. CPU write cycle MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 A1 D Figure 41. CPU write cycle throttled by slave MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 A1 D 41/77 RIVA 128 Figure 42. 128-BIT 3D MULTIMEDIA ACCELERATOR CPU read issue cycle - cannot be throttled by slave MPCLK MPFRAME# MP_AD[7:0] A0 A1/D Figure 43. CPU read_receive cycle MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 D0 Figure 44. CPU read_receive cycle - throttled by slave MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 D0 Figure 45. CD write cycle - terminated by master MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 D0 D1 D2 D3 42/77 128-BIT 3D MULTIMEDIA ACCELERATOR Figure 46. CD write cycle - terminated by slave in middle of transfer MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 D1 D2 XXX A0 D3 D4 RIVA 128 Figure 47. CD write cycle - terminated by slave on byte 31 MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 D30 XXX A0 D31 Figure 48. CD write cycle - terminated by slave on byte 32, no effect MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 D30 D31 Figure 49. UCD read cycle, terminated by master, throttled by slave MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 D0 XXX D1 D2 D3 43/77 RIVA 128 Figure 50. 128-BIT 3D MULTIMEDIA ACCELERATOR UCD read cycle, terminated by slave, throttled by slave MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 XXX D1 D2 Figure 51. UCD read cycle, slave termination after MPFRAME# deasserted, data taken MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 D1 D2 D3 Figure 52. UCD read cycle, slave termination after MPFRAME# deasserted, data not taken MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 D1 D2 D3 Figure 53. UCD read cycle, slave termination after MPFRAME# deasserted, data taken MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 D1 D2 44/77 128-BIT 3D MULTIMEDIA ACCELERATOR 8.4 656 MASTER MODE RIVA 128 The 656 Master Mode assumes that VID[7:0] and PIXCLK can be tri-stated when the slave is inactive. If a slave cannot tri-state all its signals, an external tri-state buffer is needed. Video data capture Video Port pixel data is clocked into the port by the external pixel clock and then passed to the RIVA 128's video capture FIFO. Pixel data capture is controlled by the ITU-R-656 codes embedded in the data stream; each active line beginning with SAV (start active video) and ending with EAV (end active video). In normal operation, when SAV = x00, capture of video data begins, and when EAV = xx1, capture of video data ends for that line. When VBI (Vertical Blanking Interval) capture is active, these rules are modified. Table 11 shows the Video Port pin definition when the RIVA 128 is configured in ITU-R-656 Master Mode. Before entering this mode, RIVA 128 disables all Video Port devices so that the bus is tristated. The RIVA 128 will then enable the video 656 master device through the serial bus. In this mode, the video device outputs the video data continuously at the PIXCLK rate. Table 11. 656 master mode pin definition Normal Mode MPCLK MPAD[7:0] MPFRAME# MPDTACK# MPSTOP# 656 Master Mode PIXCLK VID[7:0] Not used Not used Not used 656 master mode timing specification Figure 54. 656 Master Mode timing diagram t5 PIXCLK t3 t4 VID[7:0] t3 t4 t4 t3 Table 12. Symbol ITU-R-656 Master Mode timing parameters Parameter VID[7:0] hold from PIXCLK high VID[7:0] setup to PIXCLK high PIXCLK cycle time Min. 0 5 35 Max. Unit ns ns ns Notes t3 t4 t5 NOTE 1 VACTIVE indicates that valid pixel data is being transmitted across the video port. Table 13. 1st byte U[7:0] Cb[7:0] YUV (YCbCr) byte ordering 2nd byte Y0[7:0] Y0[7:0] 3rd byte V[7:0] Cr[7:0] 4th byte Y1[7:0] Y1[7:0] 5th (next dword) U[7:0] Cb[7:0] 6th byte Y0[7:0] Y0[7:0] 7th byte V[7:0] Cr[7:0] 45/77 RIVA 128 8.5 VBI HANDLING IN THE VIDEO PORT 128-BIT 3D MULTIMEDIA ACCELERATOR the lines specified and framed by normal ITU-R656 SAV/EAV codes. The RIVA 128 Video Port capture engine starts capturing data at an SAV code controlled by the device driver, and continues capturing data under control of SAV/EAV codes until a specific EAV code identified by the device driver is sampled. VBI capture is then complete for that field. The number of bytes collected will vary depending on the setup of the KS0127. 8.6 SCALING IN THE VIDEO PORT RIVA 128 supports two basic modes for VBI data capture. VBI mode 1 is for use with the Philips SAA7111A digitizer, VBI mode 2 is for use with the Samsung KS0127 digitizer. In VBI mode 1, the region to be captured as VBI data is set up in the SAA7111A via the serial interface, and in the RIVA 128 under software control. The SAA7111A responds by suppressing generation of SAV and EAV codes for the lines selected, and sending raw sample data to the port. The RIVA 128 Video Port capture engine starts capturing VBI data at an EAV code in the line last active and continues to capture data without a break until it detects the next SAV code. VBI capture is then complete for that field. In VBI mode 2, the region to be captured as VBI data is set up in a similar manner. The KS0127 responds by enabling VBI data collection only during The RIVA 128 Video Port allows any arbitrary scale factor between 1 and 31. For best results the scale factors of 1, 2, 3, 4, 6, 8, 12, 16, and 24 are selected to avoid filtering losses. The Video Port decimates in the y-direction, dropping lines every few lines depending on the vertical scaling factor. The intention is to support filtered downscaling in the attached video decoder. 46/77 128-BIT 3D MULTIMEDIA ACCELERATOR 9 BOOT ROM INTERFACE RIVA 128 BIOS and initialization code for the RIVA 128 is accessed from a 32KByte ROM. The RIVA 128 memory bus interface signals FBD[15:0] and FBD[31:24] are used to address and access one of 64KBytes of data respectively. The unique decode to the ROM device is provided by the ROMCS# chip select signal. Figure 55. ROM interface ROMCS# FBD[15:0] CS A[15:0] D[7:0] WE OE ROM RIVA 128 FBD[31:24] FBD[17] FBD[16] ROM interface timing specification Figure 56. ROM interface timing diagram ROM Read FDB[15:0] tBAS tBRCS ROMCS# OE# (FBD[16]) tBOS tBRV WE# (FBD[17]) tBDS tBDBZ FDB[31:24] data tBDH tBDZ tBOH tBRH address tBAH tBRCA ROM Write FDB[15:0] address tBAS ROMCS# OE# (FBD[16]) tBRCS tBAH tBWL tBWS WE# (FBD[17]) tBWDS FDB[31:24] data tBWDH 47/77 RIVA 128 Table 14. Symbol tBRCS tBRCA tBRV tBRH tBAS tBAH tBOS tBOH tBWS tBWL tBDBZ tBDS tBDH tBDZ tBWDH tBWDS NOTE 1 2 3 128-BIT 3D MULTIMEDIA ACCELERATOR ROM interface timing parameters Parameter ROMCS# active pulse width ROMCS# precharge time Read valid to ROMCS# active Read hold from ROMCS# inactive Address setup to ROMCS# active Address hold from ROMCS# inactive OE# low from ROMCS# active OE# low to ROMCS# inactive WE# low from ROMCS# active WE# low time Data bus high-z to ROMCS# active Data setup to ROMCS# inactive Data hold from ROMCS# inactive Data high-z from ROMCS# inactive Write data hold from ROMCS# inactive ROM write data setup to ROMCS# active 0.5TMCLK-5 TMCLK-5 TMCLK-5 10 0 TMCLK-5 Min. 20TMCLK-5 TMCLK-5 TMCLK-5 TMCLK-5 TMCLK-5 TMCLK-5 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 3 2 3 Notes TMCLK is the period of the internal memory clock. This parameter is programmable in the range 0 - 3 MCLK cycles This parameter is programmable in the range 0 - 15 MCLK cycles 48/77 128-BIT 3D MULTIMEDIA ACCELERATOR 10 POWER-ON RESET CONFIGURATION RIVA 128 The RIVA 128 latches its configuration on the trailing edge of RST# and holds its system bus interface in a high impedance state until this time. To accomplish this, pull-up or pull-down resistors are connected to the FBA[9:0] pins as appropriate. Power-on reset FBA[9:0] bit assignments 9 PCI Mode [9] 8 7 6 Crystal 5 Since there are no internal pull-up or pull-down resistors and the data bus should be floating during reset, a resistor value of 47KΩ should be sufficient. 4 RAM Width 3 2 1 SubVendor 0 Bus Speed TV Mode Host Interface RAM Type PCI Mode. This bit indicates whether the RIVA 128 initializes with PCI 2.1 compliance 0 = RIVA 128 is PCI 2.0 compliant (does not support delayed transactions) 1 = RIVA 128 is PCI 2.1 compliant (supports 16 clock target latency requirement). TV Mode. These bits select the timing format when TV mode is enabled. 00 = Reserved 01 = NTSC 10 = PAL 11 = TV mode disabled Crystal Frequency. This bit should match the frequency of the crystal or reference clock connected to XTALOUT and XTALIN. 0 = 13.500MHz (used where TV output may be enabled) 1 = 14.31818MHz Host Interface 0 = PCI 1 = AGP (Bit 0 must also be pulled high to indicate 66MHz) RAM Width 0 = 64-bit framebuffer data bus width (the upper 64-bit data bus and byte selects are tri-state) 1 = 128-bit framebuffer data bus width RAM Type 00 = Reserved 01 = 8Mbit SDRAM or SGRAM organized as 128K x 2 banks x 32-bit (normal SGRAM mode). 10 = Reserved 11 = 8Mbit SDRAM or SGRAM organized as 128K x 2 banks x 32-bit, framebuffer I/O pins remain tri-stated after reset. Sub-Vendor. This bit indicates whether the PCI Subsystem Vendor field is located in the system motherboard BIOS or adapter card VGA BIOS. If the Subsystem Vendor field is located in the system BIOS it must be written by the system BIOS to the PCI configuration space prior to running any PnP code. 0 = System BIOS (Subsystem Vendor ID and Subsystem ID set to 0x0000) 1 = Adapter card VGA BIOS (Subsystem Vendor ID and Subsystem ID read from ROM BIOS at location 0x54 - 0x57) Bus Speed. This bit indicates the value returned in the 66MHZ bit in the PCI Configuration registers (see page 64). 0 = RIVA 128 PCI interface is 33MHz 1 = RIVA 128 is 66MHz capable 49/77 [8:7] [6] [5] [4] [3:2] [1] [0] RIVA 128 128-BIT 3D MULTIMEDIA ACCELERATOR The following example configuration is shown in Figure 57: • Subsystem Vendor ID initialized to 0 and writeable by system BIOS (see Appendix A, page 70) • 8Mbit 128K x 2 bank x 32 SGRAM • 128-bit framebuffer interface • AGP including 66MHz PCI 2.1 compliant subset • Using 13.5000MHz crystal • TV output mode is NTSC Figure 57. Example motherboard configuration VDD (3.3V) 10KΩ FBA[0 ] FBA[1 ] FBA[2] FBA[3] AGP RIVA 128 FBA[4] FBA[5] FBA[6] FBA[7] FBA[8] FBA[9] FBA[10] SGRAM array 10KΩ 50/77 128-BIT 3D MULTIMEDIA ACCELERATOR 11 DISPLAY INTERFACE • High quality video overlay RIVA 128 11.1 PALETTE-DAC The Palette-DAC integrated into the RIVA 128 supports a traditional pixel pipeline with the following enhancements: • Support for 10:10:10, 8:8:8, 5:6:5 and 5:5:5 direct color pixel modes • Support for dynamic gamma correction on a pixel by pixel basis • Support for mixed indexed color and direct color pixels • 256 x 24 LUT for 8-bit indexed modes - Accepts interlaced video fields allowing a reduction in memory buffering requirements while incorporating temporal averaging - Line buffer for horizontal and vertical interpolation of video streams up to square pixel PAL resolution - 3x2 multitap interpolating filter with image sharpening - Color key in all color pixel modes - High quality YUV to RGB conversion with chrominance control. 11.2 PIXEL MODES SUPPORTED 8-bit indexed color In the 8-bit indexed color each 32-bit word contains four 8-bit indexed color pixels, each comprising bits b[7:0] as shown below. Pixel formats (FBD[31:0]) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 3 Pixel 2 Pixel 1 8 7 6 5 4 3 2 1 0 Pixel 0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 NOTE 1 This 32-bit representation can be extended to 64-bit and 128-bit widths by duplicating the 32-bit word in little-endian format. 16-bit direct color modes (5:6:5 direct and 5:5:5 with and without gamma correction) In 5:5:5 color modes bit 15 of each pixel can be enabled to select whether pixel data bypasses the LUT to feed the DACs directly, or indirectly, through the LUT, to allow gamma correction to be applied. If not enabled then the bypass mode will always be selected, and the LUT powered down. The 16-bit modes include a 5:6:5 format which always bypasses the LUT. Pixel formats (FBD[31:0]) 5:6:5 mode Pixel 1 Pixel 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 NOTE 1 This 32-bit representation can be extended to 64-bit and 128-bit widths by duplicating the 32-bit word in little-endian format. 0 1 Red gamma Red bypass Red bypass Green gamma Green bypass Green bypass Blue gamma Blue bypass Blue bypass 0 1 Red gamma Red bypass Red bypass Green gamma Green bypass Green bypass Blue gamma Blue bypass Blue bypass 32-bit direct color (8:8:8 with gamma correction or 10:10:10 direct) In 32-bit color mode bit 31 of each pixel selects whether pixel data bypasses the LUT, to feed the DACs directly or indirectly, through the LUT, to allow gamma correction to be applied. In the table below the Red, Green and Blue bypass bits are shown individually as R[9:0], G[9:0], and B[9:0] because, in the bypass 51/77 RIVA 128 128-BIT 3D MULTIMEDIA ACCELERATOR mode pixel format, the least significant bits of each color are located separately in the top byte of the pixel. This also permits an 8:8:8 mode without gamma with