S1HNK60

STS1HNK60 N-CHANNEL 600V - 8Ω - 0.3A SO-8 SuperMESH™Power MOSFET TYPE STS1HNK60 s s s s s VDSS 600 V RDS(on) < 8.5 Ω ID 0.3 A Pw 2W TYPICAL RDS(on) = 8 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED NEW HIGH VOLTAGE BENCHMARK SO-8 DESCRIPTION The SuperMESH™ series is obtained through an extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS SWITCH MODE LOW POWER SUPPLIES (SMPS) s LOW POWER, LOW COST CFL (COMPACT FLUORESCENT LAMPS) s LOW POWER BATTERY CHARGERS s ORDERING INFORMATION SALES TYPE STS1HNK60 MARKING S1HNK60 PACKAGE SO-8 PACKAGING TAPE & REEL August 2003 1/8 STS1HNK60 ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM ( ) PTOT dv/dt (1) Tj Tstg Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature Value 600 600 ± 30 0.3 0.19 1.2 2 0.016 3 -65 to 150 Unit V V V A A A W W/°C V/ns °C ( ) Pulse width limited by safe operating area (1) ISD ≤0.3A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. THERMAL DATA Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 °C VGS = ± 30 V VDS = VGS, ID = 250 µA VGS = 10 V, ID = 0.5 A 2.25 3 8 Min. 600 1 50 ±100 3.7 8.5 Typ. Max. Unit V µA µA nA V Ω 2/8 STS1HNK60 ELECTRICAL CHARACTERISTICS (CONTINUED) DYNAMIC Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max, ID = 0.5 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 1 156 23.5 3.8 Max. Unit S pF pF pF SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 300 V, ID = 0.5 A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) VDD = 480 V, ID = 1 A, VGS = 10V, RG = 4.7Ω Min. Typ. 6.5 5 7 1.1 3.4 10 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf tr(Voff) tf tc Parameter Turn-off Delay Time Fall Time Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 300 V, ID = 0.5 A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) VDD = 480V, ID = 1.0 A, RG = 4.7Ω, VGS = 10V (Inductive Load see, Figure 5) Min. Typ. 19 25 24 25 44 Max. Unit ns ns ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 0.3 A, VGS = 0 ISD = 0.3 A, di/dt = 100 A/µs VDD = 25 V, Tj = 150°C (see test circuit, Figure 5) 229 377 3.3 Test Conditions Min. Typ. Max. 0.3 1.2 1.6 Unit A A V ns µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3/8 STS1HNK60 Safe Operating Area Thermal Impedance Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/8 STS1HNK60 Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature 5/8 STS1HNK60 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STS1HNK60 SO-8 MECHANICAL DATA DIM. MIN. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019 0016023 7/8 STS1HNK60 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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