SCLT3-8BQ7-TR

SCLT3-8BQ7, SCLT3-8BT8 Datasheet High speed digital input current limiter with digital filter Features QFN 7x7 - 48L HTSSOP-38 package 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 4 34 33 5 32 6 31 7 30 8 29 9 28 10 27 11 12 26 • • • • • • • • • • • • 25 13 14 15 16 17 18 19 20 21 22 23 24 Top view Product status link SCLT3-8BQ7, SCLT3-8BT8 8 inputs - 8-bit SPI output High side input with common ground 5 V voltage regulator Package: QFN 7x7 - 48L or HTSSOP-38 35 V reverse polarity capable Adjustable current limiters LED output for visual status Optional: 16-bit mode with parity check, temperature and voltage alarms Daisy chain capable Input digital filter with adjustable delay: 20 µs to 3 ms Power dissipation: 78 mW per channel Complies with the following standards: – IEC 61000-4-2: ◦ ±8 kV (contact discharge) ◦ ±15 kV (air discharge) – IEC 61000-4-4: ◦ Input: ±1 kV ◦ Power supply: ±2.5 kV Applications • • • Programmable logic controller and remote input modules High speed protected termination for digital input with serialized SPI output IEC61131-2 type 1, 2 and 3 Description The SCLT3 series provides an 8-line protected digital input termination with serialized state transfer. This device enhances the I/O module density by cutting the dissipation (78 mW per input) and reducing the count of opto-transistors. An adjustable digital filter and an LED driver are embedded in each type 3 input section. Its 2 MHz SPI peripheral output serializes the input state transfer to the I/O module controller. DS11042 - Rev 5 - January 2022 For further information contact your local STMicroelectronics sales office. www.st.com SCLT3-8BQ7, SCLT3-8BT8 Circuit block diagrams 1 Circuit block diagrams Figure 1. Circuit block diagram IN1 VDD Protected input 16 µs / 3 ms digital filters 8 lines Clock divider /CS SHIFT 4 lines SPM 16-bit VC Power supply Power reset VDD VCS Under voltage alarm Over temperature alarm 8 / 64 Transfer logic SCK Current reference Oscillator MOSI MOSI DVR OSC VDD WRITE SHIFT Control state register REF /MISO COMS CAPTURE Parity bits gen. 7 lines 8 lines 8 lines I=2t o8 LDI Protected input COMP Data state register VIN 500 Ω VDD VDD Internal logic power supply voltage IDD VDD Internal logic power supply voltage RC > 500 Ω VI IN Input repetitive steady state voltage RI = 2.2 kΩ(2) VLD LDI FINmax IN FSCKmax LV OSC Tj V 10 mA -30 to 35 V Maximum LED output voltage, I = 1 to 8 2.7 V Maximum single input frequency8-bit mode 20 kHz 0.1 to 2 MHz 15 k to 1.5 M Ω 0 to 5.5 V Filter oscillator resistance range VCC ≤ 30 V All Unit V SCK, / CS, MOSI, Logic input / output voltage MISO, /MISO Tamb 15 to 35(1) 5 Maximum SPI clock frequency ROSC Value Operating ambient temperature range VCC ≤ 24 V, Rth(j-a) = 70 °C/W Operating junction temperature range -40 to 85 -40 to 105 -40 to 150 °C °C 1. 32 V in DC; 35 V during 0.5 s max 2. VI = VIN + RI x IIN DS11042 - Rev 5 page 6/20 SCLT3-8BQ7, SCLT3-8BT8 Characteristics Table 4. DC electrical characteristics based on figure 2 application environment Symbol Pin Name Conditions ILIM IN VIN = 5.5 to 26 V, RI = 2.2 kΩ ION LDI On state LED current Min. Typ. Max. Unit 2.1 2.35 2.6 mA Input current limitation VI = 11 V 2 mA Input digital filter ROSC = 51 kΩ TOSC OSC Oscillator period ROSC OSC Oscillator resistance tCKF tFT ROSC = 1200 kΩ CKF period IN 1.13 1.37 µs 20 28 µs 51 1200 kΩ DVR = VDD 64 x TOSC DVR = COMS 8 x TOSC 2 x tCKF Filtering time 3 x tCKF Table 5. SPI electrical characteristics (Tj = 25 °C, VCC = 24 V, VDD = 5 V respect to COM ground pin; unless otherwise specified) Symbol Pin Name FCK SCK Clock frequency TS MOSI Data setup time MOSI toggling to SCK rising TD MISO Write out propagation time SCK falling to MISO toggling, COUT = 10 pF TLD SCK Enable lead time /CK falling to SCK rising 80 ns THC SCK Clock hold time SCK falling to /CS rising 160 ns TDT /CS Transfer delay time /CS rising to /CS falling TH MOSI Data hold time SCK rising to MOSI toggling TDIS MISO Data output disable time /CS rising to MISO disabled 200 ns LVIH MOSI, SCK, /CS Logic input high voltage Share of VDD 70 % Logic input low voltage Share of VDD 30 IOH = 3 mA 4 LVIL LVOH MISO, /MISO Logic output high voltage LVOL TRO, TFO DS11042 - Rev 5 Logic output low voltage MISO, /MISO MISO signal fall/rise time TA MISO Output access time DUCY SCK Clock duty cycle Conditions Min. Typ. Max. Unit 2 MHz 25 ns 50 150 25 IOL = 3 mA ns ns % 4.75 0.25 IMISO = 3 mA 20 /CS falling to MISO toggling 40 25 ns V 1 V ns 80 ns 75 % page 7/20 SCLT3-8BQ7, SCLT3-8BT8 Characteristics Figure 5. Time diagram TFRAME /CS TCH TLD SCK TCL 1 THC TR 2 7 8 MSB M 7 2 LSB M TD TA MSB S MISO TDT TS TH MOSI TF MSB S TDIS 7 2 LSB S MSB M Table 6. Electromagnetic compatibility ratings Symbol Pin VPPB VI VPP VPP Parameter name(1) Value Unit Peak pulse voltage burst, IEC61000-4-4(2) 4 kV VI Peak pulse voltage surge, IEC61000-4-5 1 kV VCC Peak pulse voltage surge, IEC61000-4-5 2.5 kV ESD protection, IEC 61000-4-2, per input: VESD VIN Air Contact 15 8 kV 1. Test set-up, see application Figure 2 2. See AN3031. DS11042 - Rev 5 page 8/20 SCLT3-8BQ7, SCLT3-8BT8 Functional description 3 Functional description 3.1 Operation of the SCLT3 with SPI bus (CPOL = 0, CPHA = 0) The SPI bus master controller manages the data transfer with the chip select signal /CS and controls the data shift in the register with the clock SCK signal. Figure 6. Serial data format frame CS SCK MOSI MISO DATA CAPTURE 1 MSBM MSBS 1 2 3 4 13 14 15 16 14 13 12 3 2 1 LSBM MSBS 14 13 12 3 2 1 LSBS MSBM 2 3 4 13 14 15 16 The transfer of the SCLT3 input states in the SPI registers starts when the chip select /CS signal falls and ends when this /CS is rising back. The transfer of data out of the SCLT3 slave MISO output starts immediately when the chip select /CS goes low. Then, the input MOSI is captured and presented to the shift register on each rising edge of the clock SCK. And the data are shifted in this register on each falling edge of the serial clock SCK, the data bits being written on the output MISO with the most significant bit first. 3.1.1 The serial data Input MOSI This input signal MOSI is used to shift external data bits into the CLT01-38SQ7 register from the most significant MSB bit to the lower significant one LSB. The data bits are captured by the CLT01-38SQ7 on the rising edge of the serial clock signal SCK. 3.2 The input digital filter Depending on the biasing of the SPM pin, the data frame is 8-bits or 16-bits. A digital filter is implemented between the input state comparator and the input state register. It consists of a 2-step sampling circuit that is controlled by an oscillator as shown on . The filtering time tFT is set by the external oscillator resistor and is a function of the oscillator period tCKF: • 2 x tCKF < tFT < 3 x tCKF • tCKF = Divider ratio x tOSC (ROSC) This period can be adjusted between 20 μs and 3000 μs as shown on Table 7. Typical setting of the digital filter timings. DS11042 - Rev 5 page 9/20 SCLT3-8BQ7, SCLT3-8BT8 The SPI data transfer operation Table 7. Typical setting of the digital filter timings Input speed Fast Medium Slow Input frequency (kHz) 60 20 5 0.3 Min. filter time tFT (μs) 20 50 230 3000 OSC resistance (kΩ) 51 150 82 1300 CKF period tCKF (μs) 10 25 115 1500 COMS COMS VDD VDD 8 8 64 64 DVR connection Divider ratio Being placed in the front end of the module, this filter increases the transient immunity of the SCLT and its SPI logic circuitry. It also simplifies the input management software task of the ASIC controller. Figure 7. Two step digital filter placed after the analog section of the logic input IN D Q D Q D Q S Q CK /Q CK /Q CK /Q OUT R CKF CKF IN OUT T 3.3 The SPI data transfer operation 3.3.1 The SPI data frame Depending on the biasing of the SPM pin, the data frame is 8-bits or 16-bits. The selected structure of the SPI is a 16-bit word in order to be able to implement the input state data and some control bits such as the UVA alarm, the 4 checksum bits and the two low and high state stop bits. 3.3.2 The SPI data transfer The SCLT3 transfers its 16 data bits through the SPI within one chip select Hi-Lo-Hi sequence. So, this length defines the minimum length that the shift register of the SPI master controller is able to capture: 16 bits. The Table 8 shows the 16-bit mode way the data are transferred starting from the data bits, the control bits and ending by a stop bit. DS11042 - Rev 5 page 10/20 SCLT3-8BQ7, SCLT3-8BT8 Control bit signals of the SPI transferred data frame Table 8. SPI data transfer organization versus CLT input states with SPM = 0 Bit # LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Control High(1) Low PC4 PC3 PC2 PC1 /OTA /UVA Bit # Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 MSB Data IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8(2) 1. Last OUT 2. First OUT 3.4 3.4.1 Control bit signals of the SPI transferred data frame The power bus voltage monitoring The UVA circuit generates the alarm /UVA that is active low when the power bus voltage is lower than the activation threshold VCON, 17 V typical, and it is disabled high when the power bus voltage rises above the threshold VCOFF, 18 V typical. 3.4.2 The over temperature alarm The alarm signal /OTA is enabled, low state active, when the junction temperature is higher than the activation threshold TON, 150 ºC typical, and it is disabled when the junction temperature falls below the threshold TOFF, 140 ºC typical. 3.4.3 The parity checksum bits calculation and transfer The aim of the parity checksum bit is to detect one error in the transferred SPI word. Several parity checksum bits are generated and transmitted through the SPI on the control bit #2 to #5. In order to calculate parity bit, “exclusive NOR” operations are performed as follow: Figure 8. SCLT3 parity bit calculation example IN8 1 3.5 IN7 0 IN6 0 IN5 IN4 1 1 IN3 0 PC1 PC2 PC3 PC4 1 1 1 1 IN2 0 IN1 1 Loss of VCC power supply The operation of the SCLT3 is extended below the levels required in the IEC 61131-2 standard to allow the implementation of the under voltage alarm UVA as described the SPI control bit section. If there is no more power feeding on the VCC input, the SCLT3 chip goes to sleep mode, and the MISO output is forced in low state during SPI transfer attempt. The last SPI control data bit is a stop bit placed normally in high state all time: the loss of power supply is detected by checking its state: if low, the output is disabled by the internal power reset POR. This POR signal is active in low state when VC is less than 9 V or the internal power supply VDD is less than 3.25 V. DS11042 - Rev 5 page 11/20 SCLT3-8BQ7, SCLT3-8BT8 Loss of VCC power supply Table 9. Logic state of the SPI output versus the power loss signal POR and the SPI chip select /CS POR /CS MISO /MISO SPI status 1 1 Z Z Normal with no communication 1 0 1 0 Normal with communication 1 0 0 1 Normal with communication 0 1 Z Z Power loss with no communication 0 0 0 1 Power loss with communication attempt Figure 9. Logic status of the SCLT3 power supply Power supply suppl ystatus status Loss of power po wer UV Alarm 15V Power good 17V VC =V CC -R C x (I C + IDD) ~5V 9V 11V VCC 19V IEC61131-2 le vel VC 13V UVA /CS = Lo POR /CS = Lo MISO /CS = Lo ;I N ASIC = MISO (non inver ting isolator) Figure 10. Typical limiting current ILIM versus reference resistance RREF ILIM (mA) 6 VCC = 24 V; V I = 24 V 5 4 3 2 1 RREF (kΩ) 0 0 DS11042 - Rev 5 10 20 30 40 page 12/20 SCLT3-8BQ7, SCLT3-8BT8 Loss of VCC power supply Figure 11. Typical limiting current ILIM versus junction temperature Tj ILIM (mA) 2.8 Rref = 15 kΩ with RIN = 2.2kΩ, VI = 11 to 30 V, V CC = 11 to 30 V 2.7 2.6 2.5 2.4 2.3 2.2 TJ (°C) 2.1 2 -25 0 25 50 75 100 125 150 Figure 12. Relative variation of minimum filter time tFT versus junction temperature TJ TFT MIN /T FT MIN (25°C) 1.15 1.1 1.05 ROSC < 150kΩ 1 ROSC = 1.2MΩ 0.95 0.9 TJ (°C) 0.85 25 50 75 100 125 150 Figure 13. Variation of junction to ambient thermal resistance Rth(j-a) versus printed circuit board copper surface SCU Rth(j-a)(°C/W) Printed circuit board, FR4 epoxy single layer, copper thickness = 35 µm 120 100 80 60 40 20 S CU(mm² ) 0 0 DS11042 - Rev 5 2 0 40 60 80 100 120 140 160 180 page 13/20 SCLT3-8BQ7, SCLT3-8BT8 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 QFN 7X7-48 L package information Figure 14. QFN 7X7-48 L package outline D e C 37 PIN #1 A3 48 1 36 e b E2 E 25 12 b K D2 A1 A D L 24 ddd C Bottom view 48 1 Top view DS11042 - Rev 5 page 14/20 SCLT3-8BQ7, SCLT3-8BT8 QFN 7X7-48 L package information Table 10. QFN 7X7-48 L package mechanical data Dimensions Inches(1) Millimeters Ref. Min. Typ. Max. Min. Typ. Max. 0.80 0.90 1.00 0.0315 0.0354 0.0394 A1 0.02 0.05 0.0008 0.0020 A3 0.203 A b 0.18 0.25 0.008 0.30 0.0071 0.0100 D 7.00 0.275 E 7.00 0.275 e 0.50 0.019 0.0118 D2 5.00 5.15 5.25 0.197 0.203 0.206 E2 5.00 5.15 5.25 0.197 0.203 0.206 K 0.20 L 0.30 0.40 0.50 0.015 0.019 0.008 0.011 1. Values in inches are converted from mm and rounded to 4 decimal digits. DS11042 - Rev 5 page 15/20 SCLT3-8BQ7, SCLT3-8BT8 HTSSOP-38 package information 4.2 HTSSOP-38 package information Figure 15. HTSSOP-38 package outline 38 20 E 1 E1 c e 19 14° D 0.25 mm A2 A b P A1 Ø L P1 DS11042 - Rev 5 page 16/20 SCLT3-8BQ7, SCLT3-8BT8 HTSSOP-38 package information Table 11. HTSSOP-38 package mechanical data Dimensions Millimeters Ref. Min. Typ. A Inches Max. Min. Typ. 1.10 A1 0.05 A2 0.85 b 0.17 0.90 Max. 0.043 0.15 0.002 0.95 0.033 0.27 0.007 0.006 0.035 0.037 0.011 c 0.09 0.20 0.003 D 9.60 9.70 9.80 0.378 0.382 0.008 0.386 E1 4.30 4.40 4.50 0.169 0.173 0.177 e 0.50 0.020 E 6.40 0.252 L 0.50 0.60 0.70 0.020 0.024 0.027 P 6.40 6.50 6.60 0.252 0.256 0.260 P1 3.10 3.20 3.30 0.122 0.126 0.130 Ø 0° 8° 0° 8° Figure 16. HTSSOP-38 footprint 0.5 1.30 0.60 7.10 0.3 DS11042 - Rev 5 3.30 4.50 6.60 page 17/20 SCLT3-8BQ7, SCLT3-8BT8 Ordering information 5 Ordering information Figure 17. Ordering information scheme SC LT 3 – 8 B X X Serial current limiter termination 3: 3 mA current setting 8: eight channels B: EMC level 1 kV according to IEC 61000-4-5 T 8: HTSSOP-38 Q7: QFN - 48L 7x7 Table 12. Ordering information Order code DS11042 - Rev 5 Marking Package Weight Base qty. Delivery mode SCLT3-8BT8-TR SCLT3-8BT8 HTSSOP-38 114 mg 2500 Tape and reel SCLT3-8BQ7-TR SCLT3-8BQ7 QFN7x7-48L 130 mg 2500 Tape and reel page 18/20 SCLT3-8BQ7, SCLT3-8BT8 Revision history Table 13. Document revision history DS11042 - Rev 5 Date Revision Changes 29-Jul-2016 1 Initial release. 12-Nov-2015 2 Updated Table 4. 05-Dec-2016 3 Added part number previously included in the datasheet DocID15191. Updated document accordingly. Minor text changes. 07-Oct-2021 4 Updated Figure 2. 03-Jan-2022 5 Updated Section 5 Ordering information. page 19/20 SCLT3-8BQ7, SCLT3-8BT8 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS11042 - Rev 5 page 20/20