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SDIP-38L

SDIP-38L

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

  • 描述:

    SDIP-38L - IGBT intelligent power module (IPM) 14 A, 600 V, DBC isolated SDIP-38L molded - STMicroel...

  • 数据手册
  • 价格&库存
SDIP-38L 数据手册
STGIPL14K60 IGBT intelligent power module (IPM) 14 A, 600 V, DBC isolated SDIP-38L molded Features ■ 14 A, 600 V 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull down/pull up resistors Internal bootstrap diode Interlocking function 5 kΩ NTC for temperature control VCE(sat) negative temperature coefficient Short-circuit rugged IGBTs Under-voltage lockout DBC fully isolated package Isolation rating of 2500 Vrms/min Smart shut down function Op-amps for advanced current sensing Comparators for fault protection against over current and short-circuit SDIP-38L AM01193v1 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Description The STGIPL14K60 intelligent power module provides a compact, high performance AC motor drive for a simple and rugged design. It mainly targets low power inverters for applications such as home appliances and air conditioners. It combines ST proprietary control ICs with the most advanced short circuit rugged IGBT system technology. Please refer to dedicated technical note TN0107 for mounting instructions. Applications ■ ■ 3-phase inverters for motor drives Home appliances, such as washing machines, refrigerators, air conditioners Table 1. Device summary Marking GIPL14K60 Package SDIP-38L Packaging Tube Order code STGIPL14K60 June 2010 Doc ID 15589 Rev 3 1/21 www.st.com 21 Contents STGIPL14K60 Contents 1 2 Internal block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . 3 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.1 3.1.2 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 5 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/21 Doc ID 15589 Rev 3 STGIPL14K60 Internal block diagram and pin configuration 1 Figure 1. Internal block diagram and pin configuration Internal block diagram Doc ID 15589 Rev 3 3/21 Internal block diagram and pin configuration STGIPL14K60 Table 2. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pin description Symbol OUTU Vboot U LINU HINU OP-U OPOUT U OP+U CINU OUTV Vboot V LINV HINV OP-V OPOUT V OP+V CINV OUTW Vboot W LINW HINW OP-W OPOUT W OP+W CINW VCC SD / OD GND T2 T1 NW W P NV V Description High side reference output for U phase Bootstrap voltage for U phase Low side logic input for U phase High side logic input for U phase Opamp inverting input for U phase Opamp output for U phase Opamp non inverting input for U phase Comparator input for U phase High side reference output for V phase Bootstrap voltage for V phase Low side logic input for V phase High side logic input for V phase Opamp inverting input for V phase Opamp output for V phase Opamp non inverting input for V phase Comparator input for V phase High side reference output for W phase Bootstrap voltage for W phase Low side logic input for W phase High side logic input for W phase Opamp inverting input for W phase Opamp output for W phase Opamp non inverting input for W phase Comparator input for W phase Low voltage power supply Shut down logic input (active low) / open drain (comparator output) Ground NTC thermistor terminal 2 NTC thermistor terminal 1 Negative DC input for W phase W phase output Positive DC input Negative DC input for V phase V phase output 4/21 Doc ID 15589 Rev 3 STGIPL14K60 Table 2. Pin 35 36 37 38 Internal block diagram and pin configuration Pin description (continued) Symbol P NU U P Positive DC input Negative DC input for U phase U phase output Positive DC input Description Figure 2. Pin layout (bottom view) Marking area Doc ID 15589 Rev 3 5/21 Electrical ratings STGIPL14K60 2 2.1 Electrical ratings Absolute maximum ratings Table 3. Symbol VPN VPN(surge) VCES ± IC(2) ± ICP (3) PTOT tscw Inverter part Parameter Supply voltage applied between P-NU, NV, NW Supply voltage (surge) applied between P-NU, NV, NW Collector emitter voltage (VIN(1) = 0) Each IGBT continuous collector current at TC = 25°C Each IGBT pulsed collector current Each IGBT total dissipation at TC = 25°C Short circuit withstand time, VCE = 0.5 V(BR)CES Tj = 125 °C, VCC = Vboot= 15 V, VIN (1)= 0÷5 V Value 450 500 600 14 30 35 5 Unit V V V A A W µs 1. Applied between HINi, LINi and GND for i = U, V, W 2. Calculated according to the iterative formula: T j ( max ) – T C I C ( T C ) = --------------------------------------------------------------------------------------------------------R thj – c × V CE ( sat ) ( max ) ( T j ( max ), I C ( T C ) ) 3. Pulse width limited by max junction temperature Table 4. Symbol VOUT VCC VCIN Vboot VIN VSD/OD dVout/dt Control part Parameter Output voltage applied between OUTU, OUTV, OUTW - GND (VCC = 15 V) Low voltage power supply Comparator input voltage Bootstrap voltage applied between Vboot i - OUTi for i = U, V, W Logic input voltage applied between HIN, LIN and GND Open drain voltage Allowed output slew rate Value Vboot - 21 to Vboot + 0.3 -0.3 to +21 -0.3 to VCC +0.3 -0,3 to 620 -0.3 to 15 -0.3 to 15 50 Unit V V V V V V V/ns 6/21 Doc ID 15589 Rev 3 STGIPL14K60 Electrical ratings Table 5. Symbol VISO Tj Total system Parameter Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60sec.) Operating junction temperature Value 2500 -40 to 125 Unit V °C 2.2 Thermal data Table 6. Symbol Rth(j-c) Thermal data Parameter Thermal resistance junction-case single IGBT Thermal resistance junction-case single diode Value 2.8 5 Unit °C/W °C/W Doc ID 15589 Rev 3 7/21 Electrical characteristics STGIPL14K60 3 Electrical characteristics (Tj = 25 °C unless otherwise specified) Table 7. Symbol Inverter part Value Parameter Test condition Min. VCC = VBoot = 15 V, VIN(1)= 0 ÷ 5 V, IC = 7 A VCC = VBoot = 15 V, VIN(1)= 0 ÷ 5 V, IC = 7 A, Tj= 125 °C VCE = 600 V VCC = Vboot = 15 V VIN(1) = 0 “logic state”, IC = 7 A Typ. 2.1 1.8 Max. 2.5 V Unit VCE(sat) Collector-emitter saturation voltage ICES VF Collector-cut off current (VIN(1)=0 “logic state”) Diode forward voltage - 100 2.1 µA V Inductive load switching time and energy ton tc(on) toff tc(off) trr Eon Eoff Turn-on time Crossover time (on) Turn-off time Crossover time (off) Reverse recovery time Turn-on switching losses Turn-off switching losses VDD = 300 V, VCC = Vboot = 15 V, VIN(1)= 0 ÷ 5 V, IC = 7 A (see Figure 3) 270 130 320 110 130 150 µJ 90 ns 1. Applied between HINi LINi and GND for i = U, V, W (LIN inputs are active-low). Note: ton and toff include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of IGBT itself under the internally given gate driving condition. 8/21 Doc ID 15589 Rev 3 STGIPL14K60 Figure 3. Switching time test circuit Electrical characteristics Figure 4. Switching time definition Doc ID 15589 Rev 3 9/21 Electrical characteristics STGIPL14K60 3.1 Table 8. Symbol Vcc_hys Vcc_thON Vcc_thOFF Iqccu Control part Low voltage power supply Parameter Vcc UV hysteresis Vcc UV turn ON threshold Vcc UV turn OFF threshold Undervoltage quiescent supply current VCC = 10 V SD/OD = 5 V; LIN = 5 V; HIN = 0, CIN = 0 Vcc = 15 V SD/OD = 5 V; LIN = 5 V HIN = 0, CIN = 0 0.5 0.54 Test conditions Min. 1.2 11.5 10 Typ. 1.5 12.0 10.5 450 Max. Unit V V V µA Iqcc Quiescent current Internal comparator (CIN) reference voltage 3.5 mA Vref 0.58 mV Table 9. Symbol VBS_hys VBS_thON VBS_thOFF IQBSU Bootstrapped voltage Parameter VBS UV hysteresis VBS UV turn ON threshold VBS UV turn OFF threshold Undervoltage VBS quiescent current VBS = 10 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 VBS = 15 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 LVG ON Test conditions Min. 1.2 10.6 9.0 Typ. 1.5 11.5 10.0 70 110 Max. Unit V V V µA IQBS RDS(on) VBS quiescent current Bootstrap driver on resistance 150 120 210 µA Ω Table 10. Symbol Vil Vih IHINh IHINl ILINl ILINh ISDh Logic inputs Parameter Low logic level voltage High logic level voltage HIN logic “1” input bias current HIN logic “0” input bias current LIN logic “0” input bias current LIN logic “1” input bias current SD logic “1” input bias current HIN = 15 V HIN = 0 V LIN = 0 V LIN = 15 V SD = 15 V 120 6 2.2 175 260 1 20 1 300 Test conditions Min. Typ. Max. 0.8 Unit V V µA µA µA µA µA 10/21 Doc ID 15589 Rev 3 STGIPL14K60 Table 10. Symbol ISDl Dt Electrical characteristics Logic inputs (continued) Parameter SD logic “0” input bias current Dead time Test conditions SD = 0 V see Figure 8 600 Min. Typ. Max. 3 Unit µA ns Table 11. Symbol Vio Iio Iib Vicm VOL VOH OPAMP characteristics (VCC = 15 V) Parameter Input offset voltage Input offset current Input bias current (1) Test condition Vic = 0 V, Vo = 7.5 V Min. Typ. Max. 6 Unit mV nA nA V 4 Vic = 0 V, Vo = 7.5 V 0 RL = 10 kΩ to VCC RL = 10 kΩ to GND Source, Vid = +1; Vo = 0 V Sink, Vid = -1; Vo = VCC 14 16 50 2.5 8 70 60 55 75 14.7 30 80 3.8 12 85 75 70 100 40 200 Input common mode voltage range Low level output voltage High level output voltage 150 mV V mA mA V/µs MHz dB dB dB Io Output short circuit current SR GBWP Avd SVR CMRR Slew rate Gain bandwidth product Large signal voltage gain Supply voltage rejection ratio Common mode rejection ratio Vi = 1 ÷ 4 V; CL = 100 pF; unity gain Vo = 7.5 V R L = 2 kΩ vs. VCC 1. The direction of input current is out of the IC. Table 12. Symbol Iio Vol td_comp SR Sense comparator characteristics (VCC = 15 V) Parameter Input bias current Open-drain low-level output voltage Comparator delay Slew rate Test conditions VCP+ = 1 V Iod = - 3 mA SD/OD pulled to 5 V through 100 kΩ resistor CL = 180 pF; Rpu = 5 kΩ Min. 90 60 Typ. Max. 3 0.5 130 Unit µA V ns V/µsec Doc ID 15589 Rev 3 11/21 Electrical characteristics STGIPL14K60 Table 13. Truth table Logic input (VI) Output HIN X H L L H LVG L L L H L HVG L L L L H Condition SD/OD Shutdown enable half-bridge tri-state Interlocking half-bridge tri-state 0 ‘’logic state” half-bridge tri-state 1 “logic state” low side direct driving 1 “logic state” high side direct driving L H H H H LIN X L H L H Note: Figure 5. X: don’t care. Maximum IC(RMS) current vs. switching frequency (1) Figure 6. Maximum IC(RMS) current vs. fsine(1) 1. Simulated curves refer to typical IGBT parameters and maximum Rthj-c. 12/21 Doc ID 15589 Rev 3 STGIPL14K60 Electrical characteristics 3.1.1 NTC thermistor Table 14. Symbol R25 R125 NTC thermistor Parameter Resistance Resistance B-constant Operating temperature Test conditions TC = 25°C TC = 125°C TC = 25°C -40 Min. Typ. Max. Unit. 5 300 3435 125 kΩ Ω k °C B T Equation 1: resistance variation vs temperature 1 1B ⎛ -- – ------------ ⎞ ⎝ T 298k⎠ R ( T ) = R 25 ⋅ e Figure 7. NTC resistance vs temperature Doc ID 15589 Rev 3 13/21 Electrical characteristics STGIPL14K60 3.2 Waveforms definitions Figure 8. Dead time and interlocking waveforms definitions LIN LVG HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) INTE INTE CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME RLO CK RLO CK HIN ING ING DTLH gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DTHL LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DTHL LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DTHL LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DTHL (*) HIN and LIN can be connected together and driven by just one control signal 14/21 Doc ID 15589 Rev 3 STGIPL14K60 Smart shutdown function 4 Smart shutdown function The STGIPL14K60 integrates a comparator for fault sensing purposes. The comparator non-inverting input (CIN) can be connected to an external shunt resistor in order to implement a simple over-current protection function. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the halfbridge in tri-state. In the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a RC network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. The time delay between the fault and the outputs turn-off is no more dependent on the RC values of the external network connected to the shutdown pin. At the same time the internal logic turns on the open-drain output and holds it on until the shutdown voltage goes below the logic input lower threshold. Finally the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external RC network. Figure 9. Smart shutdown timing waveforms comp Vref CP+ PROTECTION HIN/LIN HVG/LVG SD/OD upper threshold lower threshold 1 2 open drain gate (internal) real disable time Fast shut down: the driver outputs are set in SD state immediately after the comparator triggering even if the SD signal has not yet reach the lower input threshold TIME CONSTANTS 1 2 = (RON_OD // RSD) CSD = RSD CSD SHUT DOWN CIRCUIT VBIAS RSD FROM/TO CONTROLLER SD/OD SMART SD LOGIC CSD RON_OD Doc ID 15589 Rev 3 15/21 Applications information STGIPL14K60 5 Applications information Figure 10. Typical application circuit 16/21 Doc ID 15589 Rev 3 STGIPL14K60 Applications information 5.1 Recommendations ● ● ● ● ● To prevent the input signals oscillation, the wiring of each input should be as short as possible. By integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler is possible. Each capacitor should be located as nearby the pins of IPM as possible. Low inductance shunt resistors should be used for phase leg current sensing. Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see Section 4: Smart shutdown function for detailed info). Recommended operating conditions Value Parameter Supply Voltage Conditions Min. VPN VCC VBS tdead fPWM Applied between P-Nu,Nv,Nw 13.5 Typ. 300 15 Max. 400 18 18 1 20 V V V µs kHz Unit ● Table 15. Symbol Control supply voltage Applied between VCC-GND High side bias voltage Blanking time to prevent Arm-short PWM input signal Applied between VBOOTi-OUTi for i=U,V,W For each input signal -40°C < Tc < 100°C -40°C < Tj < 125°C Doc ID 15589 Rev 3 17/21 Package mechanical data STGIPL14K60 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Please refer to dedicated technical note TN0107 for mounting instructions. Table 16. SDIP-38L mechanical data mm Dimensions Min. A A1 A2 A3 B B1 B2 B3 B4 C C1 C2 e e1 e2 e3 e4 e5 e6 F F1 R1 T1 49.1 44.1 1.37 1.23 24 27.1 28.6 11.25 12.05 5 6.40 10.41 1.1 3.2 5.8 4.6 5.6 6.3 4.5 0.8 0.35 1.3 0.45 0.55 1.3 3.4 6.0 4.8 5.8 6.5 4.7 1.0 0.5 27.6 29.1 Typ. Max. 50.1 45.1 1.47 2.23 25 28.1 29.6 12.45 13.25 6 7.40 11.41 1.5 3.6 6.2 5.0 6.0 6.7 4.9 1.2 0.65 2.1 0.65 18/21 Doc ID 15589 Rev 3 STGIPL14K60 Figure 11. SDIP-38L drawing dimensions Package mechanical data 8142868_F Doc ID 15589 Rev 3 19/21 Revision history STGIPL14K60 7 Revision history Table 17. Date 16-Apr-2009 s Document revision history Revision 1 Initial release Inserted Figure 5, Figure 6 and Section 4: Smart shutdown function. Updated Section 3.1: Control part and package mechanical data, Section 6. Minor text changes to improve readability. Document status promoted from preliminary data to datasheet. Updated Table 7: Inverter part, Figure 5: Maximum IC(RMS) current vs. switching frequency and Figure 6: Maximum IC(RMS) current vs. fsine(1). Changes 29-Mar-2010 2 14-Jun-2010 3 20/21 Doc ID 15589 Rev 3 STGIPL14K60 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 15589 Rev 3 21/21
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